Substrate Contains Silicon Or Silicon Compound Patents (Class 216/99)
  • Patent number: 10654460
    Abstract: A novel, particularly rationally designed, modular parking brake actuator for an electric drum brake system. An axle A1 from the motor, including a screw gear pinion coupled in a rotationally fixed manner, and an axle of the spindle arrangement, including a screw gear which is coupled in a rotationally fixed manner to the drive nut, define under a deflection of 90° a single wheel gearbox stage of the parking brake actuator.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: May 19, 2020
    Inventors: Thomas Winkler, Jürgen Balz, Marco Froschauer, Jürgen Bauer, Patrick Walter, Stefan Heinz, Philipp Merkel, Pejman Bijanzadeh
  • Patent number: 10381526
    Abstract: The present invention provide an orderly patterned remote phosphor crystal material and method for preparation the material and its application, which adopts short-pulse laser to make micro-structure arrays on the surface of phosphor crystal material to enhance the light extraction efficiency of the LED based on the material. The present invention overcomes the phosphor crystal material's properties of hard and dry/wet etching resistance and simplifies the processing steps, which accelerate the processing and improve the producing efficiency. The present invention is able to be performed under room temperature and environment friendly and the micro-structure is stable, which has broad application prospects in white LED field.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: August 13, 2019
    Inventors: Yufeng Li, Shuai Wang, Feng Yun
  • Patent number: 9852921
    Abstract: A substrate treating apparatus and a method of treating a substrate, the apparatus including a substrate treater that treats a substrate using a chemical solution, the chemical solution including a phosphoric acid aqueous solution and a silicon compound; and a chemical solution supplier that supplies the chemical solution to the substrate treating unit, wherein the chemical solution supplier includes a concentration measurer that measures concentrations of the chemical solutions, the concentration measurer including a first concentration measurer that measures a water concentration of the chemical solution; and a second concentration measurer that measures a silicon concentration of the chemical solution.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: December 26, 2017
    Inventors: Kyoung Hwan Kim, Ingi Kim, Mihyun Park, Young-Hoo Kim, Ui-soon Park, Jung-Min Oh, Kuntack Lee, Hyosan Lee
  • Patent number: 9691628
    Abstract: A method for selectively removing silicon nitride is described. In particular, the method includes providing a substrate having a surface with silicon nitride exposed on at least one portion of the surface and SiGex (x is greater than or equal to zero) exposed on at least another portion of the surface, and dispensing an oxidizing agent onto the surface of the substrate to oxidize the exposed SiGex. Thereafter, the method includes dispensing a silicon nitride etching agent as a liquid stream onto the surface of the substrate to remove at least a portion of the silicon nitride.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: June 27, 2017
    Assignee: TEL FSI, INC.
    Inventors: Jeffery W. Butterbaugh, Anthony S. Ratkovich
  • Patent number: 9399734
    Abstract: An etching solution, a process of producing the same, and an etching process using the same, in which the etching solution includes hydrofluoric acid (a), ammonium fluoride (b), and salt (c) formed between hydrogen fluoride and a base having a boiling point higher than that of ammonia; the concentration of ammonium fluoride (b) is not higher than 8.2 mol/kg, and the total amount of ammonium fluoride (b) and salt (c) formed between hydrogen fluoride and a base having a boiling point higher than that of ammonia is not less than 9.5 mol/kg.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: July 26, 2016
    Inventors: Mitsushi Itano, Shingo Nakamura, Takehiko Kezuka, Daisuke Watanabe
  • Patent number: 9397177
    Abstract: A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor structure includes a first gate channel region having a first gate length, and the second semiconductor structure including a second gate channel region having a second gate length that is greater than the first gate length. The method further includes depositing a work function metal layer in each of a first gate void formed at the first gate channel region and a second gate void formed at the second gate channel region. The method further includes depositing a semiconductor masking layer on the work function metal layer, and simultaneously etching the silicon masking layer located at the first and second gate channel regions to re-expose the first and second gate voids. A low-resistive metal is deposited in the first and second gate voids to form low-resistive metal gate stacks.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: July 19, 2016
    Inventors: Michael P. Chudzik, Siddarth A. Krishnan, Unoh Kwon
  • Patent number: 9318338
    Abstract: A method for fabricating a semiconductor device is provided. The method includes the following steps. Firstly, a substrate having a nitride layer and a platinum (Pt)-containing nickel (Ni)-semiconductor compound layer is provided. Then the nitride layer and the Pt are removed in situ with a chemical solution including a sulfuric acid component and a phosphoric acid component.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: April 19, 2016
    Inventors: Bor-Shyang Liao, Tsung-Hsun Tsai, Kuo-Chih Lai, Pin-Hong Chen, Chia-Chang Hsu, Shu-Min Huang, Min-Chung Cheng, Chun-Ling Lin
  • Patent number: 9177822
    Abstract: An etching method. The method includes etching a first plurality of silicon wafers in a first enchant, each silicon wafer having SiO2 and Si3N4 deposited thereon, where the etching includes dissolving a quantity of the SiO2 and a quantity of the Si3N4 in the first etchant. A quantity of insoluble SiO2 precipitates. A ratio of a first etch rate of Si3N4 to a first etch rate of SiO2 is determined to be less than a predetermined threshold. A portion of the first etchant is combined with a second etchant to form a conditioned etchant. A second plurality of silicon wafers is etched in the conditioned etchant. A ratio of a second etch rate of Si3N4 to a second etch rate of SiO2 in the conditioned etchant is greater than the threshold. A method for exchanging an etching bath solution and a method for forming a selective etchant are also disclosed.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 3, 2015
    Inventors: Russell Herbert Arndt, Paul F. Findeis, Charles Jesse Taft
  • Patent number: 9040431
    Abstract: A method for processing a silicon wafer is provided. The method includes allowing an etchant to flow along a surface of the silicon wafer to form a line in which a plurality of apertures are arranged in a flow direction of the etchant from an upstream side to a downstream side. The apertures arranged in the line include a first aperture formed on the most upstream side and a second aperture formed downstream of the first aperture in the flow direction of the etchant. The first aperture and the second aperture are subjected to different processes after being formed.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: May 26, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hirohisa Fujita, Shuji Koyama, Keiji Matsumoto, Kenta Furusawa
  • Patent number: 9034216
    Abstract: A wet-chemical method of producing a black silicon substrate. The method comprising soaking single crystalline silicon wafers in a predetermined volume of a diluted inorganic compound solution. The substrate is combined with an etchant solution that forms a uniform noble metal nanoparticle induced Black Etch of the silicon wafer, resulting in a nanoparticle that is kinetically stabilized. The method comprising combining with an etchant solution having equal volumes acetonitrile/acetic acid:hydrofluoric acid:hydrogen peroxide.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: May 19, 2015
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Vernon Yost, Hao-Chih Yuan, Matthew Page
  • Patent number: 9017568
    Abstract: A method for performing an oxide removal process is described. The method includes providing a substrate having an oxide layer, and preparing a patterned mask layer on the oxide layer, wherein the patterned mask layer has a pattern exposing at least a portion of the oxide layer. An HF treatment of the substrate is performed to transfer the pattern at least partially through the oxide layer, wherein the HF treatment exposes a silicon surface. Following the performing of the HF treatment, a surface property of the silicon surface is modified, wherein the modifying includes administering at least one oxidizing agent to contact the silicon surface to cause chemical oxidation of the silicon surface. And, following the modifying of the surface property, at least a portion of the patterned mask layer or a residual portion of the patterned mask layer is removed.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: April 28, 2015
    Assignee: TEL FSI, Inc.
    Inventor: Steven L. Nelson
  • Patent number: 9017561
    Abstract: A piezo-resistive MEMS resonator comprising an anchor, a resonator mounted on the anchor, an actuator mounted to apply an electrostatic force on the resonator and a piezo-resistive read-out means comprising a nanowire coupled to the resonator.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: April 28, 2015
    Assignee: NXP, B.V.
    Inventors: Gerhard Koops, Jozef Thomas Martinus van Beek
  • Patent number: 9011702
    Abstract: One of objects is to reduce the effect caused by the volume expansion of an active material. An embodiment is a method for manufacturing an electrode for a power storage device which includes an active material over one of surfaces of a current collector. The active material is formed by forming a conductive body functioning as the current collector; forming a mixed layer including an amorphous region and a microcrystalline region over one of surfaces of the conductive body; and etching the mixed layer selectively, so that a part of or the whole of the amorphous region is removed and the microcrystalline region is exposed. Thus, the effect caused by the volume expansion of the active material is reduced.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: April 21, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kazutaka Kuriki, Junpei Momo, Rie Matsubara
  • Patent number: 8999182
    Abstract: A method for manufacturing a liquid discharge head includes a step of preparing a first substrate having an energy generating element at a front surface side thereof; a step of forming a wall member, which is to become a wall for a liquid flow passage, at the front surface side of the first substrate; a step of forming a mask having an opening on the wall member and forming a second substrate, which is composed of silicon and is to become an orifice plate, on the mask; and a step of forming a liquid supply port in the first substrate and a liquid discharge port in the second substrate by supplying an etchant from a back surface side of the first substrate, the back surface being a surface opposite the front surface.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: April 7, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroyuki Abo, Keiji Matsumoto
  • Patent number: 8999180
    Abstract: A process of manufacturing a solar cell is provided. The process comprising the steps of: i) ink jet printing an alkali removable water insoluble hot melt ink jet ink onto a substrate comprising a silicon wafer to form a resist image on the substrate; ii) etching or plating the substrate in an aqueous acid medium; and iv) removing the resist image with an aqueous alkali.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: April 7, 2015
    Assignee: Sun Chemical Corporation
    Inventor: Nigel Anthony Caiger
  • Patent number: 8986559
    Abstract: Compositions and methods for chemical texturing a surface of a polycrystalline silicon wafer to be used in the manufacture of solar cells provide increased efficiency in the manufacture and operation of solar cells. The compositions and methods disclosed herein include first and second components, wherein the first component is a UKON etch composition, including a hydrofluoric acid/nitric acid mixture and water, while the second component includes a silicon wafer texturing enhancer (SWTE).
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: March 24, 2015
    Assignee: Avantor Performance Materials, Inc.
    Inventors: Nicolas Hildenbrand, Joannes Theodorus Valentinus Hoogboom, Michiel Scheffer, Raymond Albertus Johannes Ten Broeke
  • Patent number: 8974685
    Abstract: Provided is a fine-processing agent which, when fine-processing a laminated film stacked at least with a silicon dioxide film and a silicon nitride film, can selectively fine-process the silicon dioxide film. Also provided is a fine-processing method utilizing the fine-processing agent. The fine-processing agent is characterized by including: (a) 0.01-15.0 weight % hydrogen fluoride and/or 0.1-40.0 weight % ammonium fluoride, (b) water, and (c) 0.001-10.00 weight % water-soluble polymer selected from among a group consisting of acrylic acid, ammonium acrylate, acrylic acid ester, acrylamide, styrenesulfonic acid, ammonium styrenesulfonate, and styrenesulfonic acid ester.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: March 10, 2015
    Assignee: Stella Chemifa Corporation
    Inventors: Masayuki Miyashita, Takanobu Kujime, Keiichi Nii
  • Publication number: 20150060405
    Abstract: A method is provided for producing a microstructure. The method includes the first step of forming a supporting layer on a base substrate including a silicon substrate provided with recessed sections at a first surface thereof and a metal structure filling the recessed sections so as to come in contact with the metal structure at the first surface, the second step of forming a structure including the metal structure and the supporting layer by selectively etching the silicon substrate to expose at least the surface of the metal structure opposite the surface in contact with the supporting layer from the silicon substrate, and the third step of selectively etching the supporting layer of the metal structure.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 5, 2015
    Inventor: Takayuki Teshima
  • Patent number: 8962492
    Abstract: A method to thin an initial silicon-on-insulator substrate that has a layer of silicon oxide buried between a silicon carrier substrate and a silicon surface layer.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: February 24, 2015
    Assignee: Soitec
    Inventors: Patrick Reynaud, Ludovic Ecarnot, Khalid Radouane
  • Publication number: 20150048053
    Abstract: A layer of a metal selected from titanium, niobium, tungsten, molybdenum, ruthenium, rhodium, arsenic, aluminum and gallium, an oxide of the metal, a nitride of the metal, silicon nitride, hafnium nitride, tantalum nitride, or an alloy of these metals, the layer being provided on an underlying base material selected from glass, silicon, copper and nickel, is selectively etched with an alkaline etching solution containing a predefined complexing agent.
    Type: Application
    Filed: September 3, 2012
    Publication date: February 19, 2015
    Applicant: JCU CORPORATION
    Inventors: Christopher Cordonier, Mitsuhiro Nabeshima, Shingo Kumagai, Naoki Takahashi
  • Patent number: 8956544
    Abstract: A method for manufacturing a micromechanical structure, and a micromechanical structure. The micromechanical structure encompasses a first micromechanical functional layer, made of a first material, that comprises a buried conduit having a first end and a second end; a micromechanical sensor structure having a cap in a second micromechanical functional layer that is disposed above the first micromechanical functional layer; an edge region in the second micromechanical functional layer, such that the edge region surrounds the sensor structure and defines an inner side containing the sensor structure and an outer side facing away from the sensor structure; such that the first end is located on the outer side and the second end on the inner side.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: February 17, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Johannes Classen, Jochen Reinmuth, Sebastian Guenther, Pia Bustian-Todorov
  • Publication number: 20150045885
    Abstract: A water dispersible, biocompatible, non-toxic, seedless Group IV nanowire having an etched surface and surface oxide is provided. Also provided is a method of forming water dispersible seedless Group IV nanowires, comprising the steps of providing pristine seedless Group IV nanowires, and reacting the nanowires with a solution of an acidic amino acid to etch the nanowires and promote the formation of a water dispersible oxide layer through the formation of etched nanowires.
    Type: Application
    Filed: August 6, 2014
    Publication date: February 12, 2015
    Inventors: Patrick Kiely, Kevin Ryan, Michael Bezuidenhout
  • Patent number: 8940644
    Abstract: A method for manufacturing a semiconductor substrate product having: providing an etching liquid containing water, a hydrofluoric acid compound and an organic solvent, and applying the etching liquid to a semiconductor substrate, the semiconductor substrate having a silicon layer and a silicon oxide layer, the silicon layer containing an impurity, and thereby selectively etching the silicon oxide layer.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: January 27, 2015
    Assignee: FUJIFILM Corporation
    Inventors: Atsushi Mizutani, Tetsuya Kamimura, Akiko Yoshii, Tetsuya Shimizu
  • Patent number: 8940178
    Abstract: A method of texturizing a silicon substrate comprising a) contacting the substrate with an etching solution comprising glycolic acid, b) etching a surface of the substrate thereby forming disruptions in said surface of the substrate, and c) removing the etching solution to yield a texturized substrate, said texturized substrate having a plurality of disruptions in at least one surface with a surface density of disruptions of a minimum of 60 disruptions in a 400 micron square area.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: January 27, 2015
    Assignee: E I du Pont de Nemours and Company
    Inventors: Seung Jin Lee, Hee Soo Yeo
  • Publication number: 20150021293
    Abstract: A method for providing a nanopattern of periodically ordered metal oxide nanostructures on a substrate is described. The method comprises the steps of providing a microphase separated block copolymer as a thin film on a substrate, the block copolymer comprising a first polymer having an affinity for a cations of the metal and a second polymer having a lower affinity for the cations than the first polymer, and selectively incorporating a salt of the metal cation into the first polymer of the block copolymer by means of a solvation process prior to or after formation of the microphase separated block copolymer. The block copolymer film is then treated to oxidise the metal ion salt and remove the polymers leaving a nanopattern of metal oxide nanostructures on the substrate.
    Type: Application
    Filed: November 16, 2012
    Publication date: January 22, 2015
    Inventors: Michael Morris, Dipu Borah, Tandra Ghoshal, Parvaneh Mokarian
  • Patent number: 8936729
    Abstract: According to one embodiment, a planarizing method is proposed. In the planarizing method, a surface to be processed of an object to be processed including a silicon oxide film is planarized in a processing solution by bringing the surface to be processed into contact with or close proximity with the surface of a solid-state plate on which fluorine is adsorbed. The bonding energy between fluorine and the solid-state plate is lower than that between fluorine and silicon.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: January 20, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akifumi Gawase, Yukiteru Matsui
  • Publication number: 20150013481
    Abstract: A micro-scale pendulum structure. The structure includes a membrane having a peripheral support portion and an inner portion, and a micro-scale pendulum carried by the inner portion of the membrane.
    Type: Application
    Filed: January 26, 2012
    Publication date: January 15, 2015
    Inventors: James Elmer Abbott, JR., John L. Williams, Pavel Kornilovich
  • Patent number: 8932952
    Abstract: Disclosed is a method for polishing a silicon wafer, wherein a surface to be polished of a silicon wafer is rough polished, while supplying a polishing liquid, which is obtained by adding a water-soluble polymer to an aqueous alkaline solution that contains no free abrasive grains, to a polishing cloth. Consequently, the surface to be polished can be polished at high polishing rate and the flatness of the edge portion including roll-off and roll-up can be controlled.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: January 13, 2015
    Assignee: Sumco Corporation
    Inventors: Shinichi Ogata, Ryuichi Tanimoto, Ichiro Yamasaki, Shunsuke Mikuriya
  • Publication number: 20140356623
    Abstract: Provided are organosilica composites based on bis(3-triethoxysilylpropyl)tetrasulfide (TESPTS) or bis(3-triethoxysilylpropyl)disulfide (TESPDS) and containing octadecyltrimethoxy silane (C18TMS) and cetyltrimethylammonium bromide (CTAB), and a method for preparing hollow or porous carbon structures and silica structures using the same. According to the present disclosure, it is possible to obtain hollow or porous carbon structures and silica structures in a more simple and cost-efficient manner. Thus, the resultant structures have a high surface area and a large mesopore volume, so that they may serve as catalyst carriers for fuel cells capable of loading metal catalyst particles having a smaller particle size in a larger amount and in a more homogeneously dispersed state.
    Type: Application
    Filed: May 29, 2013
    Publication date: December 4, 2014
    Inventor: Jong-Sung Yu
  • Patent number: 8900472
    Abstract: A liquid agent for the surface treatment of monocrystalline wafers, which contains an alkaline etching agent and also at least one low-volatile organic compound. Systems of this type can be used both for the cleaning, damage etch and texturing of wafer surfaces in a single etching step and exclusively for the texturing of silicon wafers with different surface quality, whether it now be wire-sawn wafers with high surface damage or chemically polished surfaces with minimum damage density.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: December 2, 2014
    Assignee: Fraunhofer-Gesellschaft zur Föerderung der angewandten Forschung E.V.
    Inventors: Kuno Mayer, Mark Schumann, Daniel Kray, Teresa Orellana Peres, Jochen Rentsch, Martin Zimmer, Elias Kirchgässner, Eva Zimmer, Daniel Biro, Arpad Mihai Rostas, Filip Granek
  • Patent number: 8894868
    Abstract: A method of forming an aperture (e.g., a through via, a blind via, a trench, an alignment feature, etc.) within a substrate includes irradiating a substrate with a laser beam to form a laser-machined feature having a sidewall. The laser-machined feature is then processed to change at least one characteristic (e.g., the sidewall surface roughness, diameter, taper, aspect ratio, cross-sectional profile, etc.) of the laser-machined feature. The laser-machined feature can be processed to form the aperture by performing an isotropic wet-etch process employing an etchant solution containing HNO3, HF and, optionally acetic acid.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: November 25, 2014
    Assignee: Electro Scientific Industries, Inc.
    Inventors: Andy Hooper, Daragh Finn, Tim Webb, Lynn Sheehan, Kenneth Pettigrew, Yu Chong Tai
  • Patent number: 8889562
    Abstract: Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ying Zhang
  • Patent number: 8883033
    Abstract: A method for removing silicon nitride material includes following steps. A substrate having at least a gate structure formed thereon is provided, and at least a silicon nitride hard mask is formed on top of the gate structure. A first removal is performed to remove a portion of the silicon nitride hard mask with a first phosphoric acid (H3PO4) solution. A second removal is subsequently performed to remove remnant silicon nitride hard mask with a second phosphoric acid solution. The first removal and the second removal are performed in-situ. A temperature of the second phosphoric acid solution is lower than a temperature of the first phosphoric acid solution.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: November 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Sheng Chen, Shin-Chi Chen, Chih-Yueh Li, Ted Ming-Lang Guo, Bo-Syuan Lee, Tsung-Hsun Tsai, Yu-Chin Cheng
  • Patent number: 8883032
    Abstract: A method of surface treatment for zirconium oxide implants and the etching formula for the same are disclosed. The processes are carried out at room temperature. The average surface roughness Ra and the standard deviation of the implant are measured showing significant improvement while comparing with the un-treated sample and the hydrofluoric acid treated samples. The average contact angle is provided showing an almost hydrophilic surface after etched by the formula according to the present invention.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: November 11, 2014
    Inventors: Sea-Fue Wang, Chung-Kuang Yang, Jen-Chang Yang, Sheng-Yang Lee
  • Patent number: 8877072
    Abstract: A method to fabricate a hierarchical graduated-branched structure that grows in a three-dimensional pattern down to fractal-branching, nano-size level is detailed. The fractal patterning is accomplished on a three-dimensional (i.e., non-planar) surface, by exposing the surface to a properly focused particle beam, which causes the spontaneous growth of graduated branches all over the surface. The structure can be fabricated with a single material and the fractal-patterning is done in a one step process. No addition of material is required for the formation of each branch. The fractal graduated branching structure can then be molded in order to produce replicas.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: November 4, 2014
    Inventors: Ranjana Sahai, Paolo Corradi
  • Patent number: 8846536
    Abstract: Provided herein are integration-compatible dielectric films and methods of depositing and modifying them. According to various embodiments, the methods can include deposition of flowable dielectric films targeting specific film properties and/or modification of those properties with an integration-compatible treatment process. In certain embodiments, methods of depositing and modifying flowable dielectric films having tunable wet etch rates and other properties are provided. Wet etch rates can be tuned during integration through am integration-compatible treatment process. Examples of treatment processes include plasma exposure and ultraviolet radiation exposure.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: September 30, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Nerissa Draeger, Karena Shannon, Bart van Schravendijk, Kaihan Ashtiani
  • Publication number: 20140284309
    Abstract: A cement including: an alkali silicate; an organic silicate; a compound selected from a group consisting of Pozzolanic compounds and synthetic Pozzolanic substitutes; a metal oxide; an activator.
    Type: Application
    Filed: March 24, 2014
    Publication date: September 25, 2014
    Inventor: Trevor Cyril Waters
  • Patent number: 8828260
    Abstract: A substrate processing method for forming a space extending along a predetermined line in a silicon substrate includes a first step of converging a laser light which is an elliptically-polarized light having an ellipticity other than 1 at the substrate so as to form a plurality of modified spots within the substrate along the line and produce a modified region including the modified spots, and a second step of anisotropically etching the substrate so as to advance an etching selectively along the modified region and form the space in the substrate. In the first step, the light is converged at the substrate such that a moving direction of the light with respect to the substrate and a direction of polarization of the light form an angle of 45° or greater therebetween, and the modified spots are made align in one row along the line.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: September 9, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Hideki Shimoi, Keisuke Araki
  • Patent number: 8815380
    Abstract: A method for texturing an alkali alumina silicate glass substrate includes cleaning the glass substrate with at least one surfactant and etching the glass substrate using a caustic solution. The percentage of caustic solution is provided by controlling a fluid flow and temperature to control the depth of the etching. The method also includes acid cleaning the etched glass substrate to remove glass residuals and surfactants and chemically strengthening the etched and cleaned substrate.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: August 26, 2014
    Assignee: Rockwell Collins, Inc.
    Inventors: Paul R. Nemeth, John W. Sackfield, Gary N. Prior, David D. Pohl
  • Patent number: 8815104
    Abstract: A method (300) for etching a silicon surface (116) to reduce reflectivity. The method (300) includes electroless deposition of copper nanoparticles about 20 nanometers in size on the silicon surface (116), with a particle-to-particle spacing of 3 to 8 nanometers. The method (300) includes positioning (310) the substrate (112) with a silicon surface (116) into a vessel (122). The vessel (122) is filled (340) with a volume of an etching solution (124) so as to cover the silicon surface (116). The etching solution (124) includes an oxidant-etchant solution (146), e.g., an aqueous solution of hydrofluoric acid and hydrogen peroxide. The silicon surface (116) is etched (350) by agitating the etching solution (124) with, for example, ultrasonic agitation, and the etching may include heating (360) the etching solution (124) and directing light (365) onto the silicon surface (116). During the etching, copper nanoparticles enhance or drive the etching process.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: August 26, 2014
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Fatima Toor, Howard Branz
  • Publication number: 20140234198
    Abstract: Provided is an etching method including: (1) bringing a material containing at least one organic compound having an N—F bond into contact with the surface of a solid material; and (2) a step of heating the solid material; whereby etching can be performed safely and in a simple manner, at a higher etching rate, without the use of a high-environmental-load gas that causes global warming or highly reactive and toxic fluorine gas or hydrofluoric acid. The etching method may further include: (3) a step of exposing the solid material to light from the side of the material containing at least one organic compound having an N—F bond; and (4) a step of removing the material containing at least one organic compound having an N—F bond together with the residue remained between said material and the solid material.
    Type: Application
    Filed: August 10, 2012
    Publication date: August 21, 2014
    Inventors: Mizuho Morita, Junichi Uchikoshi, Kentaro Tsukamoto, Takabumi Nagai, Kenji Adachi
  • Patent number: 8809194
    Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a SiOCl-containing layer on an exposed surface of the spacer material to form a spacer protection layer.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: August 19, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Alok Ranjan, Kaushik Arun Kumar
  • Patent number: 8795542
    Abstract: A method to remove excess material during the manufacturing of semiconductor devices includes providing a semiconductor wafer comprising silicon nitride deposited thereon and applying a chemical solution to the semiconductor wafer, wherein the chemical solution comprises a combination of sulfuric acid and deionized water.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: August 5, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Edwin Adhiprakasha
  • Patent number: 8790531
    Abstract: A high purity, non-toxic, environmentally friendly method for anisotropically etching single crystal silicon and etching polysilicon, suitable for microelectronics, optoelectronics and microelectromechanical (MEMS) device fabrication, using high purity aqueous ammonium hydroxide (NH4OH) solution generated at the point of use, is presented. The apparatus of the present invention supports generation of high purity aqueous NH4OH solution from ammonia NH3 gas dissolved into distilled/deionized water and maintained in equilibrium with an overpressure of NH3, within a hermetically enclosed chamber at the optimal temperature between 70-90° C., preventing evaporation of NH3 gas from aqueous NH4OH solution for achieving a high anisotropic etching rate. Other liquid anisotropic etching methods for silicon may use tetramethylammonium hydroxide (TMAH).
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: July 29, 2014
    Inventor: Alvin Gabriel Stern
  • Patent number: 8772174
    Abstract: A method for treating silicon to form pillars, especially for use as the active anode material in Li-ion batteries, is disclosed. The process is simple to operate on a commercial scale since it uses a solution containing only a small number of ingredients whose concentration needs to be controlled and it can be cheaper to operate than previous processes. The solution includes: 0.01 to 5M HF 0.002 to 0.2M of metal ions capable of nucleating on and forming a porous layer comprising regions of elemental metal on the silicon surface; 0.001 to 0.7M of an oxidant selected from the group O2, O3, H2O2, the acid, ammonium or alkali metal salt of NO3?, S2O82?, NO2?, B4O72? and ClO4? or a mixture thereof. The treated silicon is suitably removed from the solution.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: July 8, 2014
    Assignee: Nexeon Ltd.
    Inventors: Mino Green, Feng-Ming Liu, Yuxiong Jiang, Valerie Elizabeth Dawn Stevens, Benjamin Odarkwei Mills-Lamptey
  • Patent number: 8771531
    Abstract: A substrate for a liquid ejection head, including: forming a sacrifice layer on a first surface of a silicon substrate in a region in which a liquid supply port is to open, the sacrifice layer containing aluminum which is selectively etched with respect to the silicon substrate; forming an etching mask on a second surface which is a rear surface of the first surface of the silicon substrate, the etching mask having an opening corresponding to the sacrifice layer; a first etching step of etching the silicon substrate by using the etching mask as a mask and by using a first etchant containing 8 mass % or more and less than 15 mass % of tetramethylammonium hydroxide; and after the first etching step, a second etching step of removing the sacrifice layer by using a second etchant containing 15 mass % or more and 25 mass % or less of tetramethylammonium hydroxide.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: July 8, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenta Furusawa, Shuji Koyama, Hiroyuki Abo, Taichi Yonemoto
  • Patent number: 8765001
    Abstract: Monocrystalline semiconductor substrates are textured with alkaline solutions to form pyramid structures on their surfaces to reduce incident light reflectance and improve light absorption of the wafers. The alkaline baths include hydantoin compounds and derivatives thereof in combination with alkoxylated glycols to inhibit the formation of flat areas between pyramid structures to improve the light absorption.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: July 1, 2014
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Michael P. Toben, Robert K. Barr, Corey O'Connor
  • Patent number: 8759231
    Abstract: The present disclosure includes a texture formulation that includes an aliphatic diol, an alkaline compound and water which provides a consistent textured region across a silicon surface suitable for solar cell applications. Processes for texturing a crystalline silicon substrate using these formulations are also described.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: June 24, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Zhi-Wen Sun, Sagar Vijay
  • Patent number: 8758633
    Abstract: Disclosed is a method for fabricating nanofluidic channels having a height of from about 1 nm to about 10 nm. Generally, the method includes formation of doped silicon parallel strips in a silicon substrate, formation of a native oxide layer on the substrate, and etching of the native oxide layer at one of the strips to form a channel of a depth of between about 1 nm and about 10 nm. The method also includes bonding a second wafer to the surface, the second wafer including through etched windows to provide probe contacts to two of the parallel strips during use. These parallel strips provide high-frequency transmission lines in the device that can provide broadband dielectric spectroscopy measurement within the nanochannels.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: June 24, 2014
    Assignee: Clemson University
    Inventors: Pingshan Wang, Chunrong Song
  • Patent number: RE44995
    Abstract: A method for producing a semiconductor component includes forming an n-doped layer in a p-doped layer of the semiconductor component, wherein the n-doped layer comprises at least one of: a sieve-like layer or a network-like layer. The method also includes porously etching the p-doped layer between the material of the n-doped layer to form a top electrode, and forming a cavity below the n-doped layer.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: July 8, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Hubert Benzel, Heribert Weber, Hans Artmann, Frank Schaefer