Abstract: A scintillator panel includes: a first flexible support body having a first surface and a second surface on a side opposite to the first surface; a scintillator layer formed on the first surface and containing a plurality of columnar crystals; a second flexible support body provided on the second surface; an inorganic layer provided on the second flexible support body so as to be interposed between the second surface and the second flexible support body; and a first adhesive layer bonding the second surface and the inorganic layer to each other. A radiation detector includes: the scintillator panel; and a sensor panel including a photoelectric conversion element, in which the scintillator panel is provided on the sensor panel such that the first surface is on the sensor panel side with respect to the second surface.

Abstract: A cover glass includes: a glass substrate having a convex and concave shape formed on at least one of surfaces thereof by an antiglare treatment; and an antireflection film disposed on the surface of the glass substrate, the surface having the convex and concave shape. In the cover glass, a difference ?a* in a* value between any two points within a surface of the cover glass on the side where the antireflection film is present and a difference ?b* in b* value between any two points within the surface of the cover glass on the side where the antireflection film is present satisfy the following expression: ?{(?a*)2+(?b*)2}?4.

Abstract: According to embodiments, a substrate treatment apparatus includes a housing, a heater and a pipe. The housing stores solution containing phosphoric acid and houses a substrate including a silicon substrate. The heater heats the solution over a normal boiling point of the solution. The pipe supplies heated solution heated by the heater into the housing while generating air bubbles.

Abstract: A substrate processing apparatus includes: a processing container, a mixing device, a liquid feeding path, and a controller. The processing container processes a substrate by immersing the substrate in a processing liquid. The mixing device mixes a phosphoric acid aqueous solution and an additive, to produce a mixed liquid to be used as a raw material of the processing liquid. The liquid feeding path feeds the mixed liquid from the mixing device to the processing container. The controller controls the substrate processing apparatus. The controller performs a control to feed the mixed liquid from the mixing device to the processing container in which the substrate is immersed, after a phosphoric acid concentration of the mixed liquid is regulated from a first concentration to a second concentration higher than the first concentration. The first concentration is a concentration when the phosphoric acid aqueous solution is supplied to the mixing device.

Abstract: A rigid horological component (6, 7, 8) for an oscillator mechanism or for an escapement mechanism of a horological movement, the component extending along a principal plane (P) and including at least a part made of a composite material (1), the composite material (1) including a matrix (2) and a multitude of nanotubes or nanowires (3) distributed in the matrix (2), the nanotubes or nanowires (3) being juxtaposed and disposed substantially parallel with an axis (A) substantially perpendicular to the plane (P) of the component, the matrix (2) includes a rigid material (4) to fill the interstices and join the nanotubes or nanowires (3) to one another, the material (4) having rigid mechanical properties to block the elastic deformation of the component, the rigid material (4) comprised in the component having a Young's modulus greater than 2 GPa.

Abstract: A substrate cleaning and drying system includes a cleaning station, a drying station positioned adjacent the cleaning station, a cleaner robot to transfer a substrate from the cleaning station to the drying station, an aligner stage adjacent to the drying station, a robot arm rotatable between a substantially vertical first position for receiving the substrate from the drying station and a substantially horizontal second position for releasing the substrate onto the aligner stage, and a factory interface robot to transfer a substrate from the aligner stage into a factory interface module while in a horizontal orientation. The aligner stage includes a rotatable support to hold the substrate in a substantially horizontal orientation and to rotate the substrate to a desired orientation.

Abstract: A method of forming a carrier wafer includes the steps of: lapping a first surface and a second surface of the carrier wafer such that the carrier wafer is substantially flat, the carrier wafer comprising a glass, glass-ceramic or ceramic material, wherein the carrier wafer has a diameter of from 250 mm to 450 mm and a thickness of from 0.5 mm to 2 mm after lapping; and polishing the first surface of the carrier wafer with at least one of a differential pressure, a differential speed or a differential time between a center portion and an edge portion of the carrier wafer such that the first surface has a convex or concave shape.

Abstract: A substrate processing apparatus includes a temperature detector, a calculation unit and an execution unit. The temperature detector is configured to detect a temperature of a substrate on which a processing liquid is discharged. The calculation unit is configured to calculate, by using a given calculation formula, an etching amount of the substrate based on the temperature detected by the temperature detector. The execution unit configured to perform an etching processing on the substrate by the processing liquid based on the etching amount.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an n-type doped region in a semiconductor substrate and forming a semiconductor stack over the semiconductor substrate. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes introducing n-type dopants from the n-type doped region into the semiconductor stack during the forming of the semiconductor stack. The method further includes patterning the semiconductor stack to form a fin structure and forming a dummy gate stack to wrap around a portion of the fin structure. In addition, the method includes removing the dummy gate stack and the sacrificial layers to release multiple semiconductor nanostructures made up of remaining portions of the semiconductor layers. The method includes forming a metal gate stack to wrap around the semiconductor nanostructures.

Abstract: The present disclosure relates to micro-via structures for interconnects in advanced wafer level semiconductor packaging. The methods described herein enable the formation of high-quality, low-aspect-ratio micro-via structures with improved uniformity, thus facilitating thin and small-form-factor semiconductor devices having high I/O density with improved bandwidth and power.

Abstract: A flow path structure including a first-flow path includes a first-flow path member that including a first-resin member made of a resin and a first-film member having a film, a second-flow path member laminated on the first-flow path member and adhered to the first-flow path member, in which the first-resin member includes a first-front surface that is a surface facing the second-flow path member and that is provided with a first-recessed portion, the first-film member includes a first-surface and a second-surface that is opposite from the first-surface, at least a portion of the first-surface is in close contact with a front surface of the first-resin member inside the first-recessed portion, and the second-surface and the second-flow path member define at least a portion of the first-flow path in a region overlapping the first-recessed portion in a laminating direction of the first-flow path member and the second-flow path member.

Abstract: In a method of forming a semiconductor device, an epitaxial layer stack is formed over a substrate. The epitaxial layer stack includes intermediate layers, one or more first nano layers and one or more second nano layers positioned below the one or more first nano layers. Trenches are formed in the epitaxial layer stack to separate the epitaxial layer stack into sub-stacks, the one of more first nano layers into first nano-channels, and the one or more second nano layers into second nano-channels. The intermediate layers are recessed so that one or more first nano-channels of the first nano-channels and one or more second nano-channels of the second nano-channels in each of the sub-stacks protrude from sidewalls of the intermediate layers. Bottom source/drain (S/D) regions are formed in the trenches to connect the second nano-channels. Top S/D regions are formed in the trenches to connect the first nano-channels.

Abstract: A semiconductor device is provided. The semiconductor device has a first transistor pair formed over a substrate. The first transistor pair includes a n-type transistor and a p-type transistor that are stacked over one another. The n-type transistor has a first channel region that includes one or more first nano-channels with a first stress. The one or more first nano-channels extend laterally along the substrate, are stacked over the substrate and spaced apart from one another. The p-type transistor has a second channel region that includes one or more second nano-channels with a second stress. The one or more second nano-channels extend laterally along the substrate, are stacked over the substrate and spaced apart from one another. Each of the one or more first nano-channels in the first channel region and each of the one or more second nano-channels in the second channel region are surrounded by a gate structure respectively.

Abstract: According to one embodiment, an etching solution used for etching of silicon nitride is provided. The etching solution includes phosphoric acid, an acid, silicic acid compound, and water. The phosphoric acid has a first acid dissociation exponent pKa1. The acid has an acid dissociation exponent smaller than the first acid dissociation exponent pKa1. A mass ratio M1/M2 of mass M1 of the phosphoric acid to mass M2 of the acid having the acid dissociation exponent smaller than the first acid dissociation exponent pKa1 is within a range of 0.82 or more and 725 or less.

Abstract: A novel, particularly rationally designed, modular parking brake actuator for an electric drum brake system. An axle A1 from the motor, including a screw gear pinion coupled in a rotationally fixed manner, and an axle of the spindle arrangement, including a screw gear which is coupled in a rotationally fixed manner to the drive nut, define under a deflection of 90° a single wheel gearbox stage of the parking brake actuator.

Abstract: The present invention provide an orderly patterned remote phosphor crystal material and method for preparation the material and its application, which adopts short-pulse laser to make micro-structure arrays on the surface of phosphor crystal material to enhance the light extraction efficiency of the LED based on the material. The present invention overcomes the phosphor crystal material's properties of hard and dry/wet etching resistance and simplifies the processing steps, which accelerate the processing and improve the producing efficiency. The present invention is able to be performed under room temperature and environment friendly and the micro-structure is stable, which has broad application prospects in white LED field.

Abstract: A substrate treating apparatus and a method of treating a substrate, the apparatus including a substrate treater that treats a substrate using a chemical solution, the chemical solution including a phosphoric acid aqueous solution and a silicon compound; and a chemical solution supplier that supplies the chemical solution to the substrate treating unit, wherein the chemical solution supplier includes a concentration measurer that measures concentrations of the chemical solutions, the concentration measurer including a first concentration measurer that measures a water concentration of the chemical solution; and a second concentration measurer that measures a silicon concentration of the chemical solution.

Abstract: A method for selectively removing silicon nitride is described. In particular, the method includes providing a substrate having a surface with silicon nitride exposed on at least one portion of the surface and SiGex (x is greater than or equal to zero) exposed on at least another portion of the surface, and dispensing an oxidizing agent onto the surface of the substrate to oxidize the exposed SiGex. Thereafter, the method includes dispensing a silicon nitride etching agent as a liquid stream onto the surface of the substrate to remove at least a portion of the silicon nitride.

Abstract: An etching solution, a process of producing the same, and an etching process using the same, in which the etching solution includes hydrofluoric acid (a), ammonium fluoride (b), and salt (c) formed between hydrogen fluoride and a base having a boiling point higher than that of ammonia; the concentration of ammonium fluoride (b) is not higher than 8.2 mol/kg, and the total amount of ammonium fluoride (b) and salt (c) formed between hydrogen fluoride and a base having a boiling point higher than that of ammonia is not less than 9.5 mol/kg.

Abstract: A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor structure includes a first gate channel region having a first gate length, and the second semiconductor structure including a second gate channel region having a second gate length that is greater than the first gate length. The method further includes depositing a work function metal layer in each of a first gate void formed at the first gate channel region and a second gate void formed at the second gate channel region. The method further includes depositing a semiconductor masking layer on the work function metal layer, and simultaneously etching the silicon masking layer located at the first and second gate channel regions to re-expose the first and second gate voids. A low-resistive metal is deposited in the first and second gate voids to form low-resistive metal gate stacks.

Abstract: A method for fabricating a semiconductor device is provided. The method includes the following steps. Firstly, a substrate having a nitride layer and a platinum (Pt)-containing nickel (Ni)-semiconductor compound layer is provided. Then the nitride layer and the Pt are removed in situ with a chemical solution including a sulfuric acid component and a phosphoric acid component.

Abstract: An etching method. The method includes etching a first plurality of silicon wafers in a first enchant, each silicon wafer having SiO2 and Si3N4 deposited thereon, where the etching includes dissolving a quantity of the SiO2 and a quantity of the Si3N4 in the first etchant. A quantity of insoluble SiO2 precipitates. A ratio of a first etch rate of Si3N4 to a first etch rate of SiO2 is determined to be less than a predetermined threshold. A portion of the first etchant is combined with a second etchant to form a conditioned etchant. A second plurality of silicon wafers is etched in the conditioned etchant. A ratio of a second etch rate of Si3N4 to a second etch rate of SiO2 in the conditioned etchant is greater than the threshold. A method for exchanging an etching bath solution and a method for forming a selective etchant are also disclosed.

Abstract: A method for processing a silicon wafer is provided. The method includes allowing an etchant to flow along a surface of the silicon wafer to form a line in which a plurality of apertures are arranged in a flow direction of the etchant from an upstream side to a downstream side. The apertures arranged in the line include a first aperture formed on the most upstream side and a second aperture formed downstream of the first aperture in the flow direction of the etchant. The first aperture and the second aperture are subjected to different processes after being formed.

Abstract: A wet-chemical method of producing a black silicon substrate. The method comprising soaking single crystalline silicon wafers in a predetermined volume of a diluted inorganic compound solution. The substrate is combined with an etchant solution that forms a uniform noble metal nanoparticle induced Black Etch of the silicon wafer, resulting in a nanoparticle that is kinetically stabilized. The method comprising combining with an etchant solution having equal volumes acetonitrile/acetic acid:hydrofluoric acid:hydrogen peroxide.

Abstract: A piezo-resistive MEMS resonator comprising an anchor, a resonator mounted on the anchor, an actuator mounted to apply an electrostatic force on the resonator and a piezo-resistive read-out means comprising a nanowire coupled to the resonator.

Abstract: A method for performing an oxide removal process is described. The method includes providing a substrate having an oxide layer, and preparing a patterned mask layer on the oxide layer, wherein the patterned mask layer has a pattern exposing at least a portion of the oxide layer. An HF treatment of the substrate is performed to transfer the pattern at least partially through the oxide layer, wherein the HF treatment exposes a silicon surface. Following the performing of the HF treatment, a surface property of the silicon surface is modified, wherein the modifying includes administering at least one oxidizing agent to contact the silicon surface to cause chemical oxidation of the silicon surface. And, following the modifying of the surface property, at least a portion of the patterned mask layer or a residual portion of the patterned mask layer is removed.

Abstract: One of objects is to reduce the effect caused by the volume expansion of an active material. An embodiment is a method for manufacturing an electrode for a power storage device which includes an active material over one of surfaces of a current collector. The active material is formed by forming a conductive body functioning as the current collector; forming a mixed layer including an amorphous region and a microcrystalline region over one of surfaces of the conductive body; and etching the mixed layer selectively, so that a part of or the whole of the amorphous region is removed and the microcrystalline region is exposed. Thus, the effect caused by the volume expansion of the active material is reduced.

Abstract: A method for manufacturing a liquid discharge head includes a step of preparing a first substrate having an energy generating element at a front surface side thereof; a step of forming a wall member, which is to become a wall for a liquid flow passage, at the front surface side of the first substrate; a step of forming a mask having an opening on the wall member and forming a second substrate, which is composed of silicon and is to become an orifice plate, on the mask; and a step of forming a liquid supply port in the first substrate and a liquid discharge port in the second substrate by supplying an etchant from a back surface side of the first substrate, the back surface being a surface opposite the front surface.

Abstract: A process of manufacturing a solar cell is provided. The process comprising the steps of: i) ink jet printing an alkali removable water insoluble hot melt ink jet ink onto a substrate comprising a silicon wafer to form a resist image on the substrate; ii) etching or plating the substrate in an aqueous acid medium; and iv) removing the resist image with an aqueous alkali.

Abstract: Compositions and methods for chemical texturing a surface of a polycrystalline silicon wafer to be used in the manufacture of solar cells provide increased efficiency in the manufacture and operation of solar cells. The compositions and methods disclosed herein include first and second components, wherein the first component is a UKON etch composition, including a hydrofluoric acid/nitric acid mixture and water, while the second component includes a silicon wafer texturing enhancer (SWTE).

Abstract: Provided is a fine-processing agent which, when fine-processing a laminated film stacked at least with a silicon dioxide film and a silicon nitride film, can selectively fine-process the silicon dioxide film. Also provided is a fine-processing method utilizing the fine-processing agent. The fine-processing agent is characterized by including: (a) 0.01-15.0 weight % hydrogen fluoride and/or 0.1-40.0 weight % ammonium fluoride, (b) water, and (c) 0.001-10.00 weight % water-soluble polymer selected from among a group consisting of acrylic acid, ammonium acrylate, acrylic acid ester, acrylamide, styrenesulfonic acid, ammonium styrenesulfonate, and styrenesulfonic acid ester.

Abstract: A method is provided for producing a microstructure. The method includes the first step of forming a supporting layer on a base substrate including a silicon substrate provided with recessed sections at a first surface thereof and a metal structure filling the recessed sections so as to come in contact with the metal structure at the first surface, the second step of forming a structure including the metal structure and the supporting layer by selectively etching the silicon substrate to expose at least the surface of the metal structure opposite the surface in contact with the supporting layer from the silicon substrate, and the third step of selectively etching the supporting layer of the metal structure.

Abstract: A method to thin an initial silicon-on-insulator substrate that has a layer of silicon oxide buried between a silicon carrier substrate and a silicon surface layer.

Abstract: A layer of a metal selected from titanium, niobium, tungsten, molybdenum, ruthenium, rhodium, arsenic, aluminum and gallium, an oxide of the metal, a nitride of the metal, silicon nitride, hafnium nitride, tantalum nitride, or an alloy of these metals, the layer being provided on an underlying base material selected from glass, silicon, copper and nickel, is selectively etched with an alkaline etching solution containing a predefined complexing agent.

Abstract: A method for manufacturing a micromechanical structure, and a micromechanical structure. The micromechanical structure encompasses a first micromechanical functional layer, made of a first material, that comprises a buried conduit having a first end and a second end; a micromechanical sensor structure having a cap in a second micromechanical functional layer that is disposed above the first micromechanical functional layer; an edge region in the second micromechanical functional layer, such that the edge region surrounds the sensor structure and defines an inner side containing the sensor structure and an outer side facing away from the sensor structure; such that the first end is located on the outer side and the second end on the inner side.

Abstract: A water dispersible, biocompatible, non-toxic, seedless Group IV nanowire having an etched surface and surface oxide is provided. Also provided is a method of forming water dispersible seedless Group IV nanowires, comprising the steps of providing pristine seedless Group IV nanowires, and reacting the nanowires with a solution of an acidic amino acid to etch the nanowires and promote the formation of a water dispersible oxide layer through the formation of etched nanowires.

Abstract: A method of texturizing a silicon substrate comprising a) contacting the substrate with an etching solution comprising glycolic acid, b) etching a surface of the substrate thereby forming disruptions in said surface of the substrate, and c) removing the etching solution to yield a texturized substrate, said texturized substrate having a plurality of disruptions in at least one surface with a surface density of disruptions of a minimum of 60 disruptions in a 400 micron square area.

Abstract: A method for manufacturing a semiconductor substrate product having: providing an etching liquid containing water, a hydrofluoric acid compound and an organic solvent, and applying the etching liquid to a semiconductor substrate, the semiconductor substrate having a silicon layer and a silicon oxide layer, the silicon layer containing an impurity, and thereby selectively etching the silicon oxide layer.

Abstract: A method for providing a nanopattern of periodically ordered metal oxide nanostructures on a substrate is described. The method comprises the steps of providing a microphase separated block copolymer as a thin film on a substrate, the block copolymer comprising a first polymer having an affinity for a cations of the metal and a second polymer having a lower affinity for the cations than the first polymer, and selectively incorporating a salt of the metal cation into the first polymer of the block copolymer by means of a solvation process prior to or after formation of the microphase separated block copolymer. The block copolymer film is then treated to oxidise the metal ion salt and remove the polymers leaving a nanopattern of metal oxide nanostructures on the substrate.

Abstract: According to one embodiment, a planarizing method is proposed. In the planarizing method, a surface to be processed of an object to be processed including a silicon oxide film is planarized in a processing solution by bringing the surface to be processed into contact with or close proximity with the surface of a solid-state plate on which fluorine is adsorbed. The bonding energy between fluorine and the solid-state plate is lower than that between fluorine and silicon.

Abstract: A micro-scale pendulum structure. The structure includes a membrane having a peripheral support portion and an inner portion, and a micro-scale pendulum carried by the inner portion of the membrane.

Abstract: Disclosed is a method for polishing a silicon wafer, wherein a surface to be polished of a silicon wafer is rough polished, while supplying a polishing liquid, which is obtained by adding a water-soluble polymer to an aqueous alkaline solution that contains no free abrasive grains, to a polishing cloth. Consequently, the surface to be polished can be polished at high polishing rate and the flatness of the edge portion including roll-off and roll-up can be controlled.

Abstract: Provided are organosilica composites based on bis(3-triethoxysilylpropyl)tetrasulfide (TESPTS) or bis(3-triethoxysilylpropyl)disulfide (TESPDS) and containing octadecyltrimethoxy silane (C18TMS) and cetyltrimethylammonium bromide (CTAB), and a method for preparing hollow or porous carbon structures and silica structures using the same. According to the present disclosure, it is possible to obtain hollow or porous carbon structures and silica structures in a more simple and cost-efficient manner. Thus, the resultant structures have a high surface area and a large mesopore volume, so that they may serve as catalyst carriers for fuel cells capable of loading metal catalyst particles having a smaller particle size in a larger amount and in a more homogeneously dispersed state.

Abstract: A liquid agent for the surface treatment of monocrystalline wafers, which contains an alkaline etching agent and also at least one low-volatile organic compound. Systems of this type can be used both for the cleaning, damage etch and texturing of wafer surfaces in a single etching step and exclusively for the texturing of silicon wafers with different surface quality, whether it now be wire-sawn wafers with high surface damage or chemically polished surfaces with minimum damage density.

Abstract: A method of forming an aperture (e.g., a through via, a blind via, a trench, an alignment feature, etc.) within a substrate includes irradiating a substrate with a laser beam to form a laser-machined feature having a sidewall. The laser-machined feature is then processed to change at least one characteristic (e.g., the sidewall surface roughness, diameter, taper, aspect ratio, cross-sectional profile, etc.) of the laser-machined feature. The laser-machined feature can be processed to form the aperture by performing an isotropic wet-etch process employing an etchant solution containing HNO3, HF and, optionally acetic acid.

Abstract: Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.

Abstract: A method for removing silicon nitride material includes following steps. A substrate having at least a gate structure formed thereon is provided, and at least a silicon nitride hard mask is formed on top of the gate structure. A first removal is performed to remove a portion of the silicon nitride hard mask with a first phosphoric acid (H3PO4) solution. A second removal is subsequently performed to remove remnant silicon nitride hard mask with a second phosphoric acid solution. The first removal and the second removal are performed in-situ. A temperature of the second phosphoric acid solution is lower than a temperature of the first phosphoric acid solution.

Abstract: A method of surface treatment for zirconium oxide implants and the etching formula for the same are disclosed. The processes are carried out at room temperature. The average surface roughness Ra and the standard deviation of the implant are measured showing significant improvement while comparing with the un-treated sample and the hydrofluoric acid treated samples. The average contact angle is provided showing an almost hydrophilic surface after etched by the formula according to the present invention.

Abstract: A method to fabricate a hierarchical graduated-branched structure that grows in a three-dimensional pattern down to fractal-branching, nano-size level is detailed. The fractal patterning is accomplished on a three-dimensional (i.e., non-planar) surface, by exposing the surface to a properly focused particle beam, which causes the spontaneous growth of graduated branches all over the surface. The structure can be fabricated with a single material and the fractal-patterning is done in a one step process. No addition of material is required for the formation of each branch. The fractal graduated branching structure can then be molded in order to produce replicas.

Abstract: Provided herein are integration-compatible dielectric films and methods of depositing and modifying them. According to various embodiments, the methods can include deposition of flowable dielectric films targeting specific film properties and/or modification of those properties with an integration-compatible treatment process. In certain embodiments, methods of depositing and modifying flowable dielectric films having tunable wet etch rates and other properties are provided. Wet etch rates can be tuned during integration through am integration-compatible treatment process. Examples of treatment processes include plasma exposure and ultraviolet radiation exposure.