Substrate Contains Silicon Or Silicon Compound Patents (Class 216/99)
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Patent number: 8142673Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute.Type: GrantFiled: July 12, 2004Date of Patent: March 27, 2012Assignee: Micron Technology, Inc.Inventor: Donald L Yates
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Patent number: 8123962Abstract: Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. In some embodiments, the films can be used as a template or mask to etch openings in an underlying material layer.Type: GrantFiled: June 12, 2007Date of Patent: February 28, 2012Assignee: Micron Technology, Inc.Inventors: Dan B. Millward, Donald Westmoreland, Gurtej Sandhu
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Patent number: 8123963Abstract: A method for producing a semiconductor component includes forming an n-doped layer in a p-doped layer of the semiconductor component, wherein the n-doped layer comprises at least one of: a sieve-like layer or a network-like layer. The method also includes porously etching the p-doped layer between the material of the n-doped layer to form a top electrode, and forming a cavity below the n-doped layer.Type: GrantFiled: May 12, 2008Date of Patent: February 28, 2012Assignee: Robert Bosch GmbHInventors: Hubert Benzel, Heribert Weber, Hans Artmann, Frank Schaefer
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Patent number: 8114300Abstract: Methods for fabricating sublithographic, nanoscale polymeric microstructures utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.Type: GrantFiled: April 21, 2008Date of Patent: February 14, 2012Assignee: Micron Technology, Inc.Inventor: Dan B. Millward
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Patent number: 8114301Abstract: Methods for fabricating sublithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.Type: GrantFiled: May 2, 2008Date of Patent: February 14, 2012Assignee: Micron Technology, Inc.Inventors: Dan B. Millward, Donald Westmoreland
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Patent number: 8114780Abstract: A method of removing carbon doped silicon oxide between metal contacts is provided. A layer of the carbon doped silicon oxide is converted to a layer of silicon oxide by removing the carbon dopant. The converted layer of silicon oxide is selectively wet etched with respect to the carbon doped silicon oxide and the metal contacts, which forms recess between the metal contacts.Type: GrantFiled: March 27, 2009Date of Patent: February 14, 2012Assignee: Lam Research CorporationInventors: Mayumi Block, Robert C. Hefty, Stephen M. Sirard, Kenji Takeshita
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Publication number: 20120027956Abstract: A method of forming a nitride film is disclosed. In one embodiment, the method comprises performing an ending film deposition process that differs from the main film deposition process in terms of the flow rates of the reactive and ion source gases, and maintaining acceleration power of a CVD tool during the ending film deposition process. A post deposition process may also be used to remove a denser top layer of nitride, resulting in a nitride film having a consistent density.Type: ApplicationFiled: July 29, 2010Publication date: February 2, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daewon Yang, Anthony Gene Domenicucci, Aurelia Suwarno-Handayana, Shamas Musthafa Ummer
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Patent number: 8083953Abstract: Methods for fabricating sublithographic, nanoscale linear microchannel arrays over surfaces without defined features utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. Embodiments of the methods use a multilayer induced ordering approach to align lamellar films to an underlying base film within trenches, and localized heating to anneal the lamellar-phase block copolymer film overlying the trenches and outwardly over the remaining surface.Type: GrantFiled: March 6, 2007Date of Patent: December 27, 2011Assignee: Micron Technology, Inc.Inventors: Dan B. Millward, Eugene P. Marsh
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Patent number: 8083962Abstract: A method for forming a minute pattern includes depositing a material layer on a semiconductor substrate having a conductive region, forming a first mask layer on the material layer, forming a recess region in the first mask layer, performing layer processing to form a first mask pattern in the recess region, and etching the material layer to form a material layer pattern.Type: GrantFiled: April 5, 2007Date of Patent: December 27, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jang-Eun Lee, Kyung-Tae Nam, Se-Chung Oh, Jun-Ho Jeong
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Method of forming fine patterns and manufacturing semiconductor light emitting device using the same
Patent number: 8080480Abstract: A method of forming a fine pattern begins with providing a c-plane hexagonal semiconductor crystal. A mask having a predetermined pattern is formed on the semiconductor crystal. The semiconductor crystal is dry-etched by using the mask to form a first fine pattern on the semiconductor crystal. The semiconductor crystal including the first fine pattern is wet-etched to expand the first fine pattern in a horizontal direction to form a second fine pattern. The second fine pattern obtained in the wet-etching the semiconductor crystal has a bottom surface and a sidewall that have unique crystal planes, respectively. The present fine-pattern forming process can be advantageously applied to a semiconductor light emitting device, particularly, to a phonic crystal structure required to have fine patterns or a structure using a surface plasmon resonance principle.Type: GrantFiled: September 26, 2008Date of Patent: December 20, 2011Assignee: Samsung LED Co., Ltd.Inventors: Jong Ho Lee, Moo Youn Park, Soo Ryong Hwang, Il Hyung Jung, Gwan Su Lee, Jin Ha Kim -
Patent number: 8066898Abstract: A surface treatment solution for finely processing a glass substrate containing multiple ingredients is used for the construction of liquid crystal-based or organic electroluminescence-based flat panel display devices without invoking crystal precipitation and/or increasing surface roughness. An etching solution of the invention contains, in addition to hydrofluoric acid (HF) and ammonium fluoride (NH4F), at least one acid whose dissociation constant is larger than that of HF. The concentration of the acid in the solution can advantageously be adjusted to maximize the etching rate.Type: GrantFiled: September 25, 2008Date of Patent: November 29, 2011Assignee: Stella Chemifa Kabushiki KaishaInventors: Hirohisa Kikuyama, Tatsuhiro Yabune, Masayuki Miyashita, Tadahiro Ohmi
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Patent number: 8062535Abstract: Method for producing a probe for atomic force microscopy with a silicon nitride cantilever and an integrated single crystal silicon tetrahedral tip with high resonant frequencies and low spring constants intended for high speed AFM imaging.Type: GrantFiled: January 30, 2008Date of Patent: November 22, 2011Inventor: Chung Hoon Lee
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Patent number: 8057690Abstract: Methods for creating at least one micro-electromechanical (MEMS) structure in a silicon-on-insulator (SOI) wafer. The SOI wafer with an extra layer of oxide is etched according to a predefined pattern. A layer of oxide is deposited over exposed surfaces. An etchant selectively removes the oxide to expose the SOI wafer substrate. A portion of the SOI substrate under at least one MEMS structure is removed, thereby releasing the MEMS structure to be used in the formation of an accelerometer.Type: GrantFiled: March 11, 2009Date of Patent: November 15, 2011Assignee: Honeywell International Inc.Inventor: Lianzhong Yu
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Publication number: 20110269019Abstract: A process for etching silicon to form silicon pillars on the etched surfaces, includes treating silicon with an etching solution that includes 5 to 10M HF 0.01 to 0.1M Ag+ ions and 0.02 to 0.2M NO3? ions. Further, NO3? ions in the form of alkali metal, nitric acid or ammonium nitrate salt is added to maintain the concentration of nitrate ions within the above range. The etched silicon is separated from the solution. The process provides pillars, especially for use as the active anode material in lithium ion batteries. The process is advantageous because it uses an etching bath containing only a small number of ingredients whose concentration needs to be controlled and it can be less expensive to operate than previous processes.Type: ApplicationFiled: October 2, 2009Publication date: November 3, 2011Inventors: Mino Green, Feng-Ming Liu
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Patent number: 8043517Abstract: A method of forming an opening through a substrate includes defining an area on a first surface of the substrate where the opening is to be formed, the area having a center region flanked by edge regions. A top layer having a substantially closed space located over the area is formed on the first surface. Structure for promoting etching of the center region is provided, and the first surface of the substrate is etched in the area. In one embodiment, the method can fabricate an inkjet printhead having a substrate having an ink feed hole formed therethrough and an orifice plate formed thereon. A plurality of particle tolerance elements located over a center region of the ink feed hole promoted etching during the fabrication of the printhead.Type: GrantFiled: September 19, 2005Date of Patent: October 25, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jianhui Gu, Rio Rivas, Jeremy Harlan Donaldson, Bernard A Rojas
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Patent number: 8028389Abstract: A novel surface acoustic wave device with a decreased velocity dispersion and a low insertion loss as well as the fabrication method therefore is provided. The surface acoustic wave device includes a substrate, an insulating layer with an indentation on the substrate, a silicon layer divided by an etched window with a first portion on the insulating layer and a second portion suspended above the indentation, a piezoelectric layer on the first and the second portions of the silicon layer, and at least an electrode on the piezoelectric layer.Type: GrantFiled: November 21, 2007Date of Patent: October 4, 2011Assignee: Precision Instrument Development CenterInventors: Jyh-Shin Chen, Sheng-Wen Chen, Hui-Ling Kao, Yu-Sheng Kung, Yu-Hsin Lin, Yi-Chiuen Hu
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Patent number: 8021561Abstract: The optical device includes a plurality of waveguides and an optical grating. A first portion of the waveguides act as input waveguide configured to carry a light beam that includes multiple light signals to the optical grating. The optical grating is configured to demultiplex the light signals. A second portion of the waveguides act as output waveguides configured to carry the demultiplexed light signals away from the optical grating. A method of forming the optical device includes sequentially forming the waveguides and the optical grating while a single mask defines the location of the waveguides and the optical grating.Type: GrantFiled: January 16, 2009Date of Patent: September 20, 2011Assignee: Kotura, Inc.Inventors: Wei Qian, Joan Fong, Dazeng Feng
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Patent number: 8012529Abstract: According to the invention, an insulating or semi-insulating barrier layer which has a thickness where a tunnel current can flow through is provided between a hole injection electrode and an organic compound layer with hole transport characteristics (a hole injection layer or a hole transport layer). Specifically, a thin insulating or semi-insulating barrier layer which contains silicon or silicon oxide; silicon or silicon oxide and a light transmitting conductive oxide material; or silicon or silicon oxide, a light transmitting conductive oxide material, and carbon may be provided between a light transmitting conductive oxide film formed of a light transmitting conductive oxide material, such as ITO and a hole injection layer containing an organic compound.Type: GrantFiled: July 18, 2007Date of Patent: September 6, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Junichiro Sakata, Masakazu Murakami, Koji Moriya, Yoshiaki Oikawa, Taketomi Asami, Hisashi Ohtani
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Patent number: 8007676Abstract: A slurry composition includes an acidic aqueous solution and one or both of, an amphoteric surfactant and a glycol compound. Examples of the amphoteric surfactant include a betaine compound and an amino acid compound, and examples of the amino acid compound include lysine, proline and arginine. Examples of the glycol compound include diethylene glycol, ethylene glycol and polyethylene glycol.Type: GrantFiled: May 29, 2008Date of Patent: August 30, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hyun So, Sung-Taek Moon, Dong-Jun Lee, Nam-Soo Kim, Bong-Su Ahn, Kyoung-Moon Kang
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Patent number: 7998359Abstract: A method for selectively etching a silicon-containing film on a silicon substrate is disclosed. The method includes depositing a silicon-containing film on the silicon substrate. The method further includes baking the silicon-containing film to create a densified silicon-containing film, wherein the densified film has a first thickness. The method also includes exposing the silicon substrate to an aqueous solution comprising NH4F and HF in a ratio of between about 6:1 and about 100:1, at a temperature of between about 20° C. and about 50° C., and for a time period of between about 30 seconds and about 5 minutes; wherein between about 55% and about 95% of the densified silicon-containing film is removed.Type: GrantFiled: September 24, 2010Date of Patent: August 16, 2011Assignee: Innovalight, Inc.Inventors: Elena Rogojina, Eric Rosenfeld, Dmitry Poplavskyy
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Patent number: 7988876Abstract: To reduce and homogenize the thickness of a semiconductor layer which lies on the surface of an electrically insulating material, the surface of the semiconductor layer is exposed to the action of an etchant whose redox potential is adjusted as a function of the material and the desired final thickness of the semiconductor layer, so that the material erosion per unit time on the surface of the semiconductor layer due to the etchant becomes less as the thickness of the semiconductor layer decreases, and is only from 0 to 10% of the thickness per second when the desired thickness is reached. The method is carried out without the action of light or the application of an external electrical voltage.Type: GrantFiled: January 31, 2008Date of Patent: August 2, 2011Assignee: Siltronic AGInventors: Diego Feijoo, Oliver Riemenschneider, Reinhold Wahlich
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Publication number: 20110175487Abstract: The invention relates to a method for producing a dielectric layer (3) in an electroacoustic component (1), in particular a component operating with acoustic surface waves or bulk acoustic waves, comprising a substrate and an associated electrode structure, in which the dielectric layer (3) is formed at least in part by depositing by a thermal vapour deposition process at least one evaporation material selected from the following group of layer vaporising materials: vapour deposition glass material such as borosilicate glass, silicon nitride and aluminium oxide. The invention further relates to an electroacoustic component.Type: ApplicationFiled: July 23, 2009Publication date: July 21, 2011Inventors: Ulli Hansen, Jürgen Leib, Simon Maus
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Patent number: 7981303Abstract: A novel silicon micromirror structure for improving image fidelity in laser pattern generators is presented. In some embodiments, the micromirror is formed from monocrystalline silicon. Analytical- and finite element analysis of the structure as well as an outline of a fabrication scheme to realize the structure are given. The spring constant of the micromirror structure can be designed independently of the stiffness of the mirror-surface. This makes it possible to design a mirror with very good planarity, resistance to sagging during actuation, and it reduces influence from stress in reflectivity-increasing multilayer coatings.Type: GrantFiled: September 19, 2008Date of Patent: July 19, 2011Assignee: Micronic MyData ABInventors: Martin Bring, Peter Enoksson
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Patent number: 7976714Abstract: Methods for producing a MEMS device from a single silicon-on-insulator (SOI) wafer. An SOI wafer includes a silicon (Si) handle layer, a Si mechanism layer and an insulator layer located between the Si handle and Si mechanism layers. An example method includes etching active components from the Si mechanism layer. Then, the exposed surfaces of the Si mechanism layer is doped with boron. Next, portions of the insulator layer proximate to the etched active components of the Si mechanism layer are removed and the Si handle layer is etched proximate to the etched active components.Type: GrantFiled: January 4, 2008Date of Patent: July 12, 2011Assignee: Honeywell International Inc.Inventor: Lianzhong Yu
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Patent number: 7964109Abstract: The invention includes methods of cleaning a surface of a cobalt-containing material, methods of forming an opening to a cobalt-containing material, semiconductor processing methods of forming an integrated circuit comprising a copper-containing conductive line, and cobalt-containing film cleaning solutions. In one implementation, a method of cleaning a surface of a cobalt-containing material includes forming a cobalt-containing material over a substrate. The surface of the cobalt-containing material is exposed to an aqueous mixture. The aqueous mixture has an acidic pH and comprises acetic acid, a multiprotic acid, and HF. Other aspects and implementations are contemplated.Type: GrantFiled: March 24, 2008Date of Patent: June 21, 2011Assignee: Micron Technology, Inc.Inventor: Michael T. Andreas
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Patent number: 7955440Abstract: After a water film is formed on a wafer front surface in a chamber, the water film is supplied sequentially with an oxidizing component of an oxidation gas, an organic acid component of an organic acid mist, an HF component of an HF gas, the organic acid mist, and the oxidizing component of the oxidation gas. As a result, the HF component and the organic acid component provide cleaning effect on the wafer surface, and a concentration of the cleaning components in the water film within a wafer surface can be even.Type: GrantFiled: November 21, 2008Date of Patent: June 7, 2011Assignee: Sumco CorporationInventors: Shigeru Okuuchi, Kazushige Takaishi
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Patent number: 7955989Abstract: Semiconductors are textured with aqueous solutions containing non-volatile alkoxylated glycols, their ethers and ether acetate derivatives having molecular weights of 170 or greater and flash points of 75° C. or greater. The textured semiconductors can be used in the manufacture of photovoltaic devices.Type: GrantFiled: September 22, 2010Date of Patent: June 7, 2011Assignee: Rohm and Haas Electronic Materials LLCInventors: Robert K. Barr, Corey O'Connor
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Patent number: 7955738Abstract: Polymeric ionic gels of ionic liquids having melting points below about 100° C. that are formed by the reaction of a heterocyclic amine with about 2.8 and about 3.2 moles of anhydrous hydrogen fluoride per mole of amine nitrogen. Electrochemical devices having non-aqueous electrolytes containing the ionic liquids and polymeric ionic gels are also disclosed.Type: GrantFiled: March 4, 2005Date of Patent: June 7, 2011Assignee: Honeywell International, Inc.Inventors: Rajiv R. Singh, Martin R Paonessa, Ian R Shankland
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Patent number: 7951300Abstract: Methods for wafer-scale fabrication of needle arrays can include mechanically modifying a wafer to produce a plurality of vertically-extending columns. The columns are etched to round and reshape the columns into substantially uniformly shaped needles. Needle arrays having needle width non-uniformity of less than about 3% and length non-uniformity of less than about 2% can be produced.Type: GrantFiled: May 29, 2007Date of Patent: May 31, 2011Assignee: University of Utah Research FoundationInventors: Rajmohan Bhandari, Sandeep Negi, Florian Solzbacher, Richard A. Normann
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Patent number: 7951718Abstract: A silicon-on-insulator transfer wafer having a front surface with a circumferential lip around a circular recess is polished. In one version, the circular recess on the front surface of the wafer is masked by filling the recess with spin-on-glass. The front surface of the wafer is exposed to an etchant to preferentially etch away the circumferential lip, while the circular recess is masked by the spin-on-glass. The spin-on glass is removed, and the front surface of the transfer wafer is polished. Other methods of removing the circumferential lip include applying a higher pressure to the circumferential lip in a polishing process, and directing a pressurized fluid jet at the base of the circumferential lip.Type: GrantFiled: February 19, 2008Date of Patent: May 31, 2011Assignee: Applied Materials, Inc.Inventors: Raymond John Donohoe, Krishna Vepa, Paul V. Miller, Ronald Rayandayan, Hong Wang
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Patent number: 7927500Abstract: The use of an ammonium hydroxide spike to a hot tetra methyl ammonium hydroxide (TMAH) solution to form an insitu poly oxide decapping step in a polysilicon (poly) etch process, results in a single step rapid poly etch process having uniform etch initiation and a high etch selectivity, that may be used in manufacturing a variety of electronic devices such as integrated circuits (ICs) and micro electro-mechanical (MEM) devices. The etching solution is formed by adding 35% ammonium hydroxide solution to a hot 12.5% TMAH solution at about 70° C. at a rate of 1% by volume, every hour. Such an etch solution and method provides a simple, inexpensive, single step self initiating poly etch that has etch stop ratios of over 200 to 1 over underlying insulator layers and TiN layers.Type: GrantFiled: March 22, 2007Date of Patent: April 19, 2011Assignee: Micron Technology, Inc.Inventor: Kevin Shea
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Patent number: 7923118Abstract: A method of fabricating a liquid crystal display array substrate includes forming a gate wiring line having a gate pad electrode, forming a data wiring line having a data pad electrode, forming a protection layer over the gate pad electrode and the data pad electrode, and positioning etching tapes on the protection layer over the gate pad electrode and the data pad electrode.Type: GrantFiled: January 16, 2009Date of Patent: April 12, 2011Assignee: LG Display Co., Ltd.Inventors: Jae Young Oh, Soo Pool Kim
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Patent number: 7910014Abstract: A chemical processing bath and system used in semiconductor manufacturing utilizes a dynamic spiking model that essentially constantly monitors chemical concentration in the processing bath and adds fresh chemical on a regular basis to maintain chemical concentrations at desirable levels. Etch rates and etch selectivities are maintained at desirable levels and contamination from undesirable precipitation is avoided. The system and method automatically compare concentration levels to a plurality of control limits associated with various technologies and identify the technology or technologies that may undergo processing.Type: GrantFiled: December 21, 2007Date of Patent: March 22, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-Yung Yu, Yu-Sheng Su, Li Te Hsu, Jin Lin Liang, Shih Cheng Yeh, Pin Chia Su
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Patent number: 7892440Abstract: The present invention illustrates a bulk silicon etching technique that yields straight sidewalls, through wafer structures in very short times using standard silicon wet etching techniques. The method of the present invention employs selective porous silicon formation and dissolution to create high aspect ratio structures with straight sidewalls for through wafer MEMS processing.Type: GrantFiled: July 26, 2007Date of Patent: February 22, 2011Assignee: University of South FloridaInventors: Shekhar Bhansali, Abdur Rub Abdur Rahman, Sunny Kedia
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Patent number: 7879736Abstract: In a composition for etching silicon oxide, and a method of forming a contact hole using the composition, the composition which includes from about 0.01 to about 2 percent by weight of ammonium bifluoride, from about 2 to about 35 percent by weight of an organic acid, from about 0.05 to about 1 percent by weight of an inorganic acid, and a remainder of a low polar organic solvent. The composition may reduce damages to a metal silicide pattern that may be exposed in an etching process performed for forming the contact hole.Type: GrantFiled: June 29, 2007Date of Patent: February 1, 2011Assignees: Samsung Electronics Co., Ltd., Cheil Industries, Inc.Inventors: Dong-Won Hwang, Kook-Joo Kim, Jung-In La, Pil-Kwon Jun, Seung-Ki Chae, Yang-Koo Lee
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Patent number: 7867408Abstract: A silicon oxide film is formed on one principal surface of a silicon substrate by thermal oxidation, and thereafter, a silicon nitride film is formed on the silicon oxide film by CVD. A lamination layer of the silicon oxide film and silicon nitride film is selectively dry etched to form a mask opening 22 and leave an etching mask made of a left region of the lamination layer. The substrate is selectively and anisotropically etched with alkali etchant such as TMAH by using the etching mask to form a substrate opening. By setting a ration of the thickness of the silicon oxide film to the thickness of the silicon nitride film to 1.25 or larger or preferably 1.60 or larger, it is possible to prevent the deformation of the etched shape of the inner walls of the openings and cracks in the etching mask.Type: GrantFiled: June 13, 2007Date of Patent: January 11, 2011Assignee: Yamaha CorporationInventor: Tomoyasu Aoshima
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Patent number: 7862731Abstract: To form an isolation structure in a semiconductor substrate, at least two trenches are formed with a rib therebetween in the semiconductor substrate, and then the semiconductor material in the area of the trenches and particularly the rib is converted to an electrically insulating material. For example, this is accomplished by thermal oxidation of silicon semiconductor material of the rib.Type: GrantFiled: September 12, 2003Date of Patent: January 4, 2011Assignee: Conti Temic microelectronic GmbHInventors: Matthias Aikele, Albert Engelhardt, Marcus Frey, Bernhard Schmid, Helmut Seidel
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Patent number: 7837890Abstract: The present invention relates to a novel printable etching medium having non-Newtonian flow behavior for the etching of surfaces in the production of solar cells and to the use thereof. In particular, the invention relates to corresponding particle-containing compositions by means of which extremely fine structures can be etched very selectively without damaging or attacking adjacent areas.Type: GrantFiled: December 19, 2005Date of Patent: November 23, 2010Assignee: Merck Patent GmbHInventors: Werner Stockum, Armin Kuebelbeck, Sylke Klein
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Patent number: 7833405Abstract: A micromechanical component is described which includes a substrate; a monocrystalline layer, which is provided above the substrate and which has a membrane area; a cavity that is provided underneath the membrane area; and one or more porous areas, which are provided inside the monocrystalline layer and which have a doping that is higher than that of the surrounding layer.Type: GrantFiled: December 13, 2001Date of Patent: November 16, 2010Assignee: Robert Bosch GmbHInventors: Hubert Benzel, Heribert Weber, Hans Artmann, Frank Schaeffer
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Patent number: 7833430Abstract: A method of making a microstructure with thin wall portions (T1-T3) includes a step of performing a first etching process to a material substrate having a laminate structure including a first conductive layer (11) and a second conductive layer (12) having a thickness of the thin wall portions (T1-T3), where the etching is performed from the side of the first conductive layer (11) thereby forming in the second conductive layer (12) pre thin wall portions (T1?-T3?) which has a pair of side surfaces apart from each other in an in-plane direction of the second conductive layer (12) and contact the first conductive layer (11). The method also includes a step of performing a second etching process from the side of the first conductive layer (11) for removing part of the first conductive layer (11) contacting the pre thin wall portions (T1?-T3?) to form the thin wall portions.Type: GrantFiled: October 25, 2005Date of Patent: November 16, 2010Assignee: Fujitsu LimitedInventors: Xiaoyu Mi, Norinao Kouma, Osamu Tsuboi, Masafumi Iwaki, Hisao Okuda, Hiromitsu Soneda, Satoshi Ueda, Ippei Sawaki
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Publication number: 20100282165Abstract: The invention relates to a method for selective material deposition for sensitive structures in micro systems technology for producing mechanical adjustment structures (6, 5) for a vapour penetration mask (8), the adjustment structures on the component disc (7) and the mask being created using the same structuring method. Complementary adjustment structures can be produced thereon with a very high degree of precision. KOH etching in silicon can be used in order to create equally inclined flanks (2, 2a) in a depression and a complementary protrusion.Type: ApplicationFiled: June 16, 2008Publication date: November 11, 2010Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AGInventor: Roy Knechtel
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Patent number: 7811464Abstract: There is provided a preferential etching method wherein a preferential etchant which contains at least a hydrofluoric acid whose composition by volume falls within the range of 0.02 to 0.1, a nitric acid whose composition by volume falls within the range of 0.5 to 0.6, an acetic acid whose composition by volume falls within the range of 0.2 to 0.25, and water is used to etch a silicon single crystal substrate whose electrical resistivity is less than 10 m?·cm at a rate higher than 0.1 ?m/min, thereby eliciting BMDs on a surface of the silicon single crystal substrate. As a result, the preferential etching method that can evaluate and utilize characteristics of crystal defects, especially BMDs in an ultralow-resistance silicon single crystal substrate whose electrical resistivity is less than 10 m?·cm, which cannot be readily detected by conventional techniques, by performing preferential etching using a chromeless etchant containing no harmful chrome can be provided.Type: GrantFiled: January 23, 2006Date of Patent: October 12, 2010Assignee: Shin-Etsu Handotai Co., Ltd.Inventor: Fumitaka Kume
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Publication number: 20100256408Abstract: The present disclosure relates to a method of preparing silicon carbon nanocrystals (SiC-NCs) in a size-dependent manner by reacting a compound of the Formula I: R1Si(X1)3, with a compound of the Formula II Si(X2)4(II) under conditions for the hydrolysis and condensation of the compound of the Formula I and the compound of the Formula II to form a siloxane polymer comprising repeating units of the Formula III: —[(R1SiO1.5)x(SiO2)y]—, followed by thermal processing of the siloxane polymer under conditions to form SiC-NC's. Optionally the SiC-NC's are liberated to provide free standing SiC-NC's.Type: ApplicationFiled: December 14, 2009Publication date: October 7, 2010Applicant: THE GOVERNORS OF THE UNIVERSITY OF ALBERTAInventors: Jonathan Gordon Conn Veinot, Eric James Henderson
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Publication number: 20100224593Abstract: An acid corrosion solution for preparing polysilicon suede is obtained by mixing with an oxidant and a hydrogen fluoride. The oxidant is a nitrate or nitrite. The method applied of the solution includes putting the polysilicon cut pieces into the acid corrosion solution to carry out the corrosion reaction. The reaction time is about 30 seconds to 20 minutes and the temperature of acid corrosion solution is ?10° C. to 25° C.Type: ApplicationFiled: May 24, 2006Publication date: September 9, 2010Applicant: WUXI SUNTECH POWER CO., LTD.Inventors: Jingjia Ji, Yusen Qin, Zhengrong Shi
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Patent number: 7790045Abstract: The present invention relates to the self-assembly of a spherical-morphology block copolymer into V-shaped grooves of a substrate. Although spherical morphology block copolymers typically form a body-centered cubic system (bcc) sphere array in bulk, the V-shaped grooves promote the formation of a face-centered cubic system (fcc) sphere array that is well ordered. In one embodiment, the (111) planes of the fcc sphere array are parallel to the angled side walls of the V-shaped groove. The (100) plane of the fcc sphere array is parallel to the top surface of the substrate, and may show a square symmetry among adjacent spheres. This square symmetry is unlike the hexagonal symmetry seen in monolayers of spherical domains and is a useful geometry for lithography applications, especially those used in semiconductor applications.Type: GrantFiled: September 13, 2007Date of Patent: September 7, 2010Assignee: Massachusetts Institute of TechnologyInventors: Peng-Wei Chuang, Caroline A. Ross
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Patent number: 7785485Abstract: A method for manufacturing blades for surgical and other uses from either a crystalline or polycrystalline material, preferably in the form of a wafer, comprises preparing the crystalline or polycrystalline wafers by mounting them and machining trenches into the wafers. The methods for machining the trenches, which form the bevel blade surfaces, include a diamond blade saw, laser system, ultrasonic machine, a hot forge press and a router. When a router is used, through-holes are drilled in the wafer to define the starting locations of the trenches. After the trenches are formed, the wafers are placed in an etchant solution which isotropically etches the wafers in a uniform manner, such that layers of crystalline or polycrystalline material are removed uniformly, producing single or double bevel blades, with each bevel having one or more facets. Nearly any bevel angle can be machined into the wafer which remains after etching.Type: GrantFiled: September 17, 2004Date of Patent: August 31, 2010Assignee: Becton, Dickinson and CompanyInventors: Vadim M. Daskal, Joseph F. Keenan, James Joseph Hughes
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Publication number: 20100214880Abstract: The micro-mechanical part, for example a horological movement part, includes a silicon core (1) all or part of the surface (3) of which is coated with a thick amorphous material (2). This material is preferably silicon dioxide and has a thickness which is five times greater than the thickness of native silicon dioxide.Type: ApplicationFiled: June 21, 2006Publication date: August 26, 2010Applicant: ETA SA MANUFACTURE HORLOGERE SUISSEInventors: René Rappo, Marc Lippuner, Lionel Paratte, Thierry Conus
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Patent number: 7780302Abstract: In a method of forming a device so as to include a reflective surface at a specific angle to an incident optical axis, a region of a first major surface of a substrate is exposed to an anisotropic etchant to form a surface having the specific angle with respect to the first major surface, but the etched surface is then used as a mounting surface. That is, rather than anisotropically etching a reflective surface, the etching provides the mounting surface and the second major surface of the substrate functions as the reflective surface when the fabricated device is properly mounted. The substrate may be a <100> silicon wafer having a 9.74 degree off-axis cut. Then, a 45 degree mirror is formed by the process. When the reflector is used in an optical device, the <111> crystalline plane will be generally parallel to the surface of the support.Type: GrantFiled: December 19, 2008Date of Patent: August 24, 2010Assignee: Avago Technologies Fiber IP (Singapore) Pte. Ltd.Inventor: Tak Kui Wang
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Patent number: 7781343Abstract: By forming a protection layer on the back side of a substrate prior to any process sequences, which may deposit material or material residues on the back side, the respective back side uniformity may be significantly enhanced, thereby also increasing process efficiency of subsequent back side critical processes, such as lithography, back end of line processes and the like. In one illustrative embodiment, silicon carbide may be used as a material for forming a respective protection layer.Type: GrantFiled: June 4, 2007Date of Patent: August 24, 2010Assignee: Globalfoundries Inc.Inventors: Tobias Letz, Holger Schuehrer, Markus Nopper
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Patent number: 7780868Abstract: Alkaline etching solutions capable of improving a surface roughness even with a relatively low alkaline concentration, contain bromate or both bromate and nitrate. An alkaline etching method using the solution produces silicon wafers with improved surface roughness.Type: GrantFiled: September 5, 2007Date of Patent: August 24, 2010Assignee: Siltronic AGInventor: Shigeki Nishimura