Substrate Contains Silicon Or Silicon Compound Patents (Class 216/99)
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Patent number: 5783097Abstract: A simple, non critical, low cost process step is added to the manufacture of integrated circuit wafers to remove a ridge of dielectric material remaining at the flat edge of the wafer after an edge rinse has removed the ridge of dielectric from the circular edges of the wafer. A layer of dielectric, such as Spin-On-Glass or the like, is formed on the wafer. An edge rinse is then used to remove the ridge of dielectric formed at the wafer edge, however the edge rinse does not remove the ridge of dielectric at the flat edge of the wafer. A layer of photoresist is formed on the wafer, selectively exposed, and developed to form a photoresist mask. The flat edge of the wafer is then dipped in buffered oxide etch to remove the dielectric material at the flat edge of the wafer. The photoresist mask is then stripped and processing of the wafer is continued.Type: GrantFiled: June 9, 1997Date of Patent: July 21, 1998Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Shen Lo, Chao-Hsin Chang, Chia-Hsiang Chen, Hsien-Wen Chang, Chih-Heng Shen
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Patent number: 5779928Abstract: A film dissolving liquid is ejected from a needle-shaped nozzle onto a peripheral edge portion of a substrate surface of a SOG film, while being subjected to the film dissolving liquid. The substrate is rotated in order to dissolve and remove the SOG film from the peripheral edge portion of the substrate. The film dissolving liquid is a solvent or mixture of two or more solvents selected from the group cyclohexanone, .gamma.-butyrolactone, ethyl lactate or ethyl pyruvate. As a result, a swelling of the SOG film is not created at the edge portion of the substrate. A crack is not therefore created at the edge portion of the SOG film, and generation of particles due to a damage at the film swelling portion thereof is prevented.Type: GrantFiled: February 12, 1997Date of Patent: July 14, 1998Assignee: Dainippon Screen Mfg. Co. Ltd.Inventors: Tetsuro Yamashita, Tsuyoshi Mitsuhashi, Manabu Yabe
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Patent number: 5772902Abstract: A method is provided for inhibiting stiction of suspended microstructures during post-release-etch rinsing and drying. The microstructures are shaped to include additional convex corners at regions of the released portion of the microstructure that can undergo substantial displacement toward the substrate. A stiction-inhibition method also includes incorporating clefts between the microstructure and adjacent field regions at regions of the microstructure which cannot undergo substantial displacement toward the substrate. Methods for inhibiting stiction are also provided wherein high-temperature rinse liquid is used and wherein a high-temperature anneal follows a rinsing step.Type: GrantFiled: April 10, 1996Date of Patent: June 30, 1998Assignee: Carnegie Mellon UniversityInventors: Michael L. Reed, Takeshi Abe
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Patent number: 5767020Abstract: A method for preparing a semiconductor member comprises:forming a substrate having a non-porous silicon monocrystalline layer and a porous silicon layer;bonding another substrate having a surface made of an insulating material to the surface of the monocrystalline layer; andetching to remove the porous silicon layer by immersing in an etching solution.Type: GrantFiled: February 14, 1992Date of Patent: June 16, 1998Assignee: Canon Kabushiki KaishaInventors: Kiyofumi Sakaguchi, Takao Yonehara, Nobuhiko Sato
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Patent number: 5753134Abstract: For producing a layer having reduced mechanical stresses, the layer is composed of at least two sub-layers that are matched to one another such that stress gradients in the two layers substantially compensate. The method is particularly employable in the manufacture of structures in surface micromechanics.Type: GrantFiled: November 23, 1994Date of Patent: May 19, 1998Assignee: Siemens AktiengesellschaftInventor: Markus Biebl
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Patent number: 5738800Abstract: A composition is provided for polishing a composite comprised of silica and silicon nitride comprising: an aqueous medium, abrasive particles, a surfactant, and a compound which complexes with the silica and silicon nitride wherein the complexing agent has has two or more functional groups each having a dissociable proton, the functional groups being the same or different.Type: GrantFiled: February 19, 1997Date of Patent: April 14, 1998Assignee: Rodel, Inc.Inventors: Sharath D. Hosali, Anantha R. Sethuraman, Jiun-Fang Wang, Lee Melbourne Cook
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Patent number: 5716535Abstract: A surface having exposed doped silicon dioxide such as BPSG is cleaned with a solution that etches thermal oxide at least one-third as fast as it etches the exposed doped silicon dioxide, resulting in more thorough cleaning with less removal of the exposed doped silicon dioxide. Specific applications to formation of container capacitors are disclosed. Preferred cleaning solutions include about 46 parts ammonium fluoride, about 9.5 parts hydrogen fluoride, and about 8.5 parts ammonium hydroxide in about 100 parts water by weight; and about 670 parts ammonium fluoride and about 3 parts hydrogen fluoride in about 1000 parts water by weight. The latter solution is also useful in cleaning methods in which a refractory metal silicide is exposed to the cleaning solution such as in cleaning prior to spacer formation or prior to a gate stack contact fill, in which case about 670 parts ammonium fluoride and about 1.6 parts hydrogen fluoride in about 1000 parts water is most preferred.Type: GrantFiled: March 5, 1996Date of Patent: February 10, 1998Assignee: Micron Technology, Inc.Inventors: Whonchee Lee, Richard C. Hawthorne, Li Li, Pai Hung Pan
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Patent number: 5711891Abstract: A method for forming v-shaped grooves in a substrate such as a channel plate is disclosed. A mask of silicon nitride formed by a thermal nitridation process protects the substrate during KOH etching.Type: GrantFiled: September 20, 1995Date of Patent: January 27, 1998Assignee: Lucent Technologies Inc.Inventor: Charles Walter Pearce
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Patent number: 5683593Abstract: An inventive method for manufacturing an array of thin film actuated mirrors for use in an optical projection system includes the steps of: (1) providing an active matrix; (2) depositing a thin film sacrificial layer; (3) ion-implanting the thin film sacrificial layer; (4) creating an array of empty cavities; (5) depositing an elastic layer; (6) forming an array of conduits; (7) depositing a second thin film, a thin film electrodisplacive and a first thin film layers, successively, thereby forming a multiple layered structure; (8) patterning the multiple layered structure into an array of semifinished actuated mirrors; (9) forming a thin film protection layer covering each of the semifinished actuated mirrors; (10) removing the thin film sacrificial layer by using an etchant; (11) rinsing away the etchant by using a rinse; (12) removing the rinse; and (13) removing the thin film protection layer, thereby forming the array of thin film actuated mirrors.Type: GrantFiled: March 4, 1996Date of Patent: November 4, 1997Assignee: Daewoo Electronics Co., Ltd.Inventors: Joon-Mo Kim, Young-Jun Choi
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Patent number: 5681484Abstract: A system for processing a plurality of tests or syntheses in parallel comprising a sample channel for moving samples into a microlaboratory array of a plurality of wells connected by one or more channels for the testing-or synthesis of samples, a station for housing the array and an optical system comprising at least one light source and at least one light detector for measuring the samples in the array, and a means of electrically connecting said array to an apparatus capable of monitoring and controlling the flow of fluids into the array. Samples are loaded from a common loading channel into the array, processed in the wells and measurements taken by the optical system. The array can process many samples, or synthesize many compounds in parallel, reducing the time required for such processes. Etching from both sides of a substrate using patterned photoresist and metal layers to form a network of capillary channels for separately transporting a plurality of different liquids.Type: GrantFiled: May 31, 1995Date of Patent: October 28, 1997Assignee: David Sarnoff Research Center, Inc.Inventors: Peter John Zanzucchi, Satyam Choudary Cherukuri, Sterling Edward McBride
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Patent number: 5676850Abstract: The present invention pertains to a method for making a plurality of barbs. The method is comprised of the steps of first forming a substrate of a first material with a layer of a second material thereon, and at predetermined discrete locations on the layer a third material. Next, there is the step of removing portions of the layer and the substrate such that a frustrum shape is formed on the surface of the substrate. Next, there is the step of removing the third material but leaving the first and second materials essentially untouched. Then, there is the step of reforming the layer made of the second material on the frustrum surface of the substrate. Next, there is the step of removing portions of the layer at essentially the center of the lowest points of the frustrum. There is then the step of removing portions of the substrate but not the second material such that a plurality of barbs is created.Type: GrantFiled: June 7, 1995Date of Patent: October 14, 1997Assignee: Carnegie Mellon UniversityInventors: Michael L. Reed, Lee E. Weiss
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Patent number: 5674406Abstract: A stopper manufacturing method of a silicon micromachining structure comping steps of growing an oxidized film on a n-type substrate; opening a n.sup.+ -diffusion window by the photo-lithography through first selective diffusion and forming a n.sup.+ -diffusion region using n-type impurity sources; forming a n.sup.+ diffusion region by the depth 0.5 to 5 .mu.m on the portion subject to form a stopper through the secondary diffusion; removing the oxidized film and growing a n-type silicon epitaxial layer on the front surface of the substrate; etching the n-type silicon epitaxial layer, selectively, exposing the n.sup.+ -layer and depositing a porous silicon layer in HF solution by the anodic reaction; and etching the porous silicon layer away in etching solution to form a microstructure, thereby preventing the side etching and the breaking down of the microstructure by the exterior shock.Type: GrantFiled: November 1, 1994Date of Patent: October 7, 1997Assignees: Kyungpook National University Sensor Technology Research Center, Mando Machinery CorporationInventor: Jong-Hyun Lee
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Patent number: 5660741Abstract: A small glass electrode and process for preparation thereof are disclosed. This small glass electrode is characterized in that said glass electrode, which has a bonded structure comprises a reference electrode composed of silver/silver chloride, a glass substrate having a pad embedded therein, said pad being composed of gold or platinum and circuit-connected to the reference electrode, and a silicon substrate having a (100) plane selectively etched by the anisotropic etching technique and comprising a groove for injecting an electrolyte composed of an aqueous solution containing chlorine such as KCl, or HCl, at least one hole for holding the electrolyte and a glass film formed in a portion corresponding to the reference electrode. By this structure, the small glass electrode can be easily manufactured at a low cost.Type: GrantFiled: June 5, 1995Date of Patent: August 26, 1997Assignee: Fujitsu Ltd.Inventors: Hiroaki Suzuki, Akio Sugama, Naomi Kojima
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Patent number: 5645737Abstract: A surface having an exposed silicon/silica interface is cleaned by an HF dip, followed immediately by a rinse in citric acid, followed by a rinse in deionized water. Low pH of the citric acid significantly prevents the formation of a charge differential between the silica and silicon portions of the surface, which charge differential would otherwise cause any silica particles present to remain on the silicon portion of the surface. Surfactant properties of the citric acid help remove any silica particles from the surface. The deionized water rinse then removes the citric acid from the surfaces, leaving a very clean, low particulate surface on both the silica and silicon portions thereof, with little or no etching of the silicon portion.Type: GrantFiled: February 21, 1996Date of Patent: July 8, 1997Assignee: Micron Technology, Inc.Inventors: Karl M. Robinson, Michael A. Walker
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Patent number: 5639387Abstract: A set of features, such as a pattern of V-grooves (20--20), can be precisely etched in a wafer (18) by patterning the V-grooves so that their axis of symmetry has a prescribed relationship with the axis of tilt (27) of the wafer surface (22).Type: GrantFiled: March 23, 1995Date of Patent: June 17, 1997Assignee: Lucent Technologies Inc.Inventor: Muhammed Afzal Shahid
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Patent number: 5637236Abstract: A method for producing a wall, roadway, sidewalk or floor of cementitious material having the appearance of natural stone and mortar including a base with an outer surface with a plurality of irregular shaped protrusions disposed in a random pattern to simulate natural stones and a plurality of simulated grout lines formed therebetween, the method including the steps of preparing a cementitious material, pouring the cementitious material into a form, vibrating the cementitious material, allowing the cementitious material to cure forming the base with the outer surface, releasing the base with the plurality of irregular shaped protrusions disposed in the random pattern to simulate natural stones and the plurality of simulated grout lines formed therebetween from the form, coloring the outer surface and accenting the plurality of simulated grout lines.Type: GrantFiled: September 1, 1994Date of Patent: June 10, 1997Inventor: Michael Lowe
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Patent number: 5633209Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.Type: GrantFiled: June 7, 1995Date of Patent: May 27, 1997Assignee: ELM Technology CorporationInventor: Glenn J. Leedy
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Patent number: 5603849Abstract: Methods and compositions are disclosed for cleaning oxides and metals from surfaces of silicon wafers in a two-phase liquid system. The two-phase system comprises a fluorine containing oxide etchant, such as hydrofluoric acid, that is soluble within two immiscible liquids of different densities such that the two liquids form separate layers. Silicon wafers are immersed into the top layer which is a nonpolar organic liquid. The bottom layer is polar liquid, preferably water. The nonpolar organic liquid includes ketones, ethers, alkanes and alkenes, but is preferably pentanone. Metal ions are transported from surfaces of the silicon wafers through the pentanone top layer to the polar water bottom layer, thereby eliminating metal ions from the pentanone. Due to relative solubilities, the concentration of hydrofluoric acid in the water bottom layer is greater than in the pentanone top layer.Type: GrantFiled: November 15, 1995Date of Patent: February 18, 1997Assignee: Micron Technology, Inc.Inventor: Li Li
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Patent number: 5602323Abstract: An object to the present invention is to provide a reference sample for easily and accurately calibrating a region of recesses and projections of several to ten angstroms for the observation of which an inter-atom force microscope displays its performance. The method manufacturing reference samples according to the present invention, wherein an object to be measured and a probe are placed in an opposed state with a minute clearance left between the surface of the former and a free end of the latter. The etching is carried out with an etching agent of an extremely low etching speed to accurately control the speed of etching a stepped portion of a pattern.Type: GrantFiled: July 18, 1994Date of Patent: February 11, 1997Inventor: Tadahiro Ohmi
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Patent number: 5593601Abstract: An etchant recipe suitable for the photo-etching process of the CrSi metalized film in the patterning of electronic circuitry. The etchant comprises 100 to 120 parts of 36.5 to 38% HCl, 1.0 to 2.0 parts of 48.8 to 49.2% HF, 0 to 10 parts of 30.0 to 32.0% H.sub.2 O.sub.2 and 50 to 100 parts of 85 to 87% H.sub.3 PO.sub.4. A 0.1 g/100 cc wetting agent is optionally added.Type: GrantFiled: June 1, 1995Date of Patent: January 14, 1997Assignee: Industrial Technology Research InstituteInventors: Hsien-Fen Hsieh, Ming-Teh Hsu
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Patent number: 5580639Abstract: A magnetic medium comprising a substrate formed with a stepped pit and a magnetic substance buried in the stepped pit.A method of manufacturing a magnetic medium comprising the steps of forming a first groove in a substrate by photoetching, forming a second groove in the first groove or in a portion adjacent to the first groove by the photoetching, the second groove being different in depth from the first groove, and burying magnetic substances into the first and second grooves.Type: GrantFiled: November 23, 1993Date of Patent: December 3, 1996Assignee: Teijin Seiki Co., Ltd.Inventors: Masayuki Togawa, Kiyoshi Toyama
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Patent number: 5579424Abstract: An arrangement for optically coupling a planar optical waveguide and an optical fiber comprises forming a planar optical waveguide on a surface of the substrate, forming a trench-like depression in the surface of the substrate leading from an end face of the planar waveguide to an edge of the substrate, forming a second holder part having a fiber secured between two planar surfaces lying in a common plane, assembling the separate holder part on a pair of planar surfaces lying on each side of the depression of said substrate so that the fiber is placed in the depression with play and the fiber will be arranged with the axis of the fiber being aligned with the axis of the planar waveguide.Type: GrantFiled: November 21, 1995Date of Patent: November 26, 1996Assignee: Siemens AktiengesellschaftInventor: Hartmut Schneider
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Patent number: 5575929Abstract: A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si.sub.3 N.sub.4) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO.sub.3 /CH.sub.3 COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary.Type: GrantFiled: June 5, 1995Date of Patent: November 19, 1996Assignee: The Regents of the University of CaliforniaInventors: Conrad M. Yu, Wing C. Hui
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Patent number: 5573680Abstract: A method of etching a generally planar surface of a semiconductor material to reveal flow pattern defects on the surface, by placing the material in a canted position, ranging from about 5.degree. to about 35.degree. from vertical, such that the generally planar surface of the material faces upwardly. The material is then immersed into a stagnant etchant solution. The surface of the material is etched such that bubbles nucleating at flow pattern defects on the surface of the canted material are released directly into the otherwise stagnant etchant solution.Type: GrantFiled: August 1, 1994Date of Patent: November 12, 1996Assignee: MEMC Electronic Materials, Inc.Inventors: Roger W. Shaw, Joseph C. Holzer
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Patent number: 5565060Abstract: Methods and compositions for the selective etching of silicon in the presence of p-doped silicon are disclosed whereby a portion of a silicon surface may be dissolved while a p-doped pattern in the surface remains substantially undissolved. The compositions comprise (a) an aqueous solution of an alkali metal hydroxide or a tetraalkylammonium hydroxide; and (b) a high flash point alcohol, phenol, polymeric alcohol, or polymeric phenol.Type: GrantFiled: June 6, 1995Date of Patent: October 15, 1996Assignee: International Business Machines CorporationInventors: Larry W. Austin, Harold G. Linde, James S. Nakos
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Patent number: 5558905Abstract: A substrate free single crystal pyroelectric film particularly suited for use in rapid thermal response sensors is made from a single crystal substrate by a method including the steps of:(A) etching a pattern into the substrate;(B) epitaxially growing a highly oriented superconducting material into the etched pattern to fill the etched pattern,(C) epitaxially growing a highly oriented crystalline film of a pyroelectric material over the entire surface of the substrate, and(D) dissolving away the highly oriented superconducting material.Type: GrantFiled: July 12, 1995Date of Patent: September 24, 1996Assignee: The United States of America as represented by the Secretary of the ArmyInventor: Donald W. Eckart
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Patent number: 5556530Abstract: An array of electrodes for use in a flat panel display includes a plurality of electron emitters formed of polycrystalline or single crystalline silicon which has been selectively etched to form pores in the emitters. The electrode array is then electroplated in a methane plasma to deposit a carbon compound such as silicon carbide on the surfaces of the emitters and in the pores of the emitters. Each emitter has a generally flat electron emitting surface which facilitates a longer life for the electrode array, the porous structure of the emitters increasing the electron emission efficiency of the emitters in relatively low electric fields. The electrode array can be integral with a support substrate by anisotropically etching the substrate to form the emitters. A layered interconnect structure can be formed on a surface of the silicon substrate for providing the interconnect structure for the electrode array.Type: GrantFiled: June 5, 1995Date of Patent: September 17, 1996Assignee: Walter J. FinklesteinInventors: Walter Finkelstein, John H. Hall
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Patent number: 5554303Abstract: An improvement is proposed in the method for the preparation of a magnetic recording medium by forming a magnetic recording layer of a magnetic alloy on the surface of a non-magnetic substrate plate of, e.g., silicon so as to impart the magnetic recording medium with improved CSS (contact-start-stop) characteristics still without affecting the magnetic recording density. The improvement can be obtained by subjecting the surface of the substrate plate, prior to the formation of the magnetic recording layer, to a surface-roughening treatment which is performed either by a dry-process such as plasma etching and reactive ion etching or by a wet-process of anisotropic etching by using an aqueous solution of sodium or potassium hydroxide as the anisotropic etching solution. In particular, the plasma etching or reactive ion etching is conducted in the presence of a particulate scattering source body of aluminum, etc.Type: GrantFiled: March 2, 1995Date of Patent: September 10, 1996Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Hideo Kaneko, Katsushi Tokunaga, Yoshio Tawara, Noboru Tamai, Yasuaki Nakazato
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Patent number: 5552015Abstract: The invention relates to a process for making an oblique-sided recess in a substrate in which areas of the surface of the substrate corresponding to the recess to be made are covered with an etching mask which is not attacked by an isotropic etching liquid, whereupon an isotropic etching is effected. In order to be able to make oblique sides of very slight slope with such a process, a layer (4) which is removable by the isotropic etching liquid is applied to the surface areas (3) of the substrate (2) before the application of the etching mask (5).Type: GrantFiled: September 28, 1994Date of Patent: September 3, 1996Assignee: Siemens AktiengesellschaftInventors: Frank Arndt, Helmut Schlaak
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Patent number: 5542558Abstract: A method for manufacturing micro-mechanical components in which a structure is produced on a silicon layer, which is to be undercut in a further step. The silicon is selectively anodized for this undercutting operation. Thus, the method enables the manufacturing of micro-mechanical components that can be integrated together with bipolar circuit elements.Type: GrantFiled: September 19, 1994Date of Patent: August 6, 1996Assignee: Robert Bosch GmbHInventors: Gerhard Benz, Jiri Marek, Martin Willmann, Frank Bantien, Horst Muenzel, Franz Laermer, Michael Offenberg, Andrea Schilp
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Patent number: 5540345Abstract: A process of producing a diffraction grating includes the steps of forming a coating layer on a first diffraction grating layer of a resin formed on a substrate without damaging the diffraction grating layer, removing a portion of the coating layer positioned on the first diffraction grating layer by etching to form a second diffraction grating layer of the coating layer having the reverse phase to that of the first diffraction grating layer, removing the first diffraction grating layer, and etching the substrate with a mask of the second diffraction grating layer, so that the diffraction grating having the reverse phase can be easily produced. When the first diffraction grating layer is left and both the first and second diffraction grating layers are used as a mask, the diffraction grating having a period half times as large as that of the first grating layer can be easily produced.Type: GrantFiled: December 27, 1993Date of Patent: July 30, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiroshi Sugimoto, Teruhito Matsui, Ken-ichi Ohtsuka, Yuji Abe, Toshiyuki Ohishi
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Patent number: 5509974Abstract: A dissolved wafer process is modified by providing an etch control seal around the perimeter of an etch resistant microstructure, such as a micromechanical or microelectromechanical device, formed on a first substrate. The microstructure is defined and shaped by a surrounding trench in the first substrate. Selected areas of the microstructure and the first substrate are bonded to an etch resistant second substrate. The selected bonding areas may comprise raised areas of the first substrate, or raised areas of the second substrate corresponding to the selected bonding areas of the first substrate. A bonded area forming a ring extending around the perimeter of the microstructure and its defining trench forms an etch control seal. The first substrate of the bonded assembly is dissolved in a selective etch so that the etch resistant microstructure remains attached to the second substrate only at the bonded areas.Type: GrantFiled: May 2, 1995Date of Patent: April 23, 1996Assignee: Rockwell International CorporationInventor: Kenneth M. Hays
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Patent number: 5500078Abstract: A method for fabricating an 8-beam bridge-type silicon acceleration sensor omprises the steps of: growing a silicon oxide layer on the top surface of the silicon substrate; forming an n.sup.+ diffusion region in the substrate by successively performing the process of opening a diffusion window in the silicon oxide layer, implanting n.sup.+ impurities in the silicon substrate through the diffusion window, and evenly diffusing the n.sup.+ impurities into the substrate; removing the silicon oxide layer, and then growing an epitaxial layer thereon; forming a plurality of piezo-resistors in the epitaxial layer by successively performing the process of growing an oxide layer on the epitaxial layer, implanting impurities, and then evenly diffusing the impurities; removing the silicon oxide layer; forming a porous silicon layer from the n.sup.Type: GrantFiled: December 23, 1994Date of Patent: March 19, 1996Assignees: Kyung Pook National University Sensor Technology Research Center, Mando Machinery CorporationInventor: Jong H. Lee
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Patent number: 5494543Abstract: A vibrator for a piezoelectric motor is produced by forming an elastic material into a predetermined shape, forming a piezoelectric material on the shaped elastic material for polarization and for driving, forming an electrode for polarization on the piezoelectric material, forming an electrode for driving on the surface of the electrode for polarization or on the piezoelectric material after stripping the electrode for polarization, and etching the elastic material into a predetermined shape has an elastic body and to remove the elastic body from a base. Instead of forming the piezoelectric material on the shaped elastic material for polarization and for driving, an electrode both for polarization and for driving can be formed on one face of the shaped elastic material, and the piezoelectric material can be formed on that electrode.Type: GrantFiled: April 19, 1993Date of Patent: February 27, 1996Assignee: Seiko Instruments Inc.Inventors: Hiroshi Okano, Hironobu Ito, Masao Kasuga
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Patent number: 5484073Abstract: A method for fabricating a connecting spring member (24) of an arbitrary shape extending between a central mass (21) and an outer support frame (23) of a sensor as shown in FIG. 7 is disclosed. Each of a pair of generally identical silicon wafers (10, 12) has an inner etch stop layer (16) applied to one face with an outer epitaxial layer (18) formed over such etch stop layer (16). A photosensitive oxide layer (30) is applied to the other face of each of the wafers (10, 12). Next, a pattern of the central mass (21) and outer support frame (23) as shown in FIG. 2 is photographically imposed on the photosensitive oxide layers (18) of each wafer (10, 12). After wet chemical etching of the wafers (10, 12) removes silicon material to the etch stop layer, and the etch stop layer is itself removed in the space between the mass and the frame, the two wafers (10, 12) are bonded to each other as shown in FIG. 5 .Type: GrantFiled: March 28, 1994Date of Patent: January 16, 1996Assignee: I/O Sensors, Inc.Inventor: Raymond K. Erickson
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Patent number: 5445707Abstract: An article comprising a substrate formed with predetermined patterns and magnetized magnetic substances arranged in the substrate in accordance with the predetermined patterns, and a method of manufacturing an article with magnetized magnetic substances arranged according to predetermined patterns, comprising the steps of arranging said magnetic substances in a substrate in accordance with the predetermined patterns and magnetizing the magnetic substances.Type: GrantFiled: June 7, 1994Date of Patent: August 29, 1995Assignee: Teijin Seiko Co., Ltd.Inventors: Kiyoshi Toyama, Masayuki Togawa
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Patent number: 5441593Abstract: An ink fill slot can be precisely manufactured in a substrate utilizing photolithographic techniques with chemical etching, plasma etching, or a combination thereof. These methods may be used in conjunction with laser ablation, mechanical abrasion, or electromechanical machining to remove additional substrate material in desired areas. The ink fill slots are appropriately configured to provide the requisite volume of ink at increasingly higher frequency of operation of the printhead by means of an extended portion that results in a reduced shelf length and thus reduced fluid impedance imparted to the ink. The extended portion is precisely etched to controllably align it with other elements of the printhead.Type: GrantFiled: October 14, 1994Date of Patent: August 15, 1995Assignee: Hewlett-Packard CorporationInventors: Kit C. Baughman, Jeffrey A. Kahn, Paul H. McClelland, Kenneth E. Trueba, Ellen R. Tappon
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Patent number: 5441597Abstract: A process for fabricating a flow control device which includes a housing with separate main flow and flow control (servo) passages between an inlet port and an exit port. A control chamber in the housing is in fluid communication with the servo passage. A flexible membrane forms a partition between the main flow passage and the control chamber. The servo passage includes a variable servo orifice upstream of the control chamber and a fixed orifice downstream of the chamber. When the servo valve is open to permit passage of fluid into the control chamber, the resultant pressure on the membrane maintains the main valve closed. The main valve opens in response to closing the servo valve. The fixed orifice has a profile sufficiently small to provide for an acceptable leak or continuous fluid flow through the device when the servo valve is open, and further provides for a soft start when the servo valve is closed to open the main valve.Type: GrantFiled: April 21, 1994Date of Patent: August 15, 1995Assignee: Honeywell Inc.Inventors: Ulrich Bonne, Thomas R. Ohnstein
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Patent number: 5441600Abstract: Extremely high aspect ratio vertical walls may be constructed using sodium hydroxide etches of (100) orientation silicon. Mask bodies 18a, 18b and 18c are used to form vertical wall sections 20a, 20b and 20c from a silicon substrate 10.Type: GrantFiled: July 9, 1993Date of Patent: August 15, 1995Assignee: Boston UniversityInventor: Jan G. Smits
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Patent number: 5439554Abstract: There is disclosed a method for fabricating a liquid jet recording head having heat acting portions, communicating to orifices for liquid discharge, for applying heat energy to a liquid to form a bubble therein, electricity-heat converters for generating said heat energy, pairs of electrodes, and an upper protective layer, characterized in that the wet etching rate of electrode layer is higher on the upper portion in a direction of film thickness than on the lower portion.Type: GrantFiled: June 9, 1993Date of Patent: August 8, 1995Assignee: Canon Kabushiki KaishaInventors: Hideo Tamura, Keiichi Murakami
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Patent number: 5437762Abstract: The invention concerns a method of forming various kinds of SOI structures and semiconductor memory devices using the forming technique. It is useful, for example, in SRAM or EEPROM devices. In EEPROM, it relates, in particular, to a method of manufacturing a non-volatile memory device in which a control gate electrode layer is laminated by way of an insulator film on a floating gate electrode layer. It includes a method of manufacturing a structure via the steps of forming an etching stopping layer on the surface of a silicon substrate, forming an epitaxially grown silicon layer on said etching stopping layer, bonding said silicon substrate formed with said silicon layer with another substrate as the insulator substrate, grinding said silicon substrate from the rear face and etching it until said etching stopping layer is exposed and removing said etching stopper layer, with or without polishing the other surface of said silicon substrate.Type: GrantFiled: July 13, 1994Date of Patent: August 1, 1995Assignee: Siemens AktiengesellschaftInventors: Akihiko Ochiai, Makoto Hashimoto, Takeshi Matsushita, Machio Yamagishi, Hiroshi Sato, Muneharu Shimanoe
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Patent number: 5437733Abstract: A plane of a treatment liquid holder having a number of through holes faces a treatment surface of a substrate. A treatment liquid is held between the treatment surface and the liquid holder by utilizing a surface tension of the treatment liquid. Since the treatment liquid is applied only to the treatment surface, an extremely small amount of treatment liquid suffices for the treatment. In addition, since a fresh treatment liquid can be used in every treatment, cross-contamination is suppressed and the treatment can be performed with safety at a low cost.Type: GrantFiled: October 17, 1991Date of Patent: August 1, 1995Assignee: Kabushiki Kaisha ToshibaInventor: Katsuya Okumura
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Patent number: 5431775Abstract: A method of forming optical light guides through silicon is disclosed wherein such light guides extend from a first (or front) surface along a preferred crystallographic direction to a second (or back) surface.Type: GrantFiled: July 29, 1994Date of Patent: July 11, 1995Assignee: Eastman Kodak CompanyInventor: Eric T. Prince
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Patent number: 5429714Abstract: A method of forming a silicon oxide isolation region on the surface of a silicon wafer consisting of a thin layer of silicon oxide on the wafer, a layer of impurity-doped polysilicon, and a layer of silicon nitride. The oxidation mask is formed by patterning the silicon nitride layer and at least a portion of the doped polysilicon layer. The silicon oxide field isolation region is formed by subjecting the structure to a thermal oxidation ambient. The oxidation mask is removed in one continuous etching step using a single etchant, such as phosphoric acid which etches the silicon nitride and polysilicon layers at substantially the same rate to complete the formation of the isolation region without pitting the monocrystalline substrate.Type: GrantFiled: May 31, 1994Date of Patent: July 4, 1995Assignees: ETRON Technology Inc., Industrial Technology Research InstituteInventors: Hsiao-Chin Tuan, Hu H. Chao
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Patent number: 5429711Abstract: There is disclosed a wafer-manufacturing method in which a single crystal ingot is first sliced into a plurality of wafers, and both surfaces of each wafer are subjected to grinding or lapping operation. Then, the front and back surfaces of the wafer are subjected to etching. Thereafter, the back surface of the wafer is subjected to chemical mechanical polishing to half-polish the same, following which the wafer is placed on a polishing machine, with the half-polished back surface of the wafer being adhered to a carrier plate; and the front surface of the wafer is mirror-polished. In the foregoing, a polysilicon film for extrinsic gettering may be formed on the back surface of the etched wafer prior to the half-polishing.Type: GrantFiled: August 9, 1993Date of Patent: July 4, 1995Assignees: Mitsubishi Materials Corporation, Mitsubishi Materials Silicon CorporationInventors: Mineo Watanabe, Hitoshi Harada, Masanori Takemura
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Patent number: 5427648Abstract: Porous silicon is formed by patterning a single crystal silicon substrate prior to electrochemically etching the same. The process is a controlled method of fabricating silicon microstructures which exhibit luminescence and are useful in optoelectronic devices, such as light emitting diodes. The porous silicon produced has a high degree of uniformity and repeatability.Type: GrantFiled: August 15, 1994Date of Patent: June 27, 1995Assignee: The United States of America as represented by the Secretary of the ArmyInventors: Jagadeesh Pamulapati, Hongen Shen, Mitra Dutta
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Patent number: 5425841Abstract: An electromechanical transducer is provided, and the process for making it utilizes a piezoresistive element or gage which is dielectrically isolated from a gap spanning member and substrate upon which it is supported. The gage of the invention is a force gage and is derived from a sacrificial wafer by a series of etching and bonding steps which ultimately provide a gage with substantially reduced strain energy requirements.Type: GrantFiled: June 16, 1993Date of Patent: June 20, 1995Assignee: Kulite Semiconductor Products, Inc.Inventors: Anthony D. Kurtz, Alexander A. Ned
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Patent number: 5425847Abstract: Method of removing a layer of glass formed on a sintered body which is manufactured by hot isostatic pressing of a preformed body of inorganic powder in a pressure medium at a sintering temperature, wherein the sintered body of inorganic powder is retained in an alkali solution of at least 2 percent by weight at a temperature not less than 100.degree. C. for not less than one hour.Type: GrantFiled: September 3, 1993Date of Patent: June 20, 1995Assignee: NGK Insulators, Ltd.Inventors: Akira Narukawa, Mitsuyoshi Watanabe
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Patent number: 5421952Abstract: A method for fabricating silicon injection plates is both highly precise and particularly simple. The silicon injection plate is formed by an upper silicon plate having injection holes and a lower silicon plate having a through opening and channels. The lower silicon plate is fabricated by simultaneous, double-sided etching of silicon.Type: GrantFiled: October 4, 1993Date of Patent: June 6, 1995Assignee: Robert Bosch GmbHInventors: Juergen Buchholz, Udo Jauernig, Alexandra Boehringer, Guenther Findler, Horst Muenzel
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Patent number: 5421958Abstract: A pattern of porous silicon is produced in the surface of a silicon substrate by forming a pattern of crystal defects in said surface, preferably by applying an ion milling beam through openings in a photoresist layer to the surface, and then exposing said surface to a stain etchant, such as HF:HNO.sub.3 :H.sub.2 O. The defected crystal will preferentially etch to form a pattern of porous silicon. When the amorphous content of the porous silicon exceeds 70% the porous silicon pattern emits visible light at room temperature.Type: GrantFiled: June 7, 1993Date of Patent: June 6, 1995Assignee: The United States of America as represented by the Administrator of the United States National Aeronautics and Space AdministrationInventors: Robert W. Fathauer, Eric W. Jones