Substrate Contains Silicon Or Silicon Compound Patents (Class 216/99)
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Patent number: 6431186Abstract: A simple cleaning method which can remove metal, organic and fine particle contaminants on the surface of electronic components, and especially those on silicon bases, and also suppress an increase in the roughness of base surface on the order of atoms during cleaning processes, is provided by cleaning with an oxidizing cleaning fluid, followed by cleaning with a reducing cleaning fluid with the application of ultrasonic vibrations.Type: GrantFiled: October 12, 1999Date of Patent: August 13, 2002Assignee: Kurita Water Industries Ltd.Inventors: Hiroshi Morita, Junichi Ida
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Patent number: 6428718Abstract: According to an example embodiment, a semiconductor device having a back side and a circuit side opposite the back side is analyzed. The semiconductor device includes bulk silicon in the back side and also includes epitaxial silicon. A wet etch solution comprising aqueous tetramethylammonium hydroxide (TMAHW) is directed at the back side. Using the wet etch solution, the back side is selectively etched and an exposed region is formed. The etching is selective to the bulk silicon. When the etching process encounters the epitaxial silicon, the etch rate slows and is used as an endpoint indicator of the selective etching process. Once the etching process is stopped, the circuitry is accessed via the exposed region.Type: GrantFiled: August 26, 1999Date of Patent: August 6, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Jeffrey Birdsley, Brennan Davis
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Patent number: 6413440Abstract: In a process for manufacturing an electrode (1) on a substrate (2) using a conventional structuring process, an electrically conducting surface structure is created which has at least one tip (3) or edge (4). In the area of the tip (3) or edge (4), an electrode layer (5) is galvanized onto the substrate (2) and/or applied by electrostatic powder coating. Then, a surface area of the substrate (2), which surrounds the electrode layer (5) located on the tip (3) or edge (4), is converted into an insulating layer (8) by a chemical reaction. The electrode layer (5) can also be applied in a manner where, in the area of the tip (3) or edge (4), a chemical is released, which upon irradiation by electromagnetic and/or particle radiation, precipitates an electrically conducting material. This chemical is then impinged in the area of the tip (3) or edge (4) with optical radiation.Type: GrantFiled: July 13, 1999Date of Patent: July 2, 2002Assignee: Micronas GmbHInventor: Günter Igel
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Publication number: 20020079290Abstract: A new and improved etching solution and etching method provide wet chemical pyramidal texture etching of (100) silicon surfaces. A uniform and completely pyramidal texture etching of silicon surfaces is achieved with an etching solution including water, an alkaline reagent, and isopropanol together with an aqueous alkaline ethylene glycol solution.Type: ApplicationFiled: March 5, 2002Publication date: June 27, 2002Inventor: Konstantin Holdermann
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Patent number: 6407005Abstract: A method for fabricating a field oxide layer capable of being applied to highly integrated circuits. The semiconductor device according to the present invention prevents electric field concentration at the corners of the active region, by filling a recess generated in a field oxide layer with an additional oxide spacer. The method includes the steps of a) forming a trench in a semiconductor substrate; b) forming an insulating layer on the resulting structure and burying the trench; c) forming a field oxide layer by controlling topology of the insulating layer in a wet etching process, wherein the wet etching process forms a recess at a corner of the field oxide layer so that a portion of sidewalls of the active region is exposed; d) forming an additional field oxide spacer layer at the recess in order to bury the exposed sidewall portion of the active region; and e) vertically growing an epitaxial layer on the exposed active region.Type: GrantFiled: December 26, 2000Date of Patent: June 18, 2002Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Dae-Hee Weon
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Patent number: 6403484Abstract: A method of forming shallow trench isolations is described. A plurality of isolation trenches are etched through a first etch stop layer into the underlying semiconductor substrate. An oxide layer is deposited over the first etch stop layer and within the isolation trenches using a high density plasma chemical vapor deposition process (HDP-CVD) wherein after the oxide layer fills the isolation trenches, the deposition component is discontinued while continuing the sputtering component until corners of the first etch stop layer are exposed at edges of the isolation trenches whereby the oxide layer within the isolation trenches is disconnected from the oxide layer overlying the first etch stop layer. Thereafter, a second etch stop layer is deposited overlying the oxide layer within the isolation trenches, the oxide layer overlying the first etch stop layer, and the exposed first etch stop layer corners.Type: GrantFiled: March 12, 2001Date of Patent: June 11, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Victor Seng Keong Lim, Lap Chan, James Lee, Chen Feng, Wang Ling Goh
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Patent number: 6402971Abstract: The method for manufacturing an ink jet recording head includes forming an ink pool for supplying ink to a nozzle for jetting ink on a substrate. The method also includes forming, in sequence on the substrate, a diaphragm for pressurizing ink in the ink chamber, a piezoelectric thin film serving as a pressurization source for the diaphragm, and an electrode for the piezoelectric thin film. Patterning of both the piezoelectric thin film and the electrode is done at the same time.Type: GrantFiled: January 28, 1999Date of Patent: June 11, 2002Assignee: Seiko Epson CorporationInventors: Tsutomu Hashizume, Tetsushi Takahashi
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Patent number: 6402973Abstract: A silicon substrate is prepared by furnishing a silicon substrate (10) having a step (11) of at least 5 &mgr;m high on one surface, forming by high pressure heat oxidation an oxide film (12) which is thinner than the step, and removing the oxide film on the higher surface region until the silicon surface is exposed in the higher surface region while leaving the oxide film on the lower surface region. Because of excellent electrical properties, minimized warpage, a substantially constant oxygen concentration, and a definitely ascertainable oxide-silicon boundary, the silicon substrate is suitable for use in optical waveguide devices.Type: GrantFiled: July 27, 2000Date of Patent: June 11, 2002Assignees: NTT Electronics Corp., Shin-Etsu Chemical Co., Ltd.Inventors: Yasushi Maeda, Masaharu Horiguchi, Shinji Makikawa, Seiki Ejima
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Patent number: 6399504Abstract: A surface having exposed doped silicon dioxide such as BPSG is cleaned with a solution that etches thermal oxide at least one-third as fast as it etches the exposed doped silicon dioxide, resulting in more thorough cleaning with less removal of the exposed doped silicon dioxide. Specific applications to formation of container capacitors are disclosed. Preferred cleaning solutions include about 46 parts ammonium fluoride, about 9.5 parts hydrogen fluoride, and about 8.5 parts ammonium hydroxide in about 100 parts water by weight; and about 670 parts ammonium fluoride and about 3 parts hydrogen fluoride in about 1000 parts water by weight. The latter solution is also useful in cleaning methods in which a refractory metal silicide is exposed to the cleaning solution such as in cleaning prior to spacer formation or prior to a gate stack contact fill, in which case about 670 parts ammonium fluoride and about 1.6 parts hydrogen fluoride in about 1000 parts water is most preferred.Type: GrantFiled: November 23, 1999Date of Patent: June 4, 2002Assignee: Micron Technology, Inc.Inventors: Whonchee Lee, Richard C. Hawthorne, Li Li, Pai Hung Pan
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Patent number: 6393685Abstract: A wafer level interconnecting mechanism for assembling and packaging multiple MEMS devices (modules), using microfabricated, interlocking, mechanical joints to interconnect different modules and to create miniature devices. Various devices can be fabricated using these joints, including fiber-optic switches, xyz translational stages, push-n-lock locking mechanisms, slide-n-lock locking mechanisms, t-locking joints, fluidic interconnects, on/off valves, optical fiber couplers with xy adjustments, specimen holders, and membrane stops.Type: GrantFiled: June 9, 1998Date of Patent: May 28, 2002Assignee: The Regents of the University of CaliforniaInventor: Scott D. Collins
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Patent number: 6395646Abstract: A machine for etching the edge of a wafer comprising a rotating holding plate having a work platform, the work platform having a first fillister for spraying gas to maintain a certain distance between the work platform and the wafer, a second fillister set around the periphery of the first fillister for reducing pressure of the sprayed gas at the edge of the wafer, and a plurality of holding pins; a vacuum manipulator; and an etching solution leading apparatus.Type: GrantFiled: April 13, 2000Date of Patent: May 28, 2002Assignee: Winbond Electronics Corp.Inventor: Yueh-liang Liu
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Patent number: 6390439Abstract: Hybrid molds for molding a multiplicity of solder balls for use in a molten solder screening process and methods for preparing such molds are disclosed. A method for forming the multiplicity of cavities in a pyramidal shape by anisotropically etching a crystalline silicon substrate along a specific crystallographic plane is utilized to form a crystalline silicon face plate used in the present invention hybrid mold. In a preferred embodiment, a silicon face plate is bonded to a borosilicate glass backing plate by adhesive means in a method that ensures coplanarity is achieved between the top surfaces of the silicon face plate and the glass backing plate. In an alternate embodiment, an additional glass frame is used for bonding a silicon face plate to a glass backing plate, again with ensured coplanarity between the top surfaces of the silicon face plate and the glass frame. In a second alternate embodiment, a silicon face plate is encased in an extender material which may be borosilicate glass or a polymer.Type: GrantFiled: April 7, 1999Date of Patent: May 21, 2002Assignee: International Business Machines CorporationInventors: Steven A. Cordes, David Hirsch Danovitch, Peter Alfred Gruber, James Louis Speidell, Joseph Peter Zinter
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Publication number: 20020056700Abstract: The present invention aims at high-yield manufacture of a semiconductor device of stable quality. A silicon oxide film, a polysilicon film, and a silicon nitride film are formed on a silicon substrate. After a predetermined trench structure has been formed in the films by means of etching, an oxide film is deposited so as to fill in the trench structure. The silicon substrate is subjected to chemical-and-mechanical polishing (CMP) while the silicon nitride film is used as a stopper film, thereby forming an isolation oxide film. The thickness of the isolation oxide film is measured, and the isolation oxide film is etched under the requirements which have been determined on the basis of the resultant measurement value, by means of the feedforward technique. Subsequently, the silicon nitride film and the polysilicon film are removed sequentially.Type: ApplicationFiled: April 5, 2001Publication date: May 16, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Toshiaki Ohmori
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Patent number: 6387290Abstract: A microfilter utilizing the principles of tangential flow to prevent clogging, and sloped channel sides to overcome surface tension effects is provided which has feed inlet and exit connected by a feed flow channel; a barrier channel parallel to the feed flow channel, and a filtrate collection channel parallel to the barrier channel so that liquid can flow from the feed flow channel through the barrier channel which is too small to accommodate the particles, into the filtrate collection channel, and from then through a filtrate flow channel to a filtrate exit. Several picoliters of cell-free plasma are recovered from one drop of blood for analysis.Type: GrantFiled: July 2, 1999Date of Patent: May 14, 2002Assignee: University of WashingtonInventors: James P. Brody, Thor D. Osborn
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Patent number: 6387851Abstract: An SrTiO3 monocrystal substrate having a crystallographic plane (100) or (110) is anisotropically etched in an H3PO4 solution using an SiO2 thin film as an etching mask. The H3PO4 solution is maintained at a boiling point of approximately 150 deg. C. for increasing an etching rate and enhancing selectivity for protection with the SiO2 thin film mask.Type: GrantFiled: December 16, 1999Date of Patent: May 14, 2002Assignee: Hitachi, Ltd.Inventor: Takao Matsumoto
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Patent number: 6383937Abstract: A method is disclosed for fabricating a semiconductor device structure which include a thin foot charge drain beneath the device on a silicon substrate. The structures retain high speed operation of SOI devices. In various embodiments, the invention includes forming a first diffusion-barrier layer on a semiconductor substrate, patterning the said first diffusion-barrier layer and the said silicon substrate to certain depth to form a trench, forming a second diffusion-barrier layer and patterning the said second diffusion-barrier layer to form a first spacer on the sidewall of the trench. Performing a directional etching to expose a portion of the sidewall of the trench. Introducing dopants into the said exposed sidewall to form a doped regions near the sidewall. Performing an isotropic etching using halogen gas plasma.Type: GrantFiled: November 17, 2000Date of Patent: May 7, 2002Assignee: Vanguard International Semiconductor Corp.Inventor: Horng-Huei Tseng
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Publication number: 20020050483Abstract: The present invention relates to a method of cleaning and drying a semiconductor structure in a modified conventional gas etch/rinse or dryer vessel. In an embodiment of the present invention, a semiconductor structure is placed into a first treatment vessel and chemically treated. Following the chemical treatment, the semiconductor structure is transferred directly to a second treatment vessel where it is rinsed with DI water and then dried. The second treatment vessel is flooded with both DI water and a gas that is inert to the ambient, such as nitrogen, to form a DI water bath upon which an inert atmosphere is maintained during rinsing. Next, an inert gas carrier laden with IPA vapor is fed into the second treatment vessel. After sufficient time, a layer of IPA has formed upon the surface of the DI water bath to form an IPA-DI water interface.Type: ApplicationFiled: December 19, 2001Publication date: May 2, 2002Inventor: Donald L. Yates
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Patent number: 6380099Abstract: A given planarity of the underlying layer is ensured after removal of a porous layer. In the first step, a porous layer is filled with a preprocess solution (e.g., water). In the second step, the preprocess solution filling the porous layer is replaced with an etchant (e.g., fluoric acid), and the porous layer is etched by the etchant. With this process, the time in which the porous layer is filled with the etchant is shortened to suppress variations in progress of etching.Type: GrantFiled: December 15, 1998Date of Patent: April 30, 2002Assignee: Canon Kabushiki KaishaInventors: Kiyofumi Sakaguchi, Kazutaka Yanagita
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Publication number: 20020046985Abstract: A microelectromechanical (MEMS) apparatus has a base and a flap with a portion coupled to the base may be fabricated by an inventive process. The process generally involves etching one or more trenches in a backside of a base, e.g., by anisotropic etch. The trench may be etched such that an orientation of a sidewall is defined by a crystal orientation of the base material. A layer of insulating material is formed on one or more sidewalls of one or more of the trenches. A conductive layer is formed on the layer of insulating material on one or more sidewalls of one or more of the trenches. The conductive layer may completely fill up the trench between the insulating materials on the sidewalls to provide the isolated electrode. Base material is removed from a portion of the base bordered by the one or more trenches to form a cavity in the base. The trench etch may stop on an etch-stop layer so that the cavity does not form all the way through the base.Type: ApplicationFiled: April 13, 2001Publication date: April 25, 2002Inventors: Michael J. Daneman, Chuang-Chia Lin, Boris Kobrin
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Patent number: 6372655Abstract: A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.Type: GrantFiled: April 17, 2001Date of Patent: April 16, 2002Assignee: Applied Materials, Inc.Inventors: Anisul Khan, Ajay Kumar, Jeffrey D. Chinn, Dragan Podlesnik
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Publication number: 20020040884Abstract: A probe tip configuration, being part of a probe (FIG. 2) for use in a scanning proximity microscope, is disclosed, comprising a cantilever beam (1) and a probe tip. Said tip comprises a first portion of a tip (2) and at least one second portion of a tip (5). Said first portion of a tip is connected to said cantilever beam whereas said second portion of a tip is placed on said first portion of a tip. Cantilever beam, first portion of a tip and second portion(s) of a tip can be composed of different materials and can be isolated each from another which makes an easy adjustement of the maximum penetration depth of the tip possible without limiting the resolution and makes it also possible to detect more than one signal of a sample at the same time using one cantilever beam.Type: ApplicationFiled: December 3, 2001Publication date: April 11, 2002Inventors: Thomas Hantschel, Wilfried Vandervorst
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Patent number: 6368982Abstract: In a method for patterning a target material on a semiconductor substrate, a first hardmask material is deposited on the target material and a second hardmask material is deposited on the first hardmask material. The first hardmask material is different from the target material, and the second hardmask material is different from the first hardmask material. A patterned structure of a patterning material such a photoresist material is formed on the second hardmask material. Any exposed region of the second hardmask material is etched such that a second hardmask structure is formed from the second hardmask material remaining under the patterned structure. The etching reactant for etching the second hardmask material to form the second hardmask structure substantially does not etch the first hardmask material. The second hardmask structure is trimmed to reduce the length at each side of the second hardmask structure.Type: GrantFiled: November 15, 2000Date of Patent: April 9, 2002Assignee: Advanced Micro Devices, Inc.Inventor: Bin Yu
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Publication number: 20020036183Abstract: A method of forming a pattern, which comprises forming a first resist film on a surface of a substrate, patterning the first resist film to form a first resist pattern, and forming a covering layer containing silicon or a metal on the first resist pattern by making use of a coating method using a solution containing a solvent which is incapable of dissolving the first resist.Type: ApplicationFiled: September 24, 2001Publication date: March 28, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Tsuyoshi Shibata
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Publication number: 20020036182Abstract: A method of manufacturing a silicon wafer including the step of flattening fine roughness existing on a side face of a silicon block or a silicon stack used for manufacturing the silicon wafer.Type: ApplicationFiled: September 20, 2001Publication date: March 28, 2002Inventors: Kimihiko Kajimoto, Junzou Wakuda
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Publication number: 20020037654Abstract: An inexpensive surface treatment solution that can selectively reduce the average roughness (Ra) of the surface of a polysilicon film formed by crystallization on an insulating substrate such as one made from glass with a laser annealing process. The surface treatment solution essentially comprises 0.01 to 0.5 wt % of hydrofluoric acid or 0.5 to 5 wt % of ammonium fluoride, 50.0 to 80.0 wt % of nitric acid and water.Type: ApplicationFiled: July 23, 2001Publication date: March 28, 2002Applicant: Kanto Kagaku Kabushiki KaishaInventors: Hidekazu Hayashi, Kenji Kageyama
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Patent number: 6361708Abstract: A method and an apparatus for polishing a metal film formed on a semiconductor device are disclosed. A semiconductor wafer is immersed in an oxidizing solution before it is polished. As a result, the undesirable part of a W film deposited on the circumferential edge of the wafer is removed by etching.Type: GrantFiled: May 14, 1998Date of Patent: March 26, 2002Assignee: NEC CorporationInventors: Akira Kubo, Mieko Suzuki
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Patent number: 6362107Abstract: The present invention relates to a polishing pad which is characterized in that it has a polishing layer of rubber A-type microhardness at least 80° and a cushioning layer of bulk modulus at least 40 MPa and tensile modulus in the range 0.1 MPa to 20 MPa, and to a polishing device which is characterized in that a semiconductor substrate is fixed to the polishing head, and an aforesaid polishing pad is fixed to the polishing platen so that the polishing layer faces the semiconductor substrate, and by rotating the aforesaid polishing head or the polishing platen, or both, the semiconductor substrate is polished.Type: GrantFiled: May 8, 2001Date of Patent: March 26, 2002Assignee: Toray Industries, Inc.Inventors: Kuniyasu Shiro, Hisashi Minamiguchi, Tetsuo Oka
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Publication number: 20020030034Abstract: A phase shifting mask repair process is described. The process uses an etching gas or a hydrofluoric acid solution to etch the quartz substrate and the characteristics of the phase shifter layer being only slightly etched when clean with a NH3/H2O2/H2O2 solution to calculate and adjust the respective processing time accordingly. As a result, the phase difference between the quartz substrate and the MoSiON phase shifter layer stays relatively the same before and after the repair process.Type: ApplicationFiled: November 30, 2000Publication date: March 14, 2002Inventor: Ching-Yu Chang
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Patent number: 6354309Abstract: Semiconductor substrates are contacted with a deionized water solution containing an acidic material.Type: GrantFiled: September 29, 2000Date of Patent: March 12, 2002Assignee: International Business Machines CorporationInventors: Russell H. Arndt, Glenn Walton Gale, Frederick William Kern, Jr., Karen P. Madden, Harald F. Okorn-Schmidt, George Francis Ouimet, Jr., Dario Salgado, Ryan Wayne Wuthrich
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Patent number: 6346485Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.Type: GrantFiled: August 7, 2000Date of Patent: February 12, 2002Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Takashi Nihonmatsu, Seiichi Miyazaki, Masahiko Yoshida, Hideo Kudo, Tadahiro Kato
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Publication number: 20020016072Abstract: An object of the present invention is to provide a method of manufacturing a semiconductor wafer in which the manufacturing efficiency of grinding using a double-headed grinding machine is improved, minute surface undulations arising through the grinding are reduced, and the yield of the manufacturing process is improved. By processing a sliced wafer using a double-headed grinding machine, a strained layer and a macroscopic undulation component formed on the wafer surfaces during the slicing are removed, and the degree of flatness of the wafer is improved, and by subsequently carrying out both-surfaces lapping, minute surface undulations that arose during the double-headed grinding are removed.Type: ApplicationFiled: August 2, 2001Publication date: February 7, 2002Applicant: Sumitomo Metal Industries, Ltd.Inventors: Tomohiro Hashii, Tooru Watanabe
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Patent number: 6344150Abstract: A method of etching structural depressions in a substrate comprises aligning the ferroelectric domains within the substrate to domain orientations selected from two or more possible domain orientations, whereby the rate at which substrate material is etched by an etchant varies with the domain orientation of the substrate material; and exposing the substrate to the etchant.Type: GrantFiled: November 23, 1999Date of Patent: February 5, 2002Assignee: Qinetiq LimitedInventors: Robert W. Eason, Graeme W. Ross, Peter G. R. Smith, Ian E. Barry
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Patent number: 6335294Abstract: A method for removing a formation of oxide of titanium that is generated as a byproduct of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The method applies a chemical reagent to the FET at a predetermined temperature, and for a predetermined period of time, necessary for removing the formation, wherein the reagent does not chemically react with the cobalt disilicide. A reagent that accomplishes this task comprises water (H2O), ammonium hydroxide (NH4OH), and hydrogen peroxide (H2O2), wherein the NH4OH and the H2O2 each comprise approximately 4% of the total reagent volume. An effective temperature is 65° C. combined with a 3 minute period of application.Type: GrantFiled: April 22, 1999Date of Patent: January 1, 2002Assignee: International Business Machines CorporationInventors: David Paul Agnello, Mary Conroy Bushey, Donna K. Johnson, Jerome Brett Lasky, Peter James Lindgren, Kirk David Peterson
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Patent number: 6331257Abstract: Methods for the design and fabrication of micro-electro-mechanical switches are disclosed. Two different switch designs with three different switch fabrication techniques are presented for a total of six switch structures. Each switch has a multiple-layer armature with a suspended biasing electrode and a conducting transmission line affixed to the structural layer of the armature. A conducting dimple is connected to the conducting line to provide a reliable region of contact for the switch. The switch is fabricated using silicon nitride as the armature structural layer and silicon dioxide as the sacrificial layer supporting the armature during fabrication. Hydrofluoric acid is used to remove the silicon dioxide layer with post-processing in a critical point dryer to increase yield.Type: GrantFiled: November 30, 1999Date of Patent: December 18, 2001Assignee: Hughes Electronics CorporationInventors: Robert Y. Loo, Adele Schmitz, Julia Brown, James Foschaar, Daniel J. Hyman, Tsung-Yuan Hsu
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Patent number: 6328902Abstract: A probe tip configuration, being part of a probe (FIG. 2) for use in a scanning proximity microscope, is disclosed, comprising a cantilever beam (1) and a probe tip. Said tip comprises a first portion of a tip (2) and at least one second portion of a tip (5). Said first portion of a tip is connected to said cantilever beam whereas said second portion of a tip is placed on said first portion of a tip. Cantilever beam, first portion of a tip and second portion(s) of a tip can be composed of different materials and can be isolated each from another which makes an easy adjustement of the maximum penetration depth of the tip possible without limiting the resolution and makes it also possible to detect more than one signal of a sample at the same time using one cantilever beam.Type: GrantFiled: August 14, 1998Date of Patent: December 11, 2001Assignee: IMEC vzwInventors: Thomas Hantschel, Wilfried Vandervorst
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Patent number: 6322954Abstract: The present invention relates to a process for selectively etching polysilicon utilizing an ammonia solution etchant that is selective to silicon dioxide and photoresist. In one embodiment of the inventive material, a polysilicon layer is formed over a semiconductor substrate. A photoresist layer is then formed over the polysilicon layer. A portion of the photoresist layer is selectively removed by an edge bead removal process along the edge of the semiconductor wafer so as to expose a portion of the polysilicon layer. The exposed polysilicon layer is selectively removed by an etch conducted at a temperature range from about 20° C. to about 30° C. with an ammonium hydroxide etchant having an ammonia concentration in the range of about 1% to about 5% by volume. The etch is selective to the photoresist layer.Type: GrantFiled: November 2, 1999Date of Patent: November 27, 2001Assignee: Micron TechnologyInventor: Li Li
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Patent number: 6305080Abstract: A method for manufacturing an ink jet recording head, which is provided with orifices for liquid discharge use, nozzles communicated with the orifices, electrothermal converting members arranged in the nozzles to form bubbles in the liquid by providing thermal energy for it, the liquid chamber communicated with the nozzles to supply liquid to the nozzles and a substrate having the electrothermal converting members provided therefor, comprises the steps of preparing the substrate to be a silicon substrate having (100) plane or (110) plane crystal axes therefor, forming organic resin layer at least in the liquid chamber on the silicon substrate, then, removing by means of anisotropic etching a part of the liquid chamber formation portion of the substrate from the reverse side of the formation surface of the organic resin layer and forming an elastic member portion formed by the membrane of the organic resin layer in the liquid chamber.Type: GrantFiled: December 17, 1998Date of Patent: October 23, 2001Assignee: Canon Kabushiki KaishaInventors: Hirokazu Komuro, Takashi Fujikawa, Ken Tsuchii, Norio Ohkuma, Hideto Yokoi, Shuichi Murakami
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Patent number: 6306774Abstract: In one aspect, the invention encompasses a semiconductor processing method comprising contacting a surface with a liquid solution comprising at least one fluorine-containing species and a temperature of at least about 40° C. In another aspect, the invention encompasses a method of passivating a silicon-comprising layer comprising contacting the layer with a liquid solution comprising hydrogen fluoride and a temperature of at least about 40° C. In yet another aspect, the invention encompasses a method of forming hemispherical grain polysilicon comprising: a) forming a layer comprising substantially amorphous silicon over a substrate; b) contacting the layer comprising substantially amorphous silicon with a liquid solution comprising fluorine-containing species and a temperature of at least about 40° C.; c) seeding the layer comprising substantially amorphous silicon; and d) annealing the seeded layer to convert at least a portion of the seeded layer to hemispherical grain polysilicon.Type: GrantFiled: August 25, 1999Date of Patent: October 23, 2001Assignee: Micron Technology, Inc.Inventors: Er-Xuan Ping, Li Li
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Patent number: 6306775Abstract: The invention includes methods of selectively etching polysilicon relative to at least one of deposited oxide, thermally grown oxide and nitride, and methods of selectively etching polysilicon relative to BPSG. In one implementation, a method of selectively etching polysilicon relative to at least one of deposited oxide, thermally grown oxide and nitride, includes forming a substrate to have a layer comprising polysilicon received over at least one layer comprising at least one of deposited oxide, thermally grown oxide, and nitride. The polysilicon is exposed to an aqueous solution comprising NH4F, an oxidizer, CH3COOH, TMAH, and HF under conditions effective to selectively etch at least a portion of the polysilicon comprising layer relative to an ultimately exposed portion of the at least one of deposited oxide, thermally grown oxide, and nitride.Type: GrantFiled: June 21, 2000Date of Patent: October 23, 2001Assignee: Micron Technology, Inc.Inventor: Andrew Li
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Patent number: 6303515Abstract: In one aspect, the invention encompasses a semiconductor processing method comprising contacting a surface with a liquid solution comprising at least one fluorine-containing species and a temperature of at least about 40° C. In another aspect, the invention encompasses a method of passivating a silicon-comprising layer comprising contacting the layer with a liquid solution comprising hydrogen fluoride and a temperature of at least about 40° C. In yet another aspect, the invention encompasses a method of forming hemispherical grain polysilicon comprising: a) forming a layer comprising substantially amorphous silicon over a substrate; b) contacting the layer comprising substantially amorphous silicon with a liquid solution comprising fluorine-containing species and a temperature of at least about 40° C.; c) seeding the layer comprising substantially amorphous silicon; and d) annealing the seeded layer to convert at least a portion of the seeded layer to hemispherical grain polysilicon.Type: GrantFiled: August 26, 1999Date of Patent: October 16, 2001Assignee: Micron Technology, Inc.Inventors: Er-Xuan Ping, Li Li
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Patent number: 6303506Abstract: An aqueous slurry-less composition for chemical-mechanical-polishing of a silicon dioxide workpiece comprising: a cationic surfactant that is soluble and ionized at neutral to alkaline pH conditions, in which the cationic surfactant is present in an aqueous slurry-less composition in an amount less than its critical micelle concentration.Type: GrantFiled: September 30, 1999Date of Patent: October 16, 2001Assignee: Infineon Technologies AGInventors: Haruki Nojo, Ronald J. Schutz, Ravikumar Ramachandran
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Patent number: 6303042Abstract: A method for forming an ink jet nozzle plate includes providing a structure having a top substrate layer, a bottom substrate layer, and a buried layer disposed between the top substrate layer and the bottom substrate layer; providing a composite mask over the top substrate layer having a cavity mask which provides openings and a bore mask having openings which are entirely within the openings of the cavity mask and extend to the top substrate layer; anisotopically etching through the bore mask openings through top substrate layer and the buried layer into a portion of the bottom substrate layer; removing the bore mask and etching the top and bottom substrate layers without substantially affecting the buried layer to extend the openings in the top substrate layer and the bottom substrate layer; removing the cavity mask and attaching the top substrate layer to a base provided with ink delivery channels with correspond to the openings in the buried layer; and removing the bottom substrate layer.Type: GrantFiled: March 2, 1999Date of Patent: October 16, 2001Assignee: Eastman Kodak CompanyInventors: Gilbert A. Hawkins, Xin Wen
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Publication number: 20010027798Abstract: A polishing liquid for components, preferably wafers, a process for producing a polishing liquid and a process for chemical mechanical polishing of components are provided. The polishing liquid has a polishing base liquid and an oxidizing agent. The aim is to provide an economical polishing agent which is also simple to produce, which can be used as an alkaline or acidic polishing agent and with which metallic layers in particular can be polished. Ozone, which is used as an oxidizing agent, is a strong oxidizing agent having a redox potential that is sufficient for oxidizing or polishing the metals in an acidic or alkaline environment.Type: ApplicationFiled: March 19, 2001Publication date: October 11, 2001Inventors: Rainer Flierl, Annette Sanger
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Publication number: 20010024883Abstract: A process for producing multiple undercut profiles in a single material. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch which produces a polymer film in the undercut created by the first wet etch. The polymer film prevents further etching of the undercut portion during a second wet etch. Thus, an undercut profile can be obtained having a larger undercut in an underlying portion of the work piece, utilizing only a single resist application step. The work piece may be a multi-layer work piece having different layers formed of the same material, or it may be a single layer of material.Type: ApplicationFiled: March 23, 2001Publication date: September 27, 2001Applicant: Micron Technology, Inc.Inventors: Karen Huang, Christophe Pierrat
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Publication number: 20010023829Abstract: A method for plating an electrically conductive substance, which includes the steps of contacting the electrically conductive substance with a plating agent in dilute solution, in which the plating agent is present in a concentration of 200 mM at most, and subjecting the plating agent adjacent to the electrically conducive substance to an electric field.Type: ApplicationFiled: March 1, 2001Publication date: September 27, 2001Applicant: Obducat ABInventors: Lennart Olsson, Babak Heidari
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Patent number: 6290863Abstract: The present invention provides a dynamic-flow system that uses a vacuum to pull an etchant or other processing agent through a nozzle onto the surface of the work object. The processing agent can only communicate with the vacuum and be pulled onto the wafer surface when the nozzle is sealed against the work object. Therefore, the processing agent is dispensed onto the surface of the wafer or other work object under a negative rather than a positive pressure. Accordingly, the dispensation of the processing agent is self-stopping in the event that seal of the nozzle against the work object fails. The present invention also provides a novel nozzle for dispensing a processing agent onto a selected area of a work object. The nozzle of the present invention provides a substantially unidirectional flow of processing agent along the surface of a work object and maximizes the contact time of the processing agent at the surface of the work object.Type: GrantFiled: July 31, 1999Date of Patent: September 18, 2001Assignee: Micron Technology, Inc.Inventors: Paul A. Morgan, Kevin Torek
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Patent number: 6290859Abstract: A process is disclosed whereby a 5-50-nanometer-thick conformal tungsten coating can be formed over exposed semiconductor surfaces (e.g. silicon, germanium or silicon carbide) within a microelectromechanical (MEM) device for improved wear resistance and reliability. The tungsten coating is formed after cleaning the semiconductor surfaces to remove any organic material and oxide film from the surface. A final in situ cleaning step is performed by heating a substrate containing the MEM device to a temperature in the range of 200-600 ° C. in the presence of gaseous nitrogen trifluoride (NF3). The tungsten coating can then be formed by a chemical reaction between the semiconductor surfaces and tungsten hexafluoride (WF6) at an elevated temperature, preferably about 450° C. The tungsten deposition process is self-limiting and covers all exposed semiconductor surfaces including surfaces in close contact.Type: GrantFiled: November 12, 1999Date of Patent: September 18, 2001Assignee: Sandia CorporationInventors: James G. Fleming, Seethambal S. Mani, Jeffry J. Sniegowski, Robert S. Blewer
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Publication number: 20010017287Abstract: A micromachined fluid handling device having improved properties. The valve is made of reinforced parylene. A heater heats a fluid to expand the fluid. The heater is formed on unsupported silicon nitride to reduce the power. The device can be used to form a valve or a pump. Another embodiment forms a composite silicone/parylene membrane. Another feature uses a valve seat that has concentric grooves for better sealing operation.Type: ApplicationFiled: December 22, 2000Publication date: August 30, 2001Applicant: California Institute of Technology, a California corportionInventors: Xu-Chong Tai, Xing Yang, Charles Grosjean, Xuan-Qi Wang
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Publication number: 20010015342Abstract: A method of fabricating a refractive silicon microlens by using micro-machining technology. The method of fabricating a refractive silicon microlens according to the present invention comprises the steps of forming a boron-doped region on a silicon substrate, and selectively removing regions of the substrate except for the boron-doped region to form a lens comprised of only the boron-doped region. With the method of the present invention, it is possible to fabricate a two-dimensional infrared silicon microlens array. By using such a two-dimensional infrared silicon microlens array in an infrared sensor, the detectivity of the infrared sensor can be increased by 3.4 times, which is the refraction index of silicon. In addition, the two-dimensional infrared silicon microlens array of the present invention can be used with commercial infrared telecommunication devices.Type: ApplicationFiled: December 29, 2000Publication date: August 23, 2001Applicant: Korea Advanced Institute of Science and TechnologyInventors: Choon Sup Lee, Chul Hi Han
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Patent number: 6274505Abstract: By locally heating or cooling a substrate in an etching process, temperature unevenness is controlled, and convection currents of an etching liquid are restricted simultaneously. By setting the etching temperature low in an initial stage of the etching process and increasing it in a final stage, uniform and quick etching is possible. In a drop etching method, generation of bubbles can be prevented to ensure uniform etching by providing gas release openings in a member opposed to the substrate.Type: GrantFiled: September 1, 1999Date of Patent: August 14, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Shoko Ito, Mokuji Kageyama