Substrate Contains Silicon Or Silicon Compound Patents (Class 216/99)
  • Patent number: 5417800
    Abstract: A process for manufacturing a thin film circuit board includes forming an insulator layer having a relatively high etching rate in a desired thickness on an insulator layer having a relatively low etching rate and a relatively high dielectric constant, arranging a conductor layer on the insulator layer having a relatively high etching rate, selectively removing the insulator having a relatively high etching rate by etching but excluding a portion located beneath the conductor layer, forming an insulator portion that contains the insulator layer having a relatively high etching rate and supports the conductor layer in the undercut state, forming an insulator layer having a relatively low dielectric constant so as to surround the entire conductor layer, and forming an insulator layer having a relatively high dielectric constant on top of the insulator layer having a relatively low dielectric constant so as to surround the entire insulator layer having a relatively low dielectric constant.
    Type: Grant
    Filed: June 23, 1994
    Date of Patent: May 23, 1995
    Assignee: Fujitsu Limited
    Inventor: Shuji Takeshita
  • Patent number: 5415730
    Abstract: Aluminized optical fiber is used for transmitting electricity, as well as transmitting lightwaves. In one example, an aluminized optical fiber (17) is bonded within a photonics package in contact with a conductor (15) that interconnects it to a photonic device (12) or electronic circuit. Power is then supplied to the package by applying it to the aluminized coating (19) of the optical fiber. This avoids the need for a separate conductor extending into the photonics package for supplying electrical power. It also may significantly simplify system design since the power supply can conveniently be included a fairly remote distance from the photonics package.The aluminized optical fiber can be bonded to a metallization in the V-groove (13) that provides electrical contact simply by applying heat and pressure. This allows the aluminized fiber to be bonded without the need for any adhesives, while assuring good electrical contact for the transmission of electrical power. According to another embodiment (FIG.
    Type: Grant
    Filed: December 14, 1993
    Date of Patent: May 16, 1995
    Assignee: AT&T Corp.
    Inventors: Everett J. Canning, Ranjan Dutta
  • Patent number: 5413679
    Abstract: A method of producing a silicon membrane has a step of forming an etch stop layer on an upper surface of a silicon substrate having lower and upper opposing surfaces, the etch stop layer comprising an alloy of silicon and at least one other Group IV element. The method of producing a silicon membrane has another step of forming a cap layer on the etch stop layer, the cap layer having lower and upper opposing surfaces with the lower surface contacting the etch stop layer. The method of producing a silicon membrane has a further step of removing a portion of the silicon substrate at a time when the upper surface of the cap layer is exposed, the portion of the silicon substrate being removed extending from the upper surface of the silicon substrate to the lower surface of the silicon substrate to thereby define an exposed portion of the etch stop layer. The exposed portion of the etch stop layer may be removed.
    Type: Grant
    Filed: June 30, 1993
    Date of Patent: May 9, 1995
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: David J. Godbey
  • Patent number: 5413953
    Abstract: An improved process for fabricating a planar field oxide structure on a silicon substrate was achieved. The process involves forming the field oxide by using the LOCal Oxidation of Silicon (LOCOS) process in which the device area is protected from oxidation by a silicon nitride layer. A sacrificial implant layer, such as CVD oxide, oxynitride or an anti-reflective coating (ARC) layer is used to fill in the gap between the silicon nitride and the field oxide structure and make more planar the substrate surface. The substrate surface is then implanted with As.sup.75 or p.sup.31 ions penetrating the sacrificial implant layer and forming a implant damaged layer on the field oxide. The implant damaged layer which etches faster in a wet etch in removed selectively thereby making a more planar field oxide structure. The method does not require a recess to be etched in the silicon substrate and therefore, has certain reliability and cost advantages.
    Type: Grant
    Filed: September 30, 1994
    Date of Patent: May 9, 1995
    Assignee: United Microelectronics Corporation
    Inventors: Sun-Chieh Chien, Ming-Hua Liu
  • Patent number: 5413672
    Abstract: An etching method for etching a sendust film formed on a substrate is disclosed. In this method, a mixture of acid solutions of nitric acid and hydrochloric acid is used as an etching liquid. The etching is desirably effected while the sendust film is directly or indirectly held in electrical connection with a ferrite member, with an area of a portion of the ferrite member which contacts the etching liquid being twice to twelve times a total area of etched portions of the sendust film. Also disclosed is a method for pattern-etching a sendust film, and a chromium base film formed between the sendust film and a substrate, which includes the steps of: (a) etching the sendust film to form a predetermined sendust pattern; and (b) etching the chromium base film to form a chromium pattern which conforms to the predetermined sendust pattern, such that the chromium base film is directly or indirectly held in electrical connection with a chromium bulk.
    Type: Grant
    Filed: July 14, 1993
    Date of Patent: May 9, 1995
    Assignee: NGK Insulators, Ltd.
    Inventors: Eigo Hirotsuji, Naoya Fukuda