With Measuring, Testing, Indicating, Inspecting, Or Illuminating Patents (Class 228/103)
  • Publication number: 20030136813
    Abstract: A system for testing a collection of device chips by temporarily attaching them to a carrier having a plurality of receptacles with microdendritic features; the receptacles matching with and pushed in contact with a matching set of contact pads on the device chips; said carrier additionally having test pads connected to the receptacles through interconnect wiring. The system allows connecting the chips together and testing the collection as a whole by probing the test pads on the carrier. Burn-in of the collection of chips can also be performed on the temporary carrier, which is reusable.
    Type: Application
    Filed: January 18, 2002
    Publication date: July 24, 2003
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Harold Magerlein, Samuel Roy McKnight, Kevin Shawn Petrarca, Sampath Purushothaman, Carlos Juan Sambucetti, Joseph J. Van Horn, Richard Paul Volant, George Frederick Walker
  • Patent number: 6584670
    Abstract: The present invention relates to a workpiece implementation device that fabricates individual workpieces, positions them at their point of use on a component, and connects the workpieces to the components. The device further comprises an accessory assembly capable of shaping the workpieces, coating the workpieces with a solderable material, burnishing the point of use on the component, and testing the connection between the workpieces and the component. The positioning, attaching, and accessory assemblies of the workpiece implementation device are adapted to selectively perform their individual functions without the necessity of first repositioning the component or the implementation device. Accordingly, the present invention increases overall production efficiency by integrating several separate implementation tools and workstations into a single, adaptable device.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: July 1, 2003
    Inventor: Larry J. Costa
  • Patent number: 6581817
    Abstract: A die bonding device for installing electronic components S on a metal stem, comprising a bonding nozzle for suctioning an electronic component S and positioning the electronic component S on a component mounting face of the stem, a stem carrying head for carrying the stem, a heater section for heating the electronic component S while it is positioned on the component mounting face of the stem, and an imaging camera having a light axis L extending through the component mounting face of the stem when positioned inside the heater section, which performs reciprocating motion in the direction of the light axis L.
    Type: Grant
    Filed: January 23, 2002
    Date of Patent: June 24, 2003
    Assignee: Nidec Tosok Corporation
    Inventors: Yoshiyuki Kawashima, Hiroshi Nitta, Masanori Izumi
  • Patent number: 6583386
    Abstract: The present invention provides a weld monitoring system and method that monitors and automatically coordinates information on the quality of each weld in a workpiece having one or more welds. In particular, each weld in the workpiece is automatically analyzed at the time it is being made using weld sensors such as those that measure current, wire feed, voltage, and gas flow to produce information on the quality of the weld. Using this information, the welds are sorted, displayed, and logged with workpiece and weld number information which is provided to the operator in real-time and stored in a computer for access at a later time for quality control or other purposes. Therefore, the system and method enables welds of a quality less than a pre-determined quality for the weld to be identified in real-time and information concerning any particular weld to be accessed at a later time.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: June 24, 2003
    Assignee: Impact Engineering, Inc.
    Inventor: Stephen P. Ivkovich
  • Publication number: 20030098331
    Abstract: A method for welding synthetic resin members includes the steps of detecting a temperature of a high frequency electrode or an ultrasonic horn (or an anvil) by a temperature detector, cooling the high frequency electrode or the ultrasonic horn (or the anvil) by cooling means when the temperature detected by the temperature detector during a high frequency or ultrasonic vibration exceeds a preset temperature range, thereby reducing the temperature rapidly down to the preset temperature range, and stopping an operation of the cooling means when the temperature of the high frequency electrode or the ultrasonic horn (or the anvil) is reduced to the preset temperature range.
    Type: Application
    Filed: November 20, 2002
    Publication date: May 29, 2003
    Applicant: YKK CORPORATION
    Inventors: Yoshifumi Nakata, Osamu Igarashi, Michio Ito
  • Patent number: 6568581
    Abstract: A device for monitoring a wire bonding process measures an electric signal applied to a bond wire during the bonding process, and generates an output which discriminates between successful and unsuccessful bonding. The device employs at least one variable parameter. The value of the variable parameter is determined beforehand in a learning process by monitoring examples of actual wire bonding operations. Thus, the detection method may adapt to changing requirements automatically and operate under optimal conditions for a large variety of circuits to be processed. The electric signal is preferably oscillating, and the measurement preferably includes its peak or RMS amplitude.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: May 27, 2003
    Assignee: ASM Technology Singapore Pte. Ltd.
    Inventors: Michael Armin Boller, Baskaran Annamalai, Keng Yew Song
  • Patent number: 6564987
    Abstract: A method of evaluating configuration of solder external terminals of a BGA-type tape-based semiconductor device mounted on a board such that the external terminals are joined to lands provided on the mounting board is provided. The method includes the step of obtaining geometric data related to opening of a tape substrate of the semiconductor device, solder balls to be placed at positions corresponding to the openings, and the lands of the mounting board and the step of deribing configuration of the solder external terminal based on the geometric date. The method further includes the step of calculating the volume of voids to be produced in the external terminals, so as to compensate for the geometric data related to the tape substrate.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: May 20, 2003
    Assignee: Fujitsu Limited
    Inventors: Kanako Imai, Nobutaka Ito, Fumihiko Ando
  • Patent number: 6564991
    Abstract: A work conveying path is provided in the longitudinal direction of a work on which balls are to be mounted. A ball supply tray for supplying balls and a mount head are disposed so that their longitudinal directions substantially coincide with the longitudinal direction of the work. Further, a ball inspection unit for inspecting balls sucked on the mount head is disposed so that the projecting direction of inspection light from the ball inspection unit intersects the aforementioned longitudinal directions substantially perpendicularly.
    Type: Grant
    Filed: August 1, 2000
    Date of Patent: May 20, 2003
    Assignee: Shibuya Kogyo Co., Ltd.
    Inventor: Satoshi Kinoshita
  • Patent number: 6564986
    Abstract: A method and assembly for testing multiple IC packages for solder joint fractures that occur in response to thermal cycling. A test PCB is fabricated with contact pads arranged to match a BGA IC package footprint, wherein pairs of the contact pads are linked by conductive traces (lines) to form a lower portion of a daisy chain. The BGA IC package is modified to link associated pairs of solder balls, e.g., using wire bonding to form an upper portion of the daisy chain. Mounting the BGA IC package on the test PCB completes the daisy chain. By alternating between the test PCB contact pads that are linked by conductive traces and the solder balls that are linked by wire bonding, the daisy chain provides a conductive path that passes through all solder balls of the BGA IC package.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: May 20, 2003
    Assignee: Xilinx, Inc.
    Inventor: Steven H. C. Hsieh
  • Publication number: 20030085255
    Abstract: Method of testing wire-bond connections between a bonding wire and a substrate surface, which are produced by a bonding head with a bonding tool and a wire clamp associated with the bonding tool, under pressure and the action of ultrasound and/or heat, wherein after the bonded connection has been created, the bonding head or the bonding tool is raised a short distance away from the bonding site, the bonding wire is firmly gripped by the wire clamp, and the bonding head or the wire clamp with bonding wire gripped therein is raised for a second distance, during which process the tensile force acting on the bonding wire is detected.
    Type: Application
    Filed: March 1, 2002
    Publication date: May 8, 2003
    Inventor: Farhad Farassat
  • Patent number: 6550663
    Abstract: The present invention describes the precise metering of soldering material realized in a preferred desktop preferably portable device designated for hand-soldering in small and medium volume operations. It combines the fully automated process of precise metering of the soldering wire for high accuracy and quality soldering with the freedom of a hand-operated soldering process.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: April 22, 2003
    Inventor: Leonid Poletaev
  • Patent number: 6543668
    Abstract: A mounting method and a mounting apparatus of an electronic part onto a substrate are provided, which enable inspection of a bond formed between an electronic part and a substrate when flip-chip bonding is executed by an ultrasonic wave and thermocompression bonding connecting method. The semiconductor chip has bumps which, when are compressed and subjected to ultrasonic vibration, enable formation of a connection between the semiconductor chip and a substrate conductor.
    Type: Grant
    Filed: April 7, 1999
    Date of Patent: April 8, 2003
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Tomonori Fujii, Kazutaka Suzuki
  • Publication number: 20030062397
    Abstract: The present invention provides a high-precision method for evaluating creep damage of high tension heat resistant steel used in high temperature exposing apparatuses comprising comparing particle size behavior varying with creep damage progress of crystal grains having a crystal orientation difference of about 2 degrees or more, preferably 3 degrees or more at an evaluated part on the basis of a working curve or a working map prepared in advance by looking for the relation of grain sizes to creep damage extents, and also provides a high-precision apparatus for evaluating creep damage of high tension heat resistant steel used in high temperature exposing apparatuses comprising a measuring means for measuring particle size variation behavior of crystal grains or sub grains having a crystal orientation difference of about 2 degrees or more with regard to a specimen at the evaluated part of high tension heat resistant steel and a working curve or a working map prepared in advance by looking for the relation of th
    Type: Application
    Filed: September 27, 2002
    Publication date: April 3, 2003
    Inventors: Nobuyoshi Komai, Fujimitsu Masuyama, Masahiro Kobayashi
  • Patent number: 6536649
    Abstract: Residue contaminates semiconductor devices during processing in a furnace. Residue contamination is prevented by removing the residue before it builds up to a point where it can contaminate semiconductor devices. Residue build-up is monitored using a residue build-up monitoring device mounted on the furnace exhaust stack. When residue build-up reaches a predetermined level a signal is generated by the residue build-up monitoring device notifying technicians that furnace cleaning is required.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: March 25, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Raj N. Master, Jonathan D. Halderman
  • Publication number: 20030042289
    Abstract: A method for assembling and testing an electronic circuit baseboard includes at least a step of soldering at least one electronic part to an electronic circuit baseboard using Pb excluded solder. One of erroneous wiring, erroneous mounting, malfunction, and defective soldering of the least one electronic part is tested by contacting a probe pin to various probe pin contact sections on the electronic circuit baseboard. During the step of soldering, the Pb excluded solder is also supplied to at least one of the various probe pin contact sections in order to suppress oxidation thereof.
    Type: Application
    Filed: September 6, 2002
    Publication date: March 6, 2003
    Inventors: Takashi Negishi, Katsuhiko Mukai, Hiromitsu Nakagawa
  • Patent number: 6527159
    Abstract: Surface mount technology may be utilized to join two surfaces together that may include relative surface irregularities. By varying the volume of surface mount material applied to electrically and physically join the two surfaces, surface-to-surface irregularities may be compensated for. Various techniques may be utilized to vary the volume of the interconnection material in a high speed fashion.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: March 4, 2003
    Assignee: Intel Corporation
    Inventors: Dennis L. Matthies, Ponnusamy Palanisamy
  • Publication number: 20030019910
    Abstract: A system and method for aligning optical fibers that takes into account variations due to temperature changes and other nonrandom systemic effects. The system includes an alignment tool having a plurality of internal reflection surfaces and located below a vision plane of the first one of the pair of optical fibers, and an optical detector to receive an indirect image of a bottom surface of the first optical fiber through the alignment tool, such an offset between the first optical fiber and the optical detector is determined based on the indirect image received by the optical detector. The method comprises the steps of providing a cornercube offset tool having a plurality of total internal reflection surfaces below a vision plane of the first optical fiber, and receiving an indirect image of the first optical fiber through the cornercube offset tool.
    Type: Application
    Filed: April 25, 2002
    Publication date: January 30, 2003
    Inventors: David T. Beatson, Deepak Sood, Ashoke Banerlee
  • Publication number: 20030010807
    Abstract: Surface mount technology may be utilized to join two surfaces together that may include relative surface irregularities. By varying the volume of surface mount material applied to electrically and physically join the two surfaces, surface-to-surface irregularities may be compensated for. Various techniques may be utilized to vary the volume of the interconnection material in a high speed fashion.
    Type: Application
    Filed: July 12, 2001
    Publication date: January 16, 2003
    Inventors: Dennis L. Matthies, Ponnusamy Palanisamy
  • Publication number: 20030000995
    Abstract: The present invention solves a problem that in a wire bonding process, an inert gas used for prevention of oxidation of a substrate gave rise to shimmer due to the temperature difference during bonding, thereby degrading the precision of pattern recognition. With this invention's bonding device 21 provided with recognition device, a shimmer prevention blow mechanism 31 is disposed between a ring illumination 25 and a working hole 24 and near working hole 24. Though the nitrogen gas that blows out from working hole 24 gives rise to shimmer due to temperature difference, this shimmer can be blown away by the nitrogen gas blow from shimmer prevention blow mechanism 31. As a result, the recognition precision of a recognition camera can be improved and the wire bonding precision of the &mgr;m order can be improved.
    Type: Application
    Filed: June 24, 2002
    Publication date: January 2, 2003
    Inventors: Kouji Seki, Noriyasu Sakai, Toshihiko Higashino
  • Publication number: 20030000993
    Abstract: The present invention solves a problem that in a wire bonding process, an inert gas used for prevention of oxidation of a substrate gave rise to shimmer due to the temperature difference during bonding, thereby degrading the precision of pattern recognition. With this invention's bonding device 21, shielding lids 31, 32, and 33 are disposed at upper and lower parts of a ring illumination 25 and at a lower part of lens barrel 29. Shimmer 37 of nitrogen gas that blows out from a working hole 24 can thus be prevented from entering inside ring illumination 25, especially by shielding lid 31 at the lower part of ring illumination 25. As a result, the recognition precision of a recognition camera can be improved and the wire bonding precision of the &mgr;m order can be improved.
    Type: Application
    Filed: June 24, 2002
    Publication date: January 2, 2003
    Inventors: Kouji Seki, Noriyasu Sakai, Toshihiko Higashino
  • Publication number: 20020190098
    Abstract: To offer a semiconductor light-emitting device capable of preventing a short circuit failure caused by adhesion of the solder, change of a beam shape, and decrease of a beam output.
    Type: Application
    Filed: August 14, 2002
    Publication date: December 19, 2002
    Inventor: Masafumi Ozawa
  • Publication number: 20020190097
    Abstract: The present invention (FIG. 1) relates to a new method for brazing a connecting piece of electrically conducting material, for example of metal, to a metal surface by means of a new type of temperature-controlled brazing whereby for certain types of material, for example steel, a martensite-free brazing is obtained, i.e. a brazing without deleterious structural changes (martensite formation). A brazing is obtained that is completely free of martensite underneath the brazed joint in for example railway track and/or pipework. The invention also relates to an arrangement for carrying out the said method.
    Type: Application
    Filed: May 15, 2002
    Publication date: December 19, 2002
    Inventor: Ola Pettersen
  • Patent number: 6491205
    Abstract: Chips requiring high temperature reflow for attachment to a module substrate are attached first and then a eutectic water soluble solder paste and/or water soluble flux is dispensed on both the TSOP and the PBGA chip pads instead of using the paste screening techniques. The dispensing is done by injecting solder on the solder sites individually. Characteristics of the solder paste used is that it must be fluid enough to be injected onto the individual sites yet have enough body that it remains in place and does not run from site to site once dispensed. A paste capable of providing such characteristics is one having: a ) a very fine particle size in the range of 400 to 500 mesh and preferably between 400 and 450 mesh; b) a low viscosity (below 500 k centerpoise and preferably between 425 to 375 cps); and c) a solid content of 86% or lower and preferably between 84 and 80%.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: December 10, 2002
    Assignee: International Business Machines Corporation
    Inventors: Chon C. Lei, Jac A. Burke, William F. Beausoleil, N. James Tomassetti, Lawrence A. Thomas, Tak-kwong Ng, Michael Kessler
  • Patent number: 6492828
    Abstract: The present invention provides schemes which are associated with wire bonding process or wire bonding machine to detect the bonding status of a bonding wire of a package including at least a semiconductor unit. The schemes are very useful to a BGA (Ball Grid Array) package or similar types of packages, and provide significant advantages particularly for a package in which the resistance (such as the resistance resulting from an adhesion layer and a layer of Cupric Oxide for promoting adhesion) between a semiconductor unit and its carrier is not low enough.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: December 10, 2002
    Assignee: Siliconware Precision Industries
    Inventors: Lee Ming-Hsun, Chen Chin-Te
  • Publication number: 20020179679
    Abstract: A three-dimensional soldering inspection apparatus and method. The three-dimensional soldering inspection apparatus includes a lighting module provided with a plurality of light emitting devices, a photographing unit installed at a portion of the lighting module to photograph a subject placed inside the lighting module, an image processing unit to capture each frame image from an image photographed by the photographing unit, a storage unit to store data of each frame image, a control unit to extract three-dimensional features from each frame image and restore the extracted features as a three-dimensional image, and a display unit to display the three-dimensional image under the control of the control unit.
    Type: Application
    Filed: May 3, 2002
    Publication date: December 5, 2002
    Inventors: Chang-Hyo Kim, Tae-Sun Choi
  • Patent number: 6484924
    Abstract: The present invention provides a backing device for backing up weld joints formed by friction stir welding workpieces having curvilinear geometries. The backing device includes a backing ring defining a contact zone. At least a portion of the contact zone defined by the backing ring engages the weld joint opposite the friction stir welding tool to thereby support the weld joint and to constrain the plasticized material within the weld joint. The backing device includes a restraining member in operable communication with the backing ring to urge the contact zone of the backing ring toward the weld joint. The backing device includes a sensor for measuring the magnitude of force exerted by the contact zone of the backing ring upon the weld joint.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: November 26, 2002
    Assignee: The Boeing Company
    Inventor: R. Scott Forrest
  • Publication number: 20020170945
    Abstract: A solder ball attachment system for manufacturing an integrated circuit or the like is disclosed. The solder ball attachment system includes a flux station adapted to apply flux onto a substrate and a solder ball placement station adapted to place solder balls onto the flux. A conveyor assembly is included to move the substrate between the flux station and the solder ball placement station.
    Type: Application
    Filed: May 17, 2001
    Publication date: November 21, 2002
    Applicant: Intel Corporation
    Inventor: Shafarin Shafie
  • Publication number: 20020166885
    Abstract: So as to perform high-precision position detection without performing pattern matching in the direction of rotation even when the object of detection involves a positional deviation in the direction of rotation, pattern matching between a reference image and a rotated image obtained by rotating this reference image is performed during registration, and then the difference between the measured value of the position obtained following rotation and the theoretical value of the position of the rotated image is retained as a calibration amount corresponding to the known angle of rotation. Upon detection, the measured value is detected by pattern matching between an image of the object of detection, which is detected by imaging the object of detection disposed in an attitude that includes a positional deviation in the direction of rotation, and a reference image; and this measured value is corrected by the calibration amount.
    Type: Application
    Filed: April 18, 2002
    Publication date: November 14, 2002
    Applicant: KABUSHIKI KAISHA SHINKAWA
    Inventor: Kenji Sugawara
  • Patent number: 6474537
    Abstract: Members to be soldered, such as printed circuit boards having electronic parts mounted thereon, are subjected to flow soldering in a solder bath with a Cu-containing lead-free solder. When the molten solder in the solder bath falls below a prescribed level, the molten solder is replenished with a material having a lower Cu content than the initial composition of the solder bath. Flow soldering can be continued for long periods with the Cu content of the solder bath being maintained substantially constant.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: November 5, 2002
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Seiichiro Hasegawa, Eietsu Hasegawa
  • Patent number: 6474531
    Abstract: To offer a semiconductor light-emitting device capable of preventing a short circuit failure caused by adhesion of the solder, change of a beam shape, and decrease of a beam output. A semiconductor laser device 1 is manufactured by overlaying a laser tip having a p-side electrode and a n-side electrode in a crystalline substrate and a mounting plate having a first solder film and a second solder film in a supporting body. The laser tip has a level difference A such that the p-side electrode is projected beyond the n-side electrode. The mounting plate has a level difference B such that the first solder film is projected beyond the second solder film. The level difference B of the mounting plate is determined as higher than the level difference A of the laser tip. Therefore, when the mounting plate is overlaid to the laser tip, first, the n-side electrode contacts with the second solder film, and then, the p-side electrode contacts the first solder film.
    Type: Grant
    Filed: December 5, 2000
    Date of Patent: November 5, 2002
    Assignee: Sony Corporation
    Inventor: Masafumi Ozawa
  • Patent number: 6467678
    Abstract: A wire bonding method and apparatus, in which after the tail of a wire extends out of a capillary, the capillary moves to a measurement position above a tail length measuring member; the capillary descends so that the end of the tail contacts the tail length measuring member; a position of the capillary or a distance by which the capillary is lowered at the time that electrical continuity is established with the tail length measuring member is detected; and the tail length is calculated based upon a height level of the tail length measuring member, the position of the capillary before being lowered for measuring the tail, and the position of the capillary when the wire contacts the tail length measuring member, or upon the height of the capillary above the tail length measuring member before lowering the capillary for measuring the tail, and a distance the capillary is lowered.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: October 22, 2002
    Assignee: Kabushiki Kaisha Shinkawa
    Inventors: Tooru Mochida, Tatsunari Mii, Nobuaki Hirai
  • Patent number: 6467672
    Abstract: A wire-bonding machine includes a heat block for supporting a lead frame during wire-bonding. A clamp mechanism in the machine clamps leads of the lead frame during wire-bonding by fixedly holding sets of the leads against the heat block one set at a time. A wire-bonding tool wire-bonds leads clamped by the clamp mechanism to bond pads on an integrated circuit die. By clamping leads of the lead frame in separate sets, the machine provides improved clamping for lead frames with leads requiring clamping in different planes.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: October 22, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Michael B. Ball, Rich Fogal
  • Publication number: 20020134816
    Abstract: A method for designing a weld fixture. The method includes modeling a set of distortions produced by applied mechanical forces on a material to be welded, modeling a set of distortions produced by applied thermal forces on the material to be welded, determining a set of reaction forces at a series of locations on a simulated weld fixture as a function of the modeled distortions, and designing a weld fixture as a function of the set of reaction forces.
    Type: Application
    Filed: May 9, 2001
    Publication date: September 26, 2002
    Inventors: Xiao Chen, Yi Dong, Edward T. Martin, Zhishang Yang, Wayne Tanner
  • Publication number: 20020130158
    Abstract: A device for monitoring a wire bonding process measures an electric signal applied to a bond wire during the bonding process, and generates an output which discriminates between successful and unsuccessful bonding. The device employs at least one variable parameter. The value of the variable parameter is determined beforehand in a learning process by monitoring examples of actual wire bonding operations. Thus, the detection method may adapt to changing requirements automatically and operate under optimal conditions for a large variety of circuits to be processed. The electric signal is preferably oscillating, and the measurement preferably includes its peak or RMS amplitude.
    Type: Application
    Filed: March 15, 2001
    Publication date: September 19, 2002
    Inventors: Michael Armin Boller, Baskaran Annamalai, Keng Yew Song
  • Patent number: 6446856
    Abstract: A method of welding a hollow member and an insert member to form a composite member including a hollow member and insertion member requiring a high dimensional accuracy in the end-to-end distance in the axial direction and requiring a reliable concentricity in the center axes of the hollow member and insertion member, including preparing a hollow member and insertion member, inserting the insertion member in the hollow member, providing spot welds at an overlap portion where the hollow member and insertion member overlap to correct the axial end-to-end distance of the hollow member and the insertion member, and providing a partial weld at an overlap portion where the hollow member and insertion member overlap to correct the concentricity of the hollow member and the insertion member.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: September 10, 2002
    Assignee: Denso Corporation
    Inventors: Hideaki Shirai, Takafumi Sato, Eiji Iwanari, Yoshinori Ohmi
  • Patent number: 6443351
    Abstract: A BGA (Ball Grid Array) package fabrication method is proposed for the purpose of achieving solder ball coplanarity on a warped BGA package, such as a concavely-warped BGA package or a convexly-warped BGA package. The proposed method is characterized in the provision of a plurality of variably-sized solder-ball pads over the bottom surface of the substrate, each solder-ball pad having a specified size predetermined in accordance with pre-measured package warpage and predetermined relation of solder ball height against pad size. This provision allows the use of a solder mask having fixed-size openings, as contrary to the prior art that uses a solder mask having variably-sized openings, to allow the implanted solder balls to achieve coplanarity and have strengthened shear for robust solder joint.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: September 3, 2002
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien Ping Huang, Tzong Da Ho
  • Patent number: 6435398
    Abstract: A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads covered by deposited layers of a barrier metal and a bondable metal. After identifying the wafers with off-spec metal layers, the wafers are chemically etched using selective etchants consecutively until the metal layers over the bond pads are removed without damaging the copper metallization. Replacement metal layers are finally deposited over the bond pads. Specifically, the bondable metal, such as gold, is selectively removed by a cyclic dithio-oxamine compound, dissolved in tetra-hydro-furane or acetone. The barrier metals, such as nickel and palladium, are removed by a mixture of inorganic and organic oxidizing acids.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: August 20, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Cheryl Hartfield, Thomas M. Moore
  • Publication number: 20020104871
    Abstract: A plurality of pinhole disks are superposed, fixed in position with the pinholes brought into alignment with the aid of a wire, a pin or light, and bonded or welded together to form a pinhole disk laminate. The laminate has an untapered deep enough center through-hole and is suitable as an order sorting aperture (OSA) in hard x-ray microscopy using a FZP.
    Type: Application
    Filed: January 18, 2002
    Publication date: August 8, 2002
    Applicant: Japan Synchrotron Radiation Research Institute
    Inventors: Mitsuhiro Awaji, Nagao Kamijo, Shigeharu Tamura, Masato Yasumoto
  • Publication number: 20020104872
    Abstract: A method and apparatus for protecting the stored information on an integrated circuit from being compromised through reverse engineering. To do so, the method and apparatus splits the functionality of an integrated circuit into two separate integrated circuits, which are then connected in an interlocking manner. A detection circuit monitors the interconnection of the two separate integrated circuits. Upon detection of a break in the interconnection of the two circuits, the detection circuit destroys the data stored in the two separate integrated circuits. The two integrated circuits are connected in a flip-chip fashion, thereby preventing access to the underlying conduction paths and charge storage sites which are normally used in reverse engineering an integrated circuit.
    Type: Application
    Filed: April 10, 2002
    Publication date: August 8, 2002
    Inventors: Richard Alden DeFelice, Paul A. Sullivan
  • Patent number: 6427899
    Abstract: A machine and method for bonding puncture-type conductive contact members of an interconnect to the bond pads of a bare semiconductor die includes the use of one or two ultrasonic vibrators mounted to vibrate one or both of the die and interconnect. A short axial linear burst of ultrasonic energy enables the contact members to pierce hard oxide layers on the surfaces of the bond pads at a much lower compressive force and rapidly achieve full penetration depth.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: August 6, 2002
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, Michael E. Hess, John O. Jacobson, Warren M. Farnworth, Alan G. Wood
  • Patent number: 6425515
    Abstract: A method for attaching an electronic device to and removing an electronic device from a substrate includes verifying a position of a pick-up and vacuum head relative to the electronic device prior to contacting the electronic device with the pick-up and vacuum head; contacting the electronic device with a device for conductively applying heat to the electronic device and picking up the electronic device; and heating solder for attaching the electronic device to the substrate to a reflow temperature of the solder by applying heat to the device for conductively applying heat.
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: July 30, 2002
    Assignee: International Business Machines Corporation
    Inventors: Allen Thomas Mays, Kris Allan Slesinger, Michael Camillo Weller
  • Publication number: 20020096553
    Abstract: A wire dereeler for an ultrasonic wire bonder with a bond head has a support for rotatably supporting a reel of wire driven by a stepper motor in incremental steps. Two rollers receive the wire therebetween and are driven by a motor drive for rotating or torquing the rollers and tensioning the wire placed between the rollers. A linkage generally aligns the rollers in parallel with the wire therebetween. A photoelectric sensor determines a given amount of wire at a position between the bond head and the rollers and provides a signal for controlling the stepper motor driving the reel of wire.
    Type: Application
    Filed: January 19, 2001
    Publication date: July 25, 2002
    Inventor: Theodore J. Copperthite
  • Patent number: 6419143
    Abstract: A machine and method for bonding puncture-type conductive contact members of an interconnect to the bond pads of a bare semiconductor die includes the use of one or two ultrasonic vibrators mounted to vibrate one or both of the die and interconnect. A short axial linear burst of ultrasonic energy enables the contact members to pierce hard oxide layers on the surfaces of the bond pads at a much lower compressive force and rapidly achieve full penetration depth.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: July 16, 2002
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, Michael E. Hess, John O. Jacobson, Warren M. Farnworth, Alan G. Wood
  • Publication number: 20020084310
    Abstract: In heat bonding method and device, first and second marks (MA, MB) formed on the film carrier (52) are measured before performing heat bonding of outer leads (54) formed on a film carrier (52) to electrodes (58) formed on a transparent plate (56), where an expansion amount of the film carrier (52) is changed according to a condition of the heat bonding. A distance between the measured marks (MA, MB) is then obtained. The condition for the heat bonding is determined based on this distance. The heat bonding is performed under this condition determined.
    Type: Application
    Filed: December 20, 2001
    Publication date: July 4, 2002
    Applicant: SHIBAURA MECHATRONICS CORPORATION
    Inventor: Takehiko Miyamoto
  • Patent number: 6412683
    Abstract: A vision system and method for use with a bonding tool that takes into account variations due to temperature changes and other nonrandom systemic effects. The vision system includes a cornercube offset tool having a plurality of total internal reflection surfaces, the cornercube offset tool located below the vision plane of the optical system; and an optical detector to receive an indirect image of the bonding tool through the cornercube offset tool. The method comprises the steps of providing a cornercube offset tool having a plurality of total internal reflection surfaces below a vision plane of the bonding tool; and receiving an indirect image of the bonding tool through the cornercube offset tool.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: July 2, 2002
    Assignee: Kulicke & Soffa Investments, Inc.
    Inventors: David T. Beatson, Christian Hoffman, James E. Eder, John Ditri
  • Publication number: 20020079350
    Abstract: A bonding apparatus is constituted by a bonding tool, a substrate stage, a moving mechanism for moving the bonding tool and the substrate stage, an up-and-down mechanism for moving up and down said bonding tool, and a chip recognition camera. The bonding apparatus is configured so that a chip and a substrate are subjected to positioning on the basis of a recognition result of the chip recognition camera so that the chip is bonded onto the substrate. The chip recognition camera is disposed to be lower than a level of a substrate mounted surface of the substrate stage. A lower surface of the chip is recognized in a condition that the lower surface of the chip is located to be substantially on a level with a chip bonding surface of the substrate. Positioning of the chip and the substrate is performed by the recognition image.
    Type: Application
    Filed: December 17, 2001
    Publication date: June 27, 2002
    Applicant: SHIBUYA KOGYO CO., LTD
    Inventors: Touru Terada, Yasuhisa Matsumoto
  • Patent number: 6398102
    Abstract: A method for providing an analytical solution for a thermal history of a welding process having multiple weld passes. The method includes the steps of inputting a plurality of files and parameters, preprocessing information from the plurality of files and parameters to determine a set of conditions associated with the welding process, determining a region of influence of at least one heat source used in the welding process as a function of the set of conditions, determining a plurality of point heat source solutions within the region of influence, determining a temperature solution for each weld pass as a function of a superposition of the plurality of point heat source solutions, and determining the thermal history of the welding process as a function of the temperature solutions.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: June 4, 2002
    Assignee: Caterpillar Inc.
    Inventors: Zhenning Cao, Jinmiao Zhang, Frederick W. Brust, Ashok Nanjundan, Yi Dong
  • Patent number: 6386430
    Abstract: In a system and method for adjusting a height of a base of a clamp to fit to strips of a plurality of IC (integrated circuit) package sizes, the clamp is comprised of a fixed clamp portion and the base having a height that is adjustable with respect to the fixed clamp portion. A bar is disposed over the base of the clamp along a length of the base of the clamp, and the bar is fixed with respect to the fixed clamp portion. Each of a plurality of dummy strips of IC packages corresponds to a respective IC package size. A respective dummy strip of IC packages corresponding to a respective IC package size is placed on the base of the clamp to be supported by the base of the clamp. In addition, a plurality of height adjustment jigs are disposed on the bar to slide along the bar. Each of the height adjustment jigs has a respective size corresponding to a strip of a respective IC package size.
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: May 14, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Wanus Prommate, Narong Bokkaew, Grid Kachane
  • Patent number: 6382497
    Abstract: The present invention provides an apparatus and a method for operating reflow soldering in a mounting field whereby an abnormality in transfer of circuit boards can be detected with high reliability. Whether or not a circuit board is transferred by a transfer conveyor is judged. A discharge conveyor is started when a control device judges occurrence of transfer abnormality. After the discharge conveyor starts, the transfer abnormality is determined to be a drop of the circuit board if a discharge completion detector detects that a dropped circuit board is discharged. And then the control device continues the reflow soldering. The transfer abnormality in the reflow soldering apparatus can be detected with high reliability because it can be detected whether the transfer abnormality is either the drop or a clog of the circuit board.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: May 7, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Nobuyasu Nagafuku, Akihiko Wachi, Masaya Matsumoto, Toshiyuki Koyama
  • Patent number: 6371355
    Abstract: The present invention is a method for solder joint integrity assessment. The invention comprises collecting data from one or more solder joint strain tests and characterizing the solder joint data integrity using a force-deflection graph. A force-deflection graph characterizes the response force of a solder joint to applied strain as a function of time. One embodiment of the invention uses the slope of the graph to characterize the integrity of the solder joint. Another embodiment uses the area below the graph to characterize the integrity of the solder joint. To generate the force-deflection graph, the invention applies one or more tests to the solder joint. In one embodiment, a shear test is applied to the solder joint. In another embodiment, a cold pull test is applied to the solder joint. In another embodiment, a hot pull test is applied to the solder joint.
    Type: Grant
    Filed: August 25, 2000
    Date of Patent: April 16, 2002
    Assignee: Sun Microsystems, Inc.
    Inventor: Keith G. Newman