Component Terminal To Substrate Surface (i.e., Nonpenetrating Terminal) Patents (Class 228/180.21)
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Patent number: 7316062Abstract: Methods and apparatus are provided for removing plating from a device. The method and apparatus may be used for preparing an electrical connector for connecting at least one wire or other terminus thereto where the electrical connector has at least one electrical contact with a metal coating thereon. The method includes the steps of applying molten solder to the electrical contact whereby the coating dissolves into the molten solder to thereby create a molten coating-solder mixture and rotating the electrical connector whereby the molten coating-solder mixture is removed from the electrical contact.Type: GrantFiled: May 27, 2004Date of Patent: January 8, 2008Assignee: Honeywell International Inc.Inventor: James L. Chilcote
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Patent number: 7288742Abstract: According to a method and a device for heating a strip-shaped carrier in an oven, a carrier is passed through the oven in a direction of conveyance. The carrier is supported by a heatable plate, which together with the carrier is moved through the oven stepwise with a predetermined step size from a starting position to an end position.Type: GrantFiled: September 13, 2006Date of Patent: October 30, 2007Assignee: Assembleon N.V.Inventors: Wessel Joris Wesseling, Franciscus Johannes Sonnemans, Dionys Van De Ven
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Patent number: 7271497Abstract: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.Type: GrantFiled: March 10, 2003Date of Patent: September 18, 2007Assignee: Fairchild Semiconductor CorporationInventors: Rajeev Joshi, Consuelo Tangpuz, Margie T. Rios, Erwin Victor R. Cruz
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Patent number: 7263769Abstract: A multi-layered flexible print circuit board comprising an insulating layer, a circuit layer formed on the front and back surfaces of the insulating layer and a hole connecting between the circuit layers via the insulating layer, wherein there is provided an electrically-conductive member having a metal layer formed thereon at least on the surface thereof which is press-fitted into the hole to electrically conduct the circuit layer.Type: GrantFiled: October 19, 2005Date of Patent: September 4, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shinji Morimoto, Kouji Nakashima, Toyokazu Yoshino, Katsuya Okamoto
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Patent number: 7260890Abstract: The present invention includes methods for making liquid crystalline polymer (LCP) interconnect structures using a high temperature and low temperature single sided liquid crystalline polymer LCP where both the high and low temperature LCP are drilled to form a z-axis connection. The single sided conductive layer is a bus layer to form z axis conductive stud within the high and low temperature LCP, followed by a metallic capping layer of the stud that serves as the bonding metal between the conductive interconnects to form the z-axis connection. High and low temperature LCP layers are etched or built up to form circuit patterns and subsequently bonded together to form final multilayer circuit pattern where the low temperature LCP melts to form both dielectric to dielectric bond to high temperature LCP circuit layer, and dielectric to conductive bond, whereas metal to metal bonding occurs with high temperature metal capping layer bonding to conductive metal layer.Type: GrantFiled: March 28, 2003Date of Patent: August 28, 2007Assignee: Georgia Tech Research CorporationInventors: George E. White, Madhavan Swaminathan, Venkatesh Sundaram, Sidharth Dalmia
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Patent number: 7257887Abstract: A die holding apparatus to form electrical contacts on individual dies is described. In one embodiment, a semiconductor device holder is used to hold individual dies for processing and reprocessing. The semiconductor device holder holds each individual die in a separate processing cavity configured to hold each individual die in a predetermined processing position. In one embodiment, a vacuum force is used to hold one or more dies in respective processing cavities with a predetermined level of force even if other adjacent die processing cavities are unoccupied by other individual dies.Type: GrantFiled: June 14, 2004Date of Patent: August 21, 2007Inventor: David Lee
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Patent number: 7258264Abstract: Methods of manufacturing optical transceiver modules using lead frame connectors that connect optical sub-assemblies to printed circuit boards are disclosed. The lead frame connector includes an electrically insulating case having a first part separated from a second part and a plurality of conductors that are electrically isolated one from another by the electrically insulating case. Each of the plurality of conductors can form an electrical contact restrained in a fixed position with respect to the first part and a contact point extending from the second part. The electrical contact is aligned with and soldered to the leads that protrude from the back end of an optical sub-assembly. The contact points can then be connected to electrical pads on a PCB.Type: GrantFiled: February 25, 2005Date of Patent: August 21, 2007Assignee: Finisar CorporationInventors: Donald A. Ice, Darin James Douma
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Patent number: 7251880Abstract: A method and apparatus are provided for determining whether solder used during assembly of a printed circuit board is lead-free or not. This may include providing a pad on the printed circuit board and placing solder on the pad in a predetermined pattern. The solder may be heated so as to create reflow. The solder may later be examined to determine if the solder is lead-free.Type: GrantFiled: September 28, 2001Date of Patent: August 7, 2007Assignee: Intel CorporationInventors: Tom E. Pearson, George Arrigotti, Christopher D. Combs, Raiyomand F. Aspandiar
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Patent number: 7249411Abstract: Methods for mounting electrical components on a substrate and securely retaining the components are described. The methods include altering solder paste compositions, interposed between component retentive pins and retentive through holes, during a reflow process. Electronic assemblies including circuit boards and electrical components mounted thereto are also described. In one of the electronic assembly embodiments, materials originally associated with a mounted electrical component migrate into solder paste coupling the electrical component to the circuit board.Type: GrantFiled: July 6, 2004Date of Patent: July 31, 2007Assignee: FCI Americas Technology, Inc.Inventor: Yakov Belopolsky
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Patent number: 7237331Abstract: Provided is a method of manufacturing an electronic part having a plurality of wiring patterns and an insulating layer interposed between the wiring patterns and serving to establish electrical connection between the wiring patterns through an interlayer connecting portion penetrating the insulating layer. In the method, a first step of forming a wiring pattern and a columnar conductor and a second step of forming a layer having a uniform thickness by bonding an insulating sheet from above and pressing the insulating sheet to the height of the columnar conductor with the columnar conductor as a stopper so as to conform the thickness of the insulating sheet to the height of the columnar conductor are repeated.Type: GrantFiled: December 17, 2003Date of Patent: July 3, 2007Assignee: TDK CorporationInventors: Masashi Gotoh, Kaoru Kawasaki, Mutsuko Nakano, Hiroshi Yamamoto
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Patent number: 7216792Abstract: An article of manufacture including an organic structure and inorganic atoms bonded to specific locations on the organic structure.Type: GrantFiled: September 9, 2003Date of Patent: May 15, 2007Assignee: International Business Machines CorporationInventors: Ravi F. Saraf, Hemantha K. Wickramesinghe
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Patent number: 7205177Abstract: A method of bonding two elements such as wafers used in microelectronics applications is disclosed. One inventive aspect relates to a method for bonding comprising producing on a first main surface of a first element a first solder ball, producing on a first main surface of a second element a second solder ball, providing contact between the first solder ball and the second solder ball, bonding the first element and the second element by applying a reflow act whereby the solder balls melt and form a joined solder ball structure. Prior to the bonding, the first solder ball is laterally embedded in a nonconductive material, such that the upper part of the first solder ball is not covered by the non-conductive material. Devices related to such methods are also disclosed.Type: GrantFiled: June 30, 2005Date of Patent: April 17, 2007Assignee: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Walter De Raedt, Steven Brebels, Steven Sanders, Tom Torfs, Eric Beyne
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Patent number: 7199329Abstract: A semiconductor part 1 in which a metal terminal 2 is formed on its back surface and side surface is mounted so that only the back surface portion of the metal terminal 2 is in contact with a cream solder 3. When the side surface portion of the metal terminal 2 is irradiated with laser beams, the back surface portion of the metal terminal 2 is heated by thermal conduction from the side surface portion to the back surface portion of the metal terminal 2 and the cream solder 3 in contact with the back surface portion of the metal terminal 2 is melted, whereby soldering is performed.Type: GrantFiled: August 10, 2004Date of Patent: April 3, 2007Assignee: Niigata Seimitsu Co., Ltd.Inventors: Akihiro Mano, Yukihiro Ueno, Hironori Urasawa, Yuki Oishi, Tadashi Miyazaki
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Patent number: 7197819Abstract: A method of assembling and providing an electric power apparatus. The method uses a heat resistant housing having a structure adapted to accommodate and retain a power circuit card and also including a bracket adapted to accommodate and constrain a rigid conductive member. A power circuit card having an electrical terminal is placed into the housing and a rigid conductive member into the bracket. The rigid conductive member is flow soldered to the electrical terminal, thereby exposing the heat resistant housing to heat and creating a solder bond. Finally, the rigid conductive member is affirmatively connected to the housing. The bracket constrains the rigid conductive member so that the act of affirmatively connecting does not weaken the solder bond.Type: GrantFiled: December 18, 2004Date of Patent: April 3, 2007Assignee: Rinehart Motion Systems, LLCInventors: Lawrence E. Rinehart, Guillermo L. Romero
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Patent number: 7191515Abstract: An electrical assembly (200, FIG. 2) is formed from two, interconnected circuit boards (202, 204). Conductive spacers (240) and a conductive material (260) are placed between complementary bond pads (218, 232) on the circuit boards. The conductive spacers are formed from a material that maintains its mechanical integrity during the process of attaching the circuit boards. The conductive material is a solder or conductive adhesive used to mechanically attach the circuit boards. In addition, an insulating material (270) is inserted into an interface region (250) between the circuit boards. The insulating material provides additional mechanical connection between the circuit boards. In one embodiment, one circuit board (202) includes a glass panel that holds an array of organic light emitting diodes (OLEDs), and the other circuit board (204) is a ceramic circuit board. Together, the interconnected circuit board assembly (200) forms a portion of a flat panel display (1102, FIG. 11).Type: GrantFiled: July 28, 2003Date of Patent: March 20, 2007Assignee: Intel CorporationInventors: Robert C. Sundahl, Kenneth Wong
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Patent number: 7191516Abstract: A high reliability radiation shielding integrated circuit device comprising a plurality of package layers; a radiation shielding lid or base coupled to the plurality of package layers; wherein the circuit die are shielded from receiving an amount of radiation greater than the total dose tolerance of the circuit die. An integrated circuit device for use in high reliability applications. The integrated circuit device is designed to be highly reliable and protect integrated circuit die from failing or becoming unreliable due to radiation, mechanical forces, thermal exposure, or chemical contaminates.Type: GrantFiled: July 16, 2003Date of Patent: March 20, 2007Assignee: Maxwell Technologies, Inc.Inventor: Janet Patterson
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Patent number: 7185420Abstract: An apparatus is provided for thermally coupling a heat dissipation device to a microelectronic device. A thermal compression bonding apparatus is provided comprising a bonding head adapted to apply heat and pressure to the heat dissipation device to provide the desired thermal profile to effect solidification of the interface material from the center outward.Type: GrantFiled: June 7, 2002Date of Patent: March 6, 2007Assignee: Intel CorporationInventor: Steve M. Mayer
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Patent number: 7186926Abstract: A surface mounting structure for a surface mounting electronic component includes an electronic component, a circuit board and a solder fillet. The electronic component has on a marginal portion thereof a plurality of electrodes, each of which is formed so as to cover at least an under surface, both side faces and an end face of the electronic component. The circuit board has a set of lands, on which the electrodes of the electronic component are joined by soldering. Each land corresponds to one of the electrodes and has a restricting portion, which restricts movement of the electronic component at the time of solder melting during surface mounting, and also has a protrusion on each side of the corresponding electrode. The solder fillet is formed at least on each protrusion so as to correspond to both side faces of the corresponding electrode.Type: GrantFiled: February 11, 2005Date of Patent: March 6, 2007Assignee: Kabushiki Kaisha Toyota JidoshokkiInventor: Kazuhiro Maeno
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Patent number: 7182241Abstract: Aspects of the invention provide solder compositions which include two different fluxing agents. One of the fluxing agents promotes melting of a metal of the solder at a first activation temperature and the other fluxing agent promotes melting of the metal at a second activation temperature that is higher than the first activation temperature. This dual-flux solder may be used in manufacturing microelectronic components and microelectronic component assemblies. In one specific application, the solder may be used to manufacture a flip chip or other microelectronic component which includes self-fluxing solder balls. This can obviate the need to apply another flux composition to the solder balls prior to a subsequent component attach reflow operation.Type: GrantFiled: August 9, 2002Date of Patent: February 27, 2007Assignee: Micron Technology, Inc.Inventors: Tsuyoshi Yamashita, Tongbi Jiang
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Patent number: 7174627Abstract: A known good die is economically fabricated. A tested integrated circuit is provided which includes a die having a bonding location on an upper surface and a lead. An upper portion of the integrated circuit package is removed or ground away to expose the bonding location. The lead is removed leaving the die and exposed bonding location to provide a known good die. The backside portion of the integrated circuit package is removed or ground away to expose the backside of the die. A contact pad is disposed on the bonding location. The bonding wire and exterior lead are also removed or ground away. The upper portion of the bonding ball is removed to provide a flattened bonding location. Preferably, the tested integrated circuit package provided is a thin small outline integrated circuit package (TSOP), and advantageously may be a packaged flash memory integrated circuit.Type: GrantFiled: January 9, 2003Date of Patent: February 13, 2007Assignee: Irvine Sensors CorporationInventor: Keith D. Gann
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Patent number: 7159754Abstract: The invention relates to a method for soldering an object comprising several soldered joints. The method comprises the steps of mechanically soldering of at least some of the soldered joints, visually assessing the soldered joints, and correctively soldering the visually assessed soldered joints that do not meet the relevant quality requirements. The visual assessment takes place by means of a video camera and a computing device connected to the video camera. The assessment criteria for the soldered joints are stored in the computing device. The invention also relates to an apparatus for carrying out the method.Type: GrantFiled: January 26, 2004Date of Patent: January 9, 2007Assignee: Vitronics Soltec B.V.Inventors: Johannes Coleta Maria Van Den Broek, Lambertus Petrus Christinus Willemen, Gerardus Johannes Adrianus Maria Diepstraten
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Patent number: 7153765Abstract: A nano-sized solder suspension flows by selective wetting onto a bond pad and away from a bond-pad resist area. A microelectronic package is also disclosed that uses the nano-sized solder suspension. A method of assembling a microelectronic package is also disclosed. A computing system is also disclosed that includes a bump that was reflowed from the nano-sized solder suspension.Type: GrantFiled: March 31, 2005Date of Patent: December 26, 2006Assignee: Intel CorporationInventors: Daoqiang Lu, Tian-An Chen
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Patent number: 7150096Abstract: A method for applying pressure to circuit components during a manufacturing operation. The method utilizes a plurality of compressed air pressure cylinders which are supported on a plurality of horizontal arms along different axes over a circuit board. Compressed air is supplied simultaneously to each of the cylinders, and the cylinders force the component onto a bonding position on the circuit board. The method permits heat sinks to be pressed against components located on the circuit board to bond the heat sinks to the components.Type: GrantFiled: July 19, 2000Date of Patent: December 19, 2006Assignee: International Business Machines Corp.Inventors: James Westcott Heater, Allen Thomas Mays, John Gillette Davis
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Patent number: 7128979Abstract: A circuit board including conductive layers bonded to both surfaces of an insulating ceramic substrate, with a brazing material disposed therebetween. The conductive layers comprise at least 99.98% by mass of aluminum, and display an average crystal grain diameter within a range from 0.5 mm to 5 mm and a standard deviation ? for that crystal grain diameter of no more than 2 mm. Each conductive layer comprises at least 20 ppm of Cu, Fe and Si. The surface area of the crystal with the maximum crystal grain diameter within the conductive layers accounts for no more than 15% of the surface area of the insulating ceramic substrate.Type: GrantFiled: April 21, 2003Date of Patent: October 31, 2006Assignee: Mitsubishi Materials CorporationInventors: Toshiyuki Nagase, Yoshiyuki Nagatomo
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Patent number: 7093746Abstract: A stencil used for printing solder paste on a contact pad of a printed wiring board has interior surfaces that define one or more apertures through the stencil. Those interior surfaces are coated with a material, such as parylene, having a lower surface tension than the interior surfaces absent the coating. The stencil can also have one or more reverse-tapered apertures passing there through, wherein the apertures have a variable cross-section that is larger at the fill side of the stencil (i.e., where solder paste enters the apertures) than at the board side of the stencil (i.e., where the stencil contacts the contact pad of the printed wiring board). Solder paste can be printed through the aperture(s) of the stencil onto contact pads on a printed wiring board.Type: GrantFiled: July 26, 2004Date of Patent: August 22, 2006Assignee: Fry's Metals, Inc.Inventors: Ian McPhee Fleck, Ron Tripp, Prashant Chouta, Scott Craig
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Patent number: 7071033Abstract: A semiconductor device including a leadframe and two stacked dies, a first of which is on a top surface of a leadframe while the second one is on a bottom surface of the leadframe. The drain region of the first die is coupled to a drain clip assembly that includes a drain clip that is in contact with a lead rail. The body of the semiconductor device includes a window or opening that exposes the drain region of the second die.Type: GrantFiled: July 8, 2004Date of Patent: July 4, 2006Assignee: Fairchild Semiconductor CorporationInventor: Maria Cristina B. Estacio
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Patent number: 7036217Abstract: According to a method of mounting electronic components on a printed circuit board (PCB), the electrical contacts of the components are coupled to PCB bonding pads that are intersected by via pads. To minimize various defects encountered during solder reflow, while concurrently minimizing PCB area and manufacturing costs, the via pads are formed so that the via holes substantially avoid underlying the solder fillets coupling the component contacts to the PCB bonding pads. In one embodiment, the via pads are formed in the inter-pad space beneath the component; in another embodiment they are offset from the bonding pads. A substrate, an electronic assembly, and an electronic system are also described.Type: GrantFiled: January 21, 2003Date of Patent: May 2, 2006Assignee: Intel CorporationInventors: Tom E. Pearson, Carolyn R. McCormick, Jayne L. Mershon
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Patent number: 7032306Abstract: The invention concerns a method for producing electronic modules with ball connector (7) or integrated preforms capable of being soldered on a printed circuit (3) and a device for implementing said method. The invention concerns a method for producing electronic modules in the form of ball housings combining a ball grid array (7) or geometrically identical preforms for interconnecting or shielding and surface-mounted components (2) on the same surface of a substrate (1), thereby enabling said module to be directly connectable by soldering on a printed circuit (3). The balls (7) and the components (2) are transferred in one single step onto the substrate (1) by means of a gripping device adapted to the topography of the module to be produced.Type: GrantFiled: January 6, 2000Date of Patent: April 25, 2006Assignee: Societe Novatec S.A.Inventor: Francis Bourrieres
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Patent number: 7024764Abstract: A method of making an electronic package. The method includes forming a semiconductor chip and an multi-layered interconnect structure. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The formed multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The method forms the electronic package to further include a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation.Type: GrantFiled: January 7, 2002Date of Patent: April 11, 2006Assignee: International Business Machines CorporationInventors: John S. Kresge, Robert D. Sebesta, David B. Stone, James R. Wilcox
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Patent number: 7013557Abstract: A method of packaging an electronic component having electrodes soldered on lands on a printed circuit board uses a mask pattern that corresponds to the lands onto which solder paste is deposited. Solder paste is printed on the lands using the mask which has a convex shape such that the edges of the solder paste lie inside the edges of the lands. The electrodes are then placed on the solder paste, and the solder paste is caused to reflow to solder the electrodes to the lands.Type: GrantFiled: May 30, 2002Date of Patent: March 21, 2006Assignee: NEC CorporationInventors: Hiroshi Sakai, Motoji Suzuki, Makoto Igarashi, Akihiro Tanaka
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Patent number: 7013564Abstract: A method of producing an electronic device by connecting a lead of a semiconductor device with an electrode of a circuit board to form a bonded structure. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.Type: GrantFiled: October 9, 2001Date of Patent: March 21, 2006Assignee: Hitachi, Ltd.Inventors: Hanae Shimokawa, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
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Patent number: 7007378Abstract: A process for manufacturing a land grid array connector for a printed wiring board is disclosed. The process does not require electroplating precious metal overlays. Therefore, no commoning bar is required. Another benefit of the invention includes a connector design using only a flash, soft gold application in the outer surface of the connector. Physical hardness and durability are derived from a thin palladium layer lying beneath the flash gold layer.Type: GrantFiled: December 12, 2002Date of Patent: March 7, 2006Assignee: International Business Machines CorporationInventors: John G. Gaudiello, James D. Herard, John J. Konrad, Jeffrey McKeveny, Timothy L. Wells
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Patent number: 6996899Abstract: Solder bumps are created on a substrate of an electronic assembly having lengths that are longer than the widths. The solder bumps are created by locating solder balls of power or ground connections close to one another so that, upon reflow, the solder balls combine. Signal solder balls however remain separated. Capacitors are created by locating power solder bumps adjacent ground solder bumps and extending parallel to one another.Type: GrantFiled: March 25, 2003Date of Patent: February 14, 2006Assignee: Intel CorporationInventors: Damion T. Searls, Terrance J. Dishongh, James D. Jackson
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Patent number: 6991151Abstract: To reduce the capacitance of an electronic module having an active component (1) bonded to a base (2), thereby enabling its cutoff frequency to be raised, the method provides a plurality of contact pads (P1, P?1, P2, P3, P?3) and a plurality of contact zones (Z1, Z?1, Z2, Z3, Z?3) on the component and on the base respectively. First structures (P1, P?1, Z1, Z?1) are adapted to be bonded together by melting solder. Second structures (P2, Z2) of small surface area are designed to be bonded together by thermal compression delivered by the mutual force of attraction that results between the component and the base due to the solder melting. The invention is particularly applicable to making optoelectronic components used in high data rate optical transmission systems.Type: GrantFiled: November 14, 2003Date of Patent: January 31, 2006Assignee: AlcatelInventor: Louis Giraudet
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Patent number: 6988652Abstract: A stencil used for printing solder paste on a contact pad of a printed wiring board has one or more reverse-tapered apertures passing there through, wherein the apertures have a variable cross-section that is larger at the fill side of the stencil (i.e., where solder paste enters the apertures) than at the board side of the stencil (i.e., where the stencil contacts the contact pad of the printed wiring board).Type: GrantFiled: May 29, 2002Date of Patent: January 24, 2006Assignee: Fry's Metals, Inc.Inventors: Ian McPhee Fleck, Ron Tripp, Prashant Chouta, Scott Craig
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Method of reforming reformable members of an electronic package and the resultant electronic package
Patent number: 6978542Abstract: An electronic package includes a substrate having a contact pad thereon, a reformable member such as a solder ball positioned on the contact pad, and an elastic member positioned around the reformable member. The elastic member exerts a girdling force on the reformable member so that when the reformable member is softened, the elastic member elongates the reformable member. This elongation accommodates thermal and other stresses between the foregoing substrate and another substrate joined at the free end of the reformable member. An apparatus is also provided for positioning the elastic member on and around the reformable member.Type: GrantFiled: March 28, 2003Date of Patent: December 27, 2005Assignee: International Business Machines CorporationInventor: David J. Alcoe -
Patent number: 6978539Abstract: A method for attaching an IC package to a circuit board, the IC package having a plurality of electrical contacts in an arrangement having a perimeter, first positions the IC package adjacent to the circuit board. Then, electrically connects the IC package to the circuit board through the plurality of electrical contacts. The method finally, disposes at least one anchor mechanically attaching the IC package to the circuit board, the anchor disposed at a location outside of the perimeter of the plurality of electrical contacts. The type, quantity, and exact geometry of the anchors depend on the specific design parameters of the IC package and circuit board.Type: GrantFiled: July 17, 2002Date of Patent: December 27, 2005Assignee: Compal Electronics, Inc.Inventors: Shao-Tsu Kung, Chen-Hua Liu
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Patent number: 6973717Abstract: A semiconductor device in chip format having a chip which has at least one first insulating layer and electrical connection pads free of the insulating layer is described. On the first insulating layer, interconnects run from the electrical connection pads to base regions of external connection elements. A further applied insulating layer is provided with openings leading from the outside to the base regions of the external connection elements. In the openings there is a conductive adhesive, onto which small balls which are metallic at least on the outside are placed. The semiconductor element can also contain a solder paste instead of a conductive adhesive in the openings, and metallized small plastic balls are placed onto the solder paste. The invention furthermore relates to methods for producing the semiconductor device described.Type: GrantFiled: September 9, 2004Date of Patent: December 13, 2005Assignee: Infineon Technologies AGInventors: Hans-Jürgen Hacke, Klaus-Peter Galuschki
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Patent number: 6959489Abstract: A method of making a microelectronic package includes providing a substrate having a plurality of conductive leads at a first surface of the substrate. The conductive leads may have first ends permanently attached to the substrate and second ends remote from the terminal ends, the second ends being movable relative to the first ends of the leads. One or more microelectronic elements having contact bearing surfaces and back surfaces remote therefrom may be juxtaposed with the substrate and the contacts connected with the first ends of the leads. A substantially rigid plate may be attached to the back surfaces of the microelectronic elements. The substantially rigid plate may be moved to a precise height above the substrate to vertically extend the leads. While the plate is maintained at the precise height above the substrate, a spacer material is dispensed between the plate and the substrate. The spacer material is then at least partially cured for holding the plate at the precise height above the substrate.Type: GrantFiled: September 19, 2001Date of Patent: November 1, 2005Assignee: Tessera, Inc.Inventors: Masud Beroz, Michael Warner
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Patent number: 6945447Abstract: A chip or die attachment process and related apparatus, in which a desired quantity of solder (7 or 17) is dispensed onto each, in turn, of a number of desired locations on a substrate (4 or 18), and then an integrated-circuit chip (10) is precisely positioned at each location immediately after the solder is dispensed at that location. Hot gas heaters are used both to heat the solder (7 or 17) as it is dispensed onto the substrate (4 or 18), and to heat the integrated-circuit chip (10) and to reflow the solder beneath the chip. In one form of the invention, the solder is dispensed from a wire spool (1) and melted in position on the substrate (4). Alternatively, the solder is dispensed as a drop (16) from a liquid solder reservoir (13).Type: GrantFiled: June 5, 2002Date of Patent: September 20, 2005Assignee: Northrop Grumman CorporationInventors: Dean Tran, Salim Akbany, Maurice Lowery, Leon M. Singleton, Jr., Ronald A. DePace
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Patent number: 6936793Abstract: A solder reflow oven with horizontal cyclonic convection air flow for enhancing equalized heating of printed circuit boards conveyed therethrough. Air circulation apparatus can include a first air movement fan for urging air to move horizontally laterally from the first side wall of the oven toward the second side wall of the oven across and above printed circuit boards being conveyed therethrough. A second air fan is positioned below and laterally displaced from the conveying means for directing a second air stream below the first air stream and oppositely oriented in order to urge movement of heated air across the undersurface of the conveyor for enhancing equalization of heating of the printed circuits boards thereupon. Preferably, both blowers are oriented to move air approximately perpendicularly with respect to the direction of movement of the conveyed printed circuit boards in opposite respective directions thereabove and therebelow.Type: GrantFiled: April 17, 2002Date of Patent: August 30, 2005Assignee: Novastar Technologiesm Inc.Inventors: Adam Shiloh, Peretz J. Shiloh, Avraham Shiloh, Viktor Kapiliovich
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Patent number: 6928727Abstract: A method and apparatus for manufacturing an electrical connection unit and connector array is provided. Such arrays may be used to solder together traces from opposed circuit boards, in which the array is fitted between, and soldered to the boards to complete a circuit. The method of manufacturing a connection unit includes providing a first insulative base with one or more contacts or contact groups extending from the first side towards the second side of the base. Solder portions or solder balls may be reflowed to contacts at their termination points. An apparatus and method may provide a solder positioning device or means on top of or adjacent to the first insulative base, so that solder portions or solder balls are placed within cavities in the positioning device, in alignment with apertures of the first insulative base. The connection unit may be heated to reflow and fuse the solder portions to the contact termination, thereby constructing an array.Type: GrantFiled: July 30, 2002Date of Patent: August 16, 2005Assignee: AVX CorporationInventors: John J. Ashman, Monroe Waymer, Jennifer Hammond
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Patent number: 6927346Abstract: Apparatus and methods for interconnecting a SMT component interconnect to a via-in-pad (VIP) interconnect. A first reflowable material is deposited on the VIP bond pad. A sphere having a higher melt temperature than the reflow temperature of the first interconnect material is deposited on the first interconnect material. A first reflow process is performed to interconnect the sphere and the VIP bond pad while the sphere remains solid, and the first reflowable material preventing the first interconnect material from migrating into the via-in-pad.Type: GrantFiled: December 20, 2002Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Carolyn R. McCormick, Terrance J. Dishongh
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Patent number: 6911624Abstract: An apparatus and method for attaching a flip chip configured semiconductor die to a substrate as well as removing the die and replacing it on the substrate with another flip chip-configured semiconductor die by way of an electrically resistive thermal supply circuit that provides heat to soften or melt an electrical connection material of discrete conductive elements connecting the two components, as well as providing heat to release a dielectric underfill material, if present. Methods for designing a thermal supply circuit and are also disclosed. Semiconductor die and substrate configurations incorporating thermal supply circuits as well as thermal supply circuit configurations and design approaches are also disclosed.Type: GrantFiled: August 23, 2002Date of Patent: June 28, 2005Assignee: Micron Technology, Inc.Inventor: Michel Koopmans
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Patent number: 6902098Abstract: A device including a first solder pad and a second solder pad comprised of a post-soldering alloy composition on a substrate is provided. The alloy composition comprises two or more elements, and the post soldering alloy composition of the first solder pad has different amounts of the two or more elements than the alloy composition of the second solder pad. A method of making a solder pad comprises masking a substrate comprising at least a first solder pad and a second solder pad, wherein the mask exposes a greater area of the first solder pad so that the deposited element becomes part of an alloy composition of the first solder pad upon soldering thereby changing the melting point of the first solder pad.Type: GrantFiled: April 19, 2002Date of Patent: June 7, 2005Assignee: Shipley Company, L.L.C.Inventor: Mindaugas F. Dautartas
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Patent number: 6902101Abstract: In a bump bonding technique for forming a bump on an IC, including forming a ball at the tip of a gold wire protruding from a capillary, and providing a metal-to-metal joint by applying ultrasonic vibration from a ultrasonic head through the capillary while pressing the ball against a pad portion on the IC, the metal-to-metal joint is provided by applying the ultrasonic vibration at a frequency in a range of 130 to 320 kHz, more preferably in a range of 170 to 270 kHz, and most preferably at a frequency of 230±10 kHz at room temperatures and atmospheric pressure. Consequently, a bump is formed on an IC having a low heat resistance temperature in a satisfactory joint condition, and a bump is formed with good positional accuracy without giving the influence of heat to the surroundings.Type: GrantFiled: November 15, 2002Date of Patent: June 7, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Satoshi Horie, Takahiro Yonezawa, Hiroyuki Kiyomura, Tetsuya Tokunaga, Tatsuo Sasaoka
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Patent number: 6871396Abstract: A transfer material capable of transferring a fine wiring pattern to a substrate reliably and easily. The transfer material includes at least three layers of a first metal layer as a carrier, a second metal layer that is transferred to the substrate as a wiring pattern, and a peel layer adhering the first and second metal layers releasably. On the surface portion of the first metal layer, a concave and convex portion corresponding to the wiring pattern is formed, and the peel layer and the second metal layer are formed on a region of the convex portions.Type: GrantFiled: February 7, 2001Date of Patent: March 29, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuhiro Sugaya, Shingo Komatsu, Koichi Hirano, Seiichi Nakatani, Yasuyuki Matsuoka, Toshiyuki Asahi, Yoshihisa Yamashita
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Patent number: 6851598Abstract: An electronic component with at least one semiconductor chip and a wiring layer are described. The wiring layer has elastic contact elements of low mechanical strength in the spatial directions x, y and z, which can be electrically connected to corresponding contact terminal areas of a printed circuit board. The semiconductor chip or the wiring layer additionally has at least two spacers for the mechanical connection to a printed circuit board. A method for producing the electronic component is also described.Type: GrantFiled: July 25, 2002Date of Patent: February 8, 2005Assignee: Infineon Technologies AGInventors: Uta Gebauer, Harry Hedler, Jürgen Högerl, Volker Strutz
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Patent number: 6848173Abstract: A method of making a microelectronic assembly includes juxtaposing a first element, such as a dielectric sheet having conductive leads thereon with a second element, such as a semiconductor chip, having contact thereon, and wire bonding the conductive leads on the first element to the contacts on the second element so that elongated bonding wires extend between the conductive leads and the contacts. After the wire bonding step, the first and second elements are moved through a pre-selected displacement relative to one another so as to deform the bonding wires. A flowable dielectric material may be introduced between the first and second elements and around the bonding wires during or after the moving step. The flowable material may be cured to form an encapsulant around at least a portion of the bonding wires.Type: GrantFiled: January 22, 2001Date of Patent: February 1, 2005Assignee: Tessera, Inc.Inventors: Joseph Fjelstad, Masud Beroz, John W. Smith, Belgacem Haba
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Patent number: 6839961Abstract: Methods and apparatuses for bonding solder balls to bond pads are described. In one embodiment, portions of a plurality of solder balls are placed within a frame and in registered alignment with individual bond pads over a substrate. While the ball portions are within the frame, the balls are exposed to bonding conditions effective to bond the balls with their associated bond pads. In another embodiment, a frame is provided having a plurality of holes sized to receive individual solder balls. Individual balls are delivered into the holes from over the frame. The balls are placed into registered alignment with a plurality of individual bond pads over a substrate while the balls are in the holes. The balls are bonded with the individual associated bond pads.Type: GrantFiled: October 9, 2001Date of Patent: January 11, 2005Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Alan G. Wood