Component Terminal To Substrate Surface (i.e., Nonpenetrating Terminal) Patents (Class 228/180.21)
  • Publication number: 20040262370
    Abstract: Disclosed are high reliability solder joints and methods for manufacturing the same. Methods are disclosed forming a solder joint (26) in an electronic assembly (10) having one or more copper connection sites (16) including steps for applying a nickel layer (22) with a carefully controlled thickness to the copper connection site (16), and applying a diffusion layer (24) to the thin nickel layer (22). Further steps are disclosed for positioning lead-free solder (18) adjacent to the diffusion layer (24), and for reflowing the solder (18) to form a highly reliable solder joint (26). Also disclosed is a solder joint (26) for use in a semiconductor apparatus (10) having at least one copper connection site (16). The solder joint (26) includes a thin intermetallic compound layer (28) bonded to the copper connection site (16) and lead-free solder (18) encapsulating the thin intermetallic compound layer (28).
    Type: Application
    Filed: November 12, 2003
    Publication date: December 30, 2004
    Inventor: Kazuaki Ano
  • Patent number: 6830177
    Abstract: The present invention comprises cost-effectively manufactured, electrically conductive and mechanically compliant micro-leads and a method of utilizing these compliant micro-leads to interconnect area grid array chip scale packages (“CSPs”) to printed wiring boards (“PWBs”). The preferred method includes orienting a plurality of conductive compliant micro-leads, secured to one another in parallel with tie bars and tooling, to align with a corresponding pattern of conductive pads located along the surface of an area grid array CSP. The compliant micro-leads are electrically connected and mechanically secured to the corresponding connecting surfaces of the area grid array CSP. Next, the securing tie bars and the tooling are removed. The opposite ends of the conductive compliant micro-leads are then oriented to align with a corresponding pattern of conductive surface pads on a PWB.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: December 14, 2004
    Assignee: General Dynamics Information Systems, Inc.
    Inventor: Deepak K. Pai
  • Patent number: 6827252
    Abstract: A method of forming bumps on the active surface of a silicon wafer. An under-ball metallic layer is formed over the active surface of the wafer. A plurality of first solder blocks is attached to the upper surface of the under-ball metallic layer. Each first solder block has an upper surface and a lower surface. The lower surface of each first solder block bonds with the under-ball metallic layer. The upper surfaces of the first solder blocks are planarized. A second solder block is attached to the upper surface of each first solder block and then a reflow operation is carried out.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: December 7, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee
  • Patent number: 6820798
    Abstract: The aim of the invention is to simplify and improve the production method for circuit arrangements that are mounted on a support element (5), said element having thermal through-platings (7) which are at least partially scaled by a screen printing process. To this end, the screen printing process is carried out after the application of a first metallization layer (6) to the support element (5) which forms the base metallization layer, whereby the residue of the screen printing material (8) remaining on the underside (13) of the support element (5) is stripped once the screen printing material (8) has been cured, using at least a mechanical cleaning process and/or a chemical cleaning process.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: November 23, 2004
    Assignee: Conti Temic microelectronic GmbH
    Inventors: Helmut Heinz, Bernhard Schuch
  • Publication number: 20040222272
    Abstract: There is provided a mask for use in printing solder on a plurality of terminals formed on a substrate so as to correspond to a plurality of terminals of an IC package. The mask has openings through which the solder is applied, and the openings are larger than the terminals. Although a wiring line adjacent to the terminals may be covered with the solder, a reflow process causes the solder to be divided into a first portion and a second portion, thus preventing short-circuits between the wiring line and the terminals.
    Type: Application
    Filed: September 19, 2003
    Publication date: November 11, 2004
    Inventor: Takeshi Ashida
  • Publication number: 20040222271
    Abstract: A method and associated pallet assembly for reflow soldering electrical interconnections between a pair of printed circuits, at least one of which features a relatively-low-softening-temperature substrate, includes fixturing the printed circuits between the mating surfaces of a pallet and a cover, wherein the cover includes a first aperture adapted to expose an area on the back face of the first printed circuit. When the palletized printed circuits are advanced through a reflow oven, a nozzle directs hot gases through the first aperture to impinge directly upon the back face of the substrate to thereby reflow a solder layer sandwiched between the respective substrates of the printed circuits. Additional components on the second printed circuit are advantageously soldered in the same pass as hot gases from the nozzle flow through a second aperture defined in the pallet assembly's cover to impinge upon an additional solder layer on the second printed circuit.
    Type: Application
    Filed: May 6, 2003
    Publication date: November 11, 2004
    Applicant: Visteon Global Technologies, Inc.
    Inventors: Mark Tor, Peter J. Sinkunas, Lahki N. Goenka
  • Patent number: 6814274
    Abstract: When viewed in a first direction, a cross section of a pressing surface of the bonding tool for pressing the inner leads is flat and extends uniformly over a range longer than the interval between every two electrode pads. When viewed in a second direction orthogonal to the first direction, and when the inner leads are pressed to the electrode pads by virtue of a predetermined pressing force, the length of a pressing area having a pressing force acting between the inner leads and the electrode pads is shorter than the length of each electrode pad.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: November 9, 2004
    Assignee: NEC Electronics Corporation
    Inventors: Yoichiro Kurita, Teruji Inomata
  • Patent number: 6815613
    Abstract: The invention relates to an electronic component with external connection elements and to a method of electrically connecting and/or fixing an electronic component to a printed-circuit board. For this purpose, the electronic component has capillary elements as external connection elements, which are connected to contact connection areas of a leadframe or to contact areas of a chip. The capillary element protrudes out of the electronic component and has, on its protruding end, a suction opening with capillary action.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: November 9, 2004
    Assignee: Technologies AG
    Inventors: Uta Gebauer, Volker Strutz
  • Patent number: 6813153
    Abstract: A polymer solder hybrid (PSH) thermal interface material (TIM). The PSH TIM includes a solder with a low melt temperature and a filler with a high melt temperature. Upon initiation of reflow, the filler diffuses into the solder to form a new filler-solder alloy having an increased melting point and added robustness.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: November 2, 2004
    Assignee: Intel Corporation
    Inventors: Paul A. Koning, Fay Hua
  • Patent number: 6807730
    Abstract: A pad structure for a semiconductor package is provided by forming solder lands at predetermined locations on a printed circuit board. First circular pad portions are formed protruding laterally from upper surfaces of the solder lands. Second circular pad portions are formed protruding laterally from other lateral sides of the pads. The leads are secured to the pads of the semiconductor package so that, when the first and second circular pad portions are pushed laterally, the circular pad portions do not contact each other, thereby preventing short circuits.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: October 26, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Won-Dong Hwang Bo
  • Publication number: 20040206802
    Abstract: In a process of soldering an electric connector on a circuit board, the connector has an insulator and a plurality of leads mounted inside the insulator. Each lead has a first end extending into a soldering terminal to a bonding surface of the insulator. A soft solder paste is dispensed over a bonding surface of the circuit board. The soldering process inserts the soldering terminal of each lead in the soft solder paste and applies heat to the soft solder paste to bond the soldering terminal and the circuit board together. The direct insertion of the soldering terminal of the lead into the soft paste on the circuit board minimizes the contact area between the lead and the circuit board and prevents the solder paste from being unduly spread, causing short circuit. Furthermore, the yield and soldering reliability are increased and the production cost is reduced.
    Type: Application
    Filed: April 16, 2003
    Publication date: October 21, 2004
    Inventor: Ted Ju
  • Patent number: 6805277
    Abstract: In a process of soldering an electric connector on a circuit board, the connector has an insulator and a plurality of leads mounted inside the insulator. Each lead has a first end extending into a soldering terminal to a bonding surface of the insulator. A soft solder paste is dispensed over a bonding surface of the circuit board. The soldering process inserts the soldering terminal of each lead in the soft solder paste and applies heat to the soft solder paste to bond the soldering terminal and the circuit board together. The direct insertion of the soldering terminal of the lead into the soft paste on the circuit board minimizes the contact area between the lead and the circuit board and prevents the solder paste from being unduly spread, causing short circuit. Furthermore, the yield and soldering reliability are increased and the production cost is reduced.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: October 19, 2004
    Assignee: Lotes Co., Ltd.
    Inventor: Ted Ju
  • Publication number: 20040200886
    Abstract: A semiconductor device is disclosed containing a semiconductor die having a trimetal electrode soldered to a substrate by a Sn—Sb solder.
    Type: Application
    Filed: April 9, 2003
    Publication date: October 14, 2004
    Applicant: International Rectifier Corp.
    Inventor: Chuan Cheah
  • Publication number: 20040200885
    Abstract: A method for assembling semiconductor devices includes providing a first semiconductor device, securing spacers to noncircuit bond pads of the first semiconductor device, and positioning a second semiconductor device on the spacers. Adhesive material may be applied to a surface of one or both of the first and second semiconductor devices prior to positioning of the second semiconductor device, or introduced between first and second semiconductor devices. The noncircuit bond pads may be electrically isolated from other structures of the first semiconductor device or communicate with a ground or reference voltage plane, in which case the back side of the second semiconductor device may communicate with the ground or reference voltage plane upon being positioning against the spacers. Additional semiconductor devices may be added to the assembly. The first semiconductor device may be associated with a substrate. Assemblies and packages at least partially fabricated by the method are also disclosed.
    Type: Application
    Filed: April 29, 2004
    Publication date: October 14, 2004
    Inventor: James M. Derderian
  • Publication number: 20040195295
    Abstract: A titanium alloy strip has a reduced cross section in the central region of the strip. By concentrating heat in this central region the process of bonding laser devices to a substrate is greatly improved. Furthermore, the present invention allows for the possibility of removing the laser device from the substrate without destroying the laser device.
    Type: Application
    Filed: April 27, 2004
    Publication date: October 7, 2004
    Applicant: AGILENT TECHNOLOGIES, INC.
    Inventors: Maheshchandra Mistry, Christopher Main
  • Patent number: 6796481
    Abstract: A method for mounting a chip on a substrate includes applying the underfill agent onto at least one of the substrate and the chip and moving the chip to the substrate to bring the bump into contact with the electrode. The method also includes steps to distribute the underfill agent in a space between the chip and the substrate, to around the bump and the electrode, heating the bump or electrode in the state that the bump is buried in the underfill agent to melt the bump or electrode so as to weld the bump to the electrode.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: September 28, 2004
    Assignee: Toray Engineering Co., Ltd.
    Inventor: Akira Yamauchi
  • Publication number: 20040173664
    Abstract: A circuit board pallet with an improved securement pin and component positioning arms is disclosed. The improved pin of the present invention is cylindrical pin with an enlarged head. A countersunk hole is drilled in the bottom of the pallet to accommodate the pin. The pin is inserted into the countersunk hole and secured with a high-temperature epoxy resin. The epoxy holds the pin securely in place and keeps the pin from moving up or down.
    Type: Application
    Filed: March 6, 2003
    Publication date: September 9, 2004
    Inventor: James Gleason
  • Patent number: 6782616
    Abstract: The present disclosure relates to connection arrangements for electrical devices. In the connection arrangements, an electrical device having at least one ledge that includes a plurality of contact terminals provided thereon is electrically connected to an electrical component having a plurality of contacts formed thereon.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: August 31, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Kenneth J. Eldredge
  • Patent number: 6769598
    Abstract: The invention provides metal connecting composition for connecting metal to metal with removing oxide film on the mother metal surface. The metal connecting composition contains metal particles and hydrocarbon compound having C—H bonding dissociation energy of a value equal to or lower than 950 KJ/mol. When metal pieces between which the metal connecting composition is applied is heated, the hydrocarbon compound is dehydrogenated to form radical, and the radical reduces oxide film on the metal surface to be connected.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: August 3, 2004
    Assignee: Denso Corporation
    Inventors: Toshihiro Miyake, Yoshitaro Yazaki
  • Publication number: 20040142512
    Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.
    Type: Application
    Filed: January 12, 2004
    Publication date: July 22, 2004
    Applicants: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
  • Publication number: 20040134976
    Abstract: A system and method are disclosed for providing a solder joint between a pair of electrical devices which have juxtapositionable solderable portions. A solder material is provided between the solderable portions at the solder joint. A spacer material is suspended in the solder material to maintain the electrical devices spaced a predetermined distance from each other at the solder joint. The spacer material has a melting point higher than that of the solder material.
    Type: Application
    Filed: January 14, 2003
    Publication date: July 15, 2004
    Inventors: Frank Keyser, Robert Fuerst
  • Patent number: 6761304
    Abstract: A heating head for soldering and de-soldering surface mount devices (SMD's) using hot inert gas or air is comprised of a handle in which there is placed a heater sub-assembly on which there is secured a quick connect mechanism for mounting a heating nozzle. The heater sub-assembly is enclosed in a shroud and is secured to the end of the handle by a thermal insulating ring, such shroud housing a ceramic rod having elongated bosses on which a heating element is secured, while a laminar flow equilizer is used to provide more uniform gas flow across the heating element. Quick connect mechanism is secured to the heater sub-assembly shroud and uses a spring loaded winged locking mechanism to the secure heating nozzles to the heater head. In one embodiment, the heating nozzles have a truncated pyramid shaped chamber to which individual end nozzles are attached for directing gas flow.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: July 13, 2004
    Inventor: Czeslaw A. Ruszowski
  • Patent number: 6756184
    Abstract: A method of making electrically conductive bumps of improved height on a semiconductor device. The method includes steps of depositing an under bump metallurgy over a semiconductor device onto a contact pad; depositing and patterning a photoresist layer to provide an opening over the under bump metallurgy; depositing a first electrically conductive material into the opening in the photoresist layer; depositing a second electrically conductive material over the first electrically conductive material; removing the photoresist layer and the excess under bump metallurgy; applying a flux agent to the top surface of the second electrically conductive material; hard baking the semiconductor device to remove any oxide; dipping a portion of the semiconductor device in an electroless plating solution; removing the semiconductor device from the electroless plating solution; and reflowing the electrically conductive materials to provide a bump of improved height on the semiconductor device.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: June 29, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chiou-Shian Peng, Euegene Chu, Alex Fahn, Kenneth Lin, Gilbert Fane, James Chen, Kuo-Wei Lin
  • Publication number: 20040112943
    Abstract: A method of securing articles to each other and an alignment and holding apparatus comprising a platform having an alignment member for positioning and holding a first article, such as a substrate, in a first position and a further alignment member for aligning extensions of a second article, such as a lead frame, in an assembleable position with respect to the first article while a spacer maintains the extensions in proper lateral position and a clamp that secures the extensions proximate the first article while an electrical connection is formed between the first article and the extensions of the second article.
    Type: Application
    Filed: December 16, 2002
    Publication date: June 17, 2004
    Inventors: Robert James Monson, Richard L. Cellini, Roger J. Karnopp
  • Publication number: 20040108363
    Abstract: In order to reduce the capacitance of an electronic module comprising an active component (1) bonded to a base (2), thereby enabling its cutoff frequency to be raised, the method consists in providing a plurality of contact pads (P1, P′1, P2, P3, P′3) and a plurality of contact zones (Z1, Z′1, Z2, Z3, Z′3) on the component and on the base respectively. First structures (P1, P′1, Z1, Z′1) are adapted to be bonded together by melting solder. Second structures (P2, Z2) of small surface area are designed to be bonded together by thermal compression delivered by the mutual force of attraction that results between the component and the base due to the solder melting. The invention is particularly applicable to making optoelectronic components used in high data rate optical transmission systems.
    Type: Application
    Filed: November 14, 2003
    Publication date: June 10, 2004
    Applicant: ALCATEL
    Inventor: Louis Giraudet
  • Patent number: 6742248
    Abstract: A reliable, long-lived soldered electrical connection is made to a ceramic substrate having a thick-film metallization thereon, over which is deposited a joint-structure-stabilizing thin-film metallization. The thin-film metallization is a multilayered structure having an adhesion layer overlying and in contact with the thick-film metallization, a readily wettable base-metal layer overlying and in contact with the adhesion layer, and an oxidation-prevention layer overlying and in contact with the base-metal layer. An electrical conductor is soldered to the thin-film metallization of the ceramic substrate. The electrical conductor may be a bonding pad of a flip chip having a solder bump thereon.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: June 1, 2004
    Assignee: The Boeing Company
    Inventors: Boon Wong, Robert E. Silhavy, Jennifer Shinno
  • Patent number: 6735857
    Abstract: Solder paste is applied beforehand onto through-hole upper lands (or solder) of a printed circuit board and attachment is effected by inserting solder joined to the BGA-side pads into the holes of the through-hole upper lands; solder and solder paste are then melted by heating, causing them to flow into the through-holes and to wet and spread out upon the through-hole bottom face lands, thereby effecting a soldered joint with the BGA-side pads and through-hole upper lands securely attached, and forming solder fillets. In this way, the quality of the solder joints can be ascertained by an ordinary external inspection method.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: May 18, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuji Saito, Kozo Fukuzawa
  • Patent number: 6732907
    Abstract: A soldering method including: bonding a first electronic component having electrodes plated with a material containing lead to one surface of an interconnect substrate through solder containing no lead; and flow-soldering to bond a second electronic component to the other surface of the interconnect substrate. In the soldering method, a joint section between the first electronic component and the interconnect substrate is heated at the same time as or after the step of flow soldering to melt the joint section.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: May 11, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Ikuya Miyazawa
  • Publication number: 20040084508
    Abstract: A method and structure for controlling solder spread in a predefined/designed area during flip chip assembly build is disclosed. Using conventional processes used in the art blind holes or dimples are incorporated onto the lead frame which then act as containers or wells trapping the solder and thereby preventing it from spreading wider.
    Type: Application
    Filed: October 30, 2002
    Publication date: May 6, 2004
    Applicant: Advanpack Solutions Pte. Ltd.
    Inventors: John Briar, Roman Perez, Kee Kwang Lau, Alex Chew
  • Publication number: 20040079791
    Abstract: A method for manufacturing a printed circuit board includes: washing a land that corresponds to the exposed portion of a copper circuit of a printed circuit board with acidic electrolytic water having a pH of not more than 5 to remove an oxide; treating the land with basic electrolytic water having a pH of not less than 9 to prevent oxidation; and soldering electronic components to the land. The portion to be soldered is treated with the electrolytic water beforehand, thereby improving soldering at low cost without any adverse effect on the environment.
    Type: Application
    Filed: July 9, 2003
    Publication date: April 29, 2004
    Applicant: MEC COMPANY LTD.
    Inventors: Tetsuo Kida, Samuel Kenneth Liem
  • Patent number: 6723629
    Abstract: The invention discloses a method for attaching solder members (114) to a substrate (112). The method includes forming a decal (110) with a plurality of solder members (114). The method further comprises aligning the decal (110) with the substrate (112) and transferring the solder members (114) on the decal (110) to the substrate (112).
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: April 20, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory B. Hotchkiss, Gary D. Stevens
  • Patent number: 6722028
    Abstract: A method of manufacturing an electronic device including a first electronic component mounted on one main surface of a wiring board by being thermo-compression bonded by means of a thermo-compression bonding tool with an adhesive resin interposed between a first area of the one main surface of the wiring board and the first electronic component, and a second electronic component mounted on a second area different from the first area of the one main surface of the wiring board by melting a soldering paste material and higher than the first electronic component in post-mounting height, and wherein the first electronic component is mounted before the mounting of the second electronic component.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: April 20, 2004
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.
    Inventor: Shigeru Nakamura
  • Publication number: 20040060969
    Abstract: A plurality of lands and a plurality of conducting wires connected independently to each land are formed on one side surface of an insulating substrate of a flexible printed circuit board. Through-holes are formed through the insulating substrate for exposing the lands to the other side surface. Solder is provided in the through-holes. The solder connects the lands to the head terminals on an inkjet head, which is located facing the other side surface of the insulating substrate. The insulating substrate separates the solder from areas between the conducting wires and from areas between the lands, thereby preventing short circuits from occurring when manufacturing the connecting structure with a low tolerance grade.
    Type: Application
    Filed: September 26, 2003
    Publication date: April 1, 2004
    Inventors: Koji Imai, Shuhei Hiwada
  • Patent number: 6713376
    Abstract: In a method of manufacturing a contact element, provision is made of a laminated body which has an insulating film, an electrically conductive layer stacked on the insulating film, and bump holes opened. A treatment is carried out so as to remove organic materials and the like from an interior of the bump holes and/or a surface of the insulating film before bumps are formed on the bump holes. The treatment may be a plasma treatment or an X-ray irradiation.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: March 30, 2004
    Assignee: Hoya Corporation
    Inventor: Osamu Sugihara
  • Publication number: 20040056073
    Abstract: A method is provided for forming a wafer stack. This may include providing a first wafer having a first plurality of metalized trenches on a surface of the first wafer. A second wafer may be provided having a second plurality of metalized trenches on a surface of the second wafer facing the first wafer. The first plurality of metalized trenches may be solder bonded to the second plurality of metalized trenches.
    Type: Application
    Filed: September 25, 2003
    Publication date: March 25, 2004
    Inventors: Stefan Hau-Riege, Christine Hau-Riege
  • Patent number: 6708868
    Abstract: A method for molding and soldering electrical connection pads to the electrical connection-receiving zones of electronic components or circuits includes an operation for the injection of conductive liquid alloy into a guide open at one end placed so as to face the connection-receiving zone of the component. The guide is formed by two separable parts, a mold and an injection matrix, the mold and the injection matrix including passages, with a narrowing of the guide at the level of the separation of the parts, and the parts of the guide are separated while the alloy is in the liquid state. Such a method may find particular application to, as an example, making connection pads for substrates or electronic components.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: March 23, 2004
    Assignee: Applied Utech
    Inventor: Eric Pilat
  • Publication number: 20040046002
    Abstract: An article of manufacture including an organic structure and inorganic atoms bonded to specific locations on the organic structure.
    Type: Application
    Filed: September 9, 2003
    Publication date: March 11, 2004
    Applicant: IBM CORPORATION
    Inventors: Ravi F. Saraf, Hemantha K. Wickramesinghe
  • Patent number: 6702176
    Abstract: A solder consists essentially of 1.0% to 4.0% of Ag by mass, 0.2% to 1.3% of Cu by mass, 0.02% to 0.06% of Co by mass, and the remaining of Sn and inevitable impurities.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: March 9, 2004
    Assignees: NEC Toppan Circuit Solutions, INC, Solder Coat Co., Ltd.
    Inventors: Toshihide Ito, Shiro Hara
  • Patent number: 6698084
    Abstract: A method for manufacturing radio frequency module components with a surface acoustic wave element includes a gold plating step of plating gold at a component bonded portion on a conductive surface of a ceramic multi-layer substrate 40 to have a mounted electrode 43, a surface acoustic wave element mounting step of face down bonding a flip chip 30 as the surface acoustic wave element on the ceramic multi-layer substrate 40 by the gold—gold connection, a side wall formation step of bonding a side wall member 60 surrounding the flip chip 30 onto the ceramic multi-layer substrate 40 by adhesives, a lid formation step of bonding a lid member 61 enclosing an opening of the side wall onto the side wall member by adhesives, after mounting the flip chip 30, and a soldered component mounting step of mounting a soldered component 50 by the use of solder, after the lid formation step.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: March 2, 2004
    Assignee: TDK Corporation
    Inventor: Fumio Uchikoba
  • Patent number: 6700204
    Abstract: A substrate for accommodating a passive component is proposed, including a core layer defined with a chip attach area and a trace forming area surrounding the chip attach area, with a solder mask layer being applied on the trace forming area. At least a pair of solder pads are formed on the trace forming area, and partly exposed to outside of the solder mask layer. The solder pads are each formed at a central position with an recess, allowing the core layer to be partly exposed through the recesses of the solder pads. For bonding a passive component to the solder pads, solder paste soldered on the solder pads forms a recessed top surface due to surface tension of the solder paste, and generates a downward and convergent dragging force for properly positioning the passive component on the solder pads without producing shifting or tombstone effect.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: March 2, 2004
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Ping Huang, Chien-Te Chen
  • Patent number: 6694610
    Abstract: A method of producing an electronic component including the steps of applying solder paste to both a connection land electrode, to which a surface-mount part is to be electrically and mechanically connected, and a case-fixing electrode, to which an engaging portion of a shield case is to be electrically and mechanically connected and affixed; mounting the surface-mount part and the shield case onto predetermined locations of a printed board, the shield case being mounted so as to accommodate the surface-mount part therein; and after the mounting step, soldering the surface-mount part and the shield case onto the printed board at the same time by putting printed board, having the surface-mount part and the shield case mounted thereon, into a reflow oven. The electronic component production method makes it possible to efficiently produce an electronic component having a structure in which a surface-mount part is accommodated in a shield case.
    Type: Grant
    Filed: February 16, 2000
    Date of Patent: February 24, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Kazuhiko Kitade
  • Patent number: 6693801
    Abstract: An electronic device includes a wiring board, and at least one pair of signal lines that is provided on the wiring board in parallel and has an equal length. A chip is mounted on the wiring board and includes at least one differential driver which outputs complementary digital transmit signals to said at least one of lines. A pair of power system lines is provided to supply first and second power supply voltages to the above-mentioned at least one differential driver. The power system lines are parallel to each other and have an equal length.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: February 17, 2004
    Inventor: Kanji Otsuka
  • Patent number: 6689412
    Abstract: The invention concerns a method for producing and soldering electrical connection beads (1) on mounting lands (2) for electronic circuit or component (3) electrical connection. The invention further concerns the device for implementing said method. The invention is characterized in that it essentially comprises the following steps: the operations for filling the stencil screen openings (4) by means of a squeegee (6) or the like and hot refusion are carried out with the stencil screen positioned above the substrate; the stencil screen (4) positioned on the component (3) during refusion is separated from the component after refusion but before the beads (1) are solidified, the latter being still in liquid state such that the balls that are being formed acquire their balanced position and their strictly identical spherical shape whatever their number; after the beads are solidified, the denatured binder is cleaned out.
    Type: Grant
    Filed: August 28, 2000
    Date of Patent: February 10, 2004
    Assignee: Societe Novatec S.A.
    Inventor: Francis Bourrieres
  • Publication number: 20040020972
    Abstract: Disclosed is an improved printed circuit board having circuit patterns printed thereon. It has a plurality of composite lands each including a first land having a terminal hole made at its center for inserting the terminal of a selected electric or electronic part or device, and a plurality of second lands each being contiguous to and extending outwards from the first land. The areas contiguous to the contours of the first and second lands have no conductive foils such as copper foils to expose the substrate surface of the printed circuit board. The exposed areas are effective to confine the thermal energy in the limited areas for soldering. And the composite land shape defines a ridged cone like solder lump, which can fixedly grip the terminal of the part or device.
    Type: Application
    Filed: July 28, 2003
    Publication date: February 5, 2004
    Inventor: Yoshiyuki Miyajima
  • Patent number: 6677179
    Abstract: A new method has been developed to provide underfill to chips mounted on substrates. First, an underfill is dispensed on the substrate. Second, the bumps of the chip are dipped in a flux that does not contain filler. Third, the chip that has been dipped in a tacky thermosettable flux is placed on the substrate, and fourth, the chip is soldered to the substrate, and simultaneously the underfill is cured. This process eliminates the interference on solder joints caused by the presence of filler in filled no-flow underfill. In addition, the fluxing property of the flux allows the use of underfills with emphasis on curing and mechanical properties instead of fluxing performance. Accordingly, a mounted device with reliable solder joints and underfill encapsulation is obtained.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: January 13, 2004
    Assignee: Indium Corporation of America
    Inventors: Wusheng Yin, Ning-Cheng Lee
  • Patent number: 6669077
    Abstract: A soldering method achieving a high-strength joint between a solder and an nickel/gold electroless plated surface is disclosed. The nickel/gold electroless plated layer is soldered using a solder including tin (Sn), silver (Ag), and copper (Cu). At a solder joint, a layer sturcture of nickel layer/intermetallic compound layer/solder layer is formed. The intermetallic compound layer is composed mainly of tin (Sn) and copper (Cu), and further including nickel (Ni). The intermetallic compound layer has cauliflower-shaped surfaces formed in a solder-layer's side thereof.
    Type: Grant
    Filed: September 1, 2000
    Date of Patent: December 30, 2003
    Assignee: NEC Corporation
    Inventors: Kazuyuki Kawashima, Yasunori Tanaka
  • Publication number: 20030226877
    Abstract: A chip or die attachment process and related apparatus, in which a desired quantity of solder (7 or 17) is dispensed onto each, in turn, of a number of desired locations on a substrate (4 or 18), and then an integrated-circuit chip (10) is precisely positioned at each location immediately after the solder is dispensed at that location. Hot gas heaters are used both to heat the solder (7 or 17) as it is dispensed onto the substrate (4 or 18), and to heat the integrated-circuit chip (10) and to reflow the solder beneath the chip. In one form of the invention, the solder is dispensed from a wire spool (1) and melted in position on the substrate (4). Alternatively, the solder is dispensed as a drop (16) from a liquid solder reservoir (13).
    Type: Application
    Filed: June 5, 2002
    Publication date: December 11, 2003
    Inventors: Dean Tran, Salim Akbany, Maurice Lowery, Leon M. Singleton, Ronald A. DePace
  • Publication number: 20030222125
    Abstract: A stencil used for printing solder paste on a contact pad of a printed wiring board has one or more reverse-tapered apertures passing there through, wherein the apertures have a variable cross-section that is larger at the fill side of the stencil (i.e., where solder paste enters the apertures) than at the board side of the stencil (i.e., where the stencil contacts the contact pad of the printed wiring board).
    Type: Application
    Filed: May 29, 2002
    Publication date: December 4, 2003
    Inventors: Ian McPhee Fleck, Ron Tripp, Prashant Chouta
  • Publication number: 20030222124
    Abstract: A radio wave soldering method provides instant heating for substrate of semiconductor device. The radio wave soldering method can heat a local portion of a substrate rapidly to 500-600° C. The method is suitable for substrate of semiconductor device with limit heat-resistance.
    Type: Application
    Filed: May 29, 2002
    Publication date: December 4, 2003
    Inventors: Yu-Peng Chung, Robert Lee, Max Lin
  • Patent number: 6651869
    Abstract: A method of wave soldering a circuit board while avoiding reflow of a solder joint on the topside of the board from heat conducted from the solder wave through at least one via in the board in heat conducting relation with the topside solder joint, comprises subjecting the circuit board to a solder wave and absorbing heat being conducted from the solder wave through the at least one via with an endothermic material in the via hole which undergoes a heat absorbing reaction. The heat absorbing reaction of the endothermic material is preferably a phase change, such as melting. The melted endothermic material is retained in the via hole during wave soldering by capillary forces and a cap on the lower end of the via hole. A disclosed method of making the circuit board includes locating the endothermic material in the via hole by inserting a preform of the endothermic material into the via hole or hot dispensing the endothermic material into the via hole.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: November 25, 2003
    Assignee: Intel Corporation
    Inventors: Raiyomand F. Aspandiar, Tom E. Pearson, Christopher Combs