Particular Size Or Shape Patents (Class 228/246)
  • Patent number: 11817369
    Abstract: Disclosed herein are lids for integrated circuit (IC) packages with solder thermal interface materials (STIMs), as well as related methods and devices. For example, in some embodiments, an IC package may include a STIM between a die of the IC package and a lid of the IC package. The lid of the IC package may include nickel, the IC package may include an intermetallic compound (IMC) between the STIM and the nickel, and the lid may include an intermediate material between the nickel and the IMC.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: November 14, 2023
    Assignee: Intel Corporation
    Inventors: Bamidele Daniel Falola, Susmriti Das Mahapatra, Sergio Antonio Chan Arguedas, Peng Li, Amitesh Saha
  • Patent number: 11752571
    Abstract: A coherent beam coupled laser diode array includes an array of laser diodes. Each diode emits a beam propagating along a beam path. An array of collimation optics is included. Each of the collimation optics collimates one beam. A first lenslet array is included. Each lenslet refracts a portion of one beam and a portion of a different beam from the array. A partially reflecting mirror is included. A first portion of each beam propagates through the partially reflecting mirror and a second portion of each beam is reflected back toward the first lenslet array. The second portion of each beam reflected propagates back through the first lenslet array and the collimation optics and into one of the diodes in the array of laser diodes, thereby creating an optical cross coupling. A second lenslet array collimates each beam propagating through each lenslet to form a single laser beam.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: September 12, 2023
    Assignee: LEONARDO ELECTRONICS US INC.
    Inventors: Connor Magness, Prabhuram Thiagarajan, Jason Helmrich
  • Patent number: 11705690
    Abstract: A laser diode apparatus has a first waveguide layer including a gain region connected in series with a second waveguide layer with a second gain region. A tunnel junction is positioned between the first and second guide layers. A single collimator is positioned in an output path of laser beams emitted from the first and second waveguide layers. The optical beam from the single collimator may be coupled into an optical fiber.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: July 18, 2023
    Assignee: LEONARDO ELECTRONICS US INC.
    Inventors: Devin Earl Crawford, Prabhu Thiagarajan, Mark McElhinney
  • Patent number: 11406004
    Abstract: A metal-core printed circuit board (MCPCB) and method of generating an ultra-narrow, high-current pulse driver with a MCPCB is provided. The MCPCB includes a rigid, metal heat sink layer and at least one electrically conductive top layer. At least one electrically insulating dielectric layer is positioned between the conductive top layer and rigid, metal heat sink layer, wherein the dielectric layer has a thickness of less than 0.007 inches.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: August 2, 2022
    Assignee: LEONARDO ELECTRONICS US INC.
    Inventors: Eric Paul Ruben, Jean Michel Maillard, Prabhu Thiagarajan
  • Patent number: 11296481
    Abstract: A divergence reshaping apparatus for laser diodes having a fast axis and a slow axis includes a fast axis collimator element having positive optical power in the fast axis and no optical power in the slow axis. A slow axis magnifier element has no optical power in the fast axis and positive optical power in the slow axis. An objective element has positive optical power in the fast axis and no optical power in the slow axis. A slow axis collimator element has negative optical power in the fast axis and positive optical power in the slow axis. Every element is optically aligned down an optical axis, and wherein a beam traveling through every element is collimated, compressed and shifted in the fast axis and expanded and collimated in the slow axis.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: April 5, 2022
    Assignee: LEONARDO ELECTRONICS US INC.
    Inventor: Connor L. Magness
  • Patent number: 11164835
    Abstract: A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: November 2, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Takashi Noma, Kazuhiro Saito
  • Patent number: 11056854
    Abstract: An epoxy-free laser assembly includes at least one laser array and at least one optics assembly positioned within an optical path of at least one laser array. The laser array and the optics assembly are epoxy-free. In one example, the optics assembly has a beam shaping optic and a wavelength stabilization optic, wherein the wavelength stabilization optic is connected to beam shaping optic with at least one tab and solder. In another example, a plurality of optics assemblies is included within the laser assembly, whereby the laser array and all of the plurality of optics assemblies fit within a footprint of the heatsink. Methods of manufacturing the same are also provided.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: July 6, 2021
    Assignee: LEONARDO ELECTRONICS US INC.
    Inventors: Jason Helmrich, Steven Smith, Prabhu Thiagarajan
  • Patent number: 10840108
    Abstract: A method of forming a bonding element including a first transient liquid phase (TLP) bonding element including a first material and a second material, the first material having a higher melting point than the second material, a ratio of a quantity of the first material and the second material in the first TLP bonding element having a first value, and a second TLP bonding element including the first material and the second material, a ratio of a quantity of the first material and the second material in the second TLP bonding element having a second value different from the first value.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: November 17, 2020
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Bradley Paul Barber
  • Patent number: 10622299
    Abstract: An integrated circuit (IC) device, e.g., wafer, chip, die, interposer, carrier, etc., includes a patterned mask that includes a first opening that exposes a signal region of a first contact. The mask further includes a second opening that exposes a signal region of a second contact that neighbors the first contact. The mask further includes a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact. The mask further includes a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact. A multi terminal capacitor may be connected to the IC device such that a first terminal is connected to the extension region of the first contact and a second terminal is connected to the extension region of the second contact.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Jean Audet, Brian W. Quinlan, Charles L. Reynolds, Brian R. Sundlof
  • Patent number: 10597767
    Abstract: Methods for fabricating at least one nanoparticle include providing one or more substrates and depositing a substance on the one or more substrates. At least one portion of the substance is heated or annealed so the at least one portion beads up on the one or more substrates due to cohesive forces of the substance being greater than adhesive forces between the substrate and the substance. In some methods, a pattern generation process is performed to define the at least one portion. A combination of a substance material for the substance and a substrate material for the one or more substrates may also be selected so that the at least one portion beads up into a predetermined shape. The substance may also be deposited on the one or more substrates with a sub-monolayer thickness or with gaps to further reduce a nanoparticle size.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: March 24, 2020
    Assignee: Roswell Biotechnologies, Inc.
    Inventors: Barry L. Merriman, Paul W. Mola, Chulmin Choi
  • Patent number: 10561020
    Abstract: A process includes utilizing a pin array that includes multiple segmented pins for forming selectively plated through holes. The process includes forming a PCB laminate structure that includes multiple spinel-doped core layers and multiple through holes. Each spinel-doped core layer includes a heat-activated spinel material incorporated into a dielectric material. The process includes aligning individual segmented pins of a pin array with corresponding through holes of the PCB laminate structure, where each segmented pin includes heated segment(s) and insulating segment(s). The process includes inserting the segmented pins of the pin array into the corresponding through holes and generating heat within each heated pin segment that is sufficient to form metal nuclei sites in selected regions of the spinel-doped core layers adjacent to portions of the through holes that contain the heated pin segments. The metal nuclei sites function as seed layers to enable formation of selectively plated through holes.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Matthew S. Doyle, Jeffrey N. Judd, Joseph Kuczynski, Scott D. Strand, Timothy J. Tofil
  • Patent number: 10551262
    Abstract: A component arrangement comprising a first component which has a first joining surface and a second component which has a second joining surface. The first joining surface is connected to the second joining surface using an integrated reactive material system. The integrated reactive material system comprises at least one coating of at least one of the joining surfaces, and the integrated reactive material system comprises an activation region on one surface. The integrated activation region is arranged outside of the joined together regions of the first or second joining surfaces and adjoins the regions which are joined together.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: February 4, 2020
    Assignee: ENDRESS+HAUSER SE+CO.KG
    Inventors: Anh Tuan Tham, Benjamin Lemke, Jorg Brauer, Jan Besser, Maik Wiemer, Thomas Gessner
  • Patent number: 10493567
    Abstract: A solder alloy of the disclosure includes Sb of which a content is in a range of 3 wt % to 30 wt %, Te of which a content is in a range of 0.01 wt % to 1.5 wt %, Au of which a content is in a range of 0.005 wt % to 1 wt %, at least one of Ag and Cu, wherein a content rate of at least one of Ag and Cu in the solder alloy is in a range of 0.1 wt % to 20 wt %; and a content rate of a sum of Ag and Cu in the solder alloy is in a range of 0.1 wt % to 20 wt %; and a balance of Sn.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: December 3, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kazuki Sakai, Akio Furusawa, Hidetoshi Kitaura, Kiyohiro Hine
  • Patent number: 10447834
    Abstract: Embodiments are directed to an enclosure for an electronic device. In one aspect, an embodiment includes an enclosure having an enclosure component and an internal component that may be affixed along a bonding region. The enclosure component may be formed from an enclosure material and defines an exterior surface of the enclosure and an opening configured to receive a display. The internal component may be formed from a metal material different than the enclosure material. The bonding region may include an interstitial material that has a melting temperature that is less than a melting temperature of either one of the enclosure material or the metal material. The bonding region may also include one or more of the enclosure material or the metal material.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: October 15, 2019
    Assignee: Apple Inc.
    Inventors: Abhijeet Misra, Steven J. Osborne, Ian A. Spraggs, Marwan Rammah, William A. Counts
  • Patent number: 10081852
    Abstract: A mixed mother alloy is prepared from a solder mixture comprising a pyrolyzable flux and high melting point metal particles, the mixed mother alloy is charged into a large amount of molten solder and stirred, and a billet is prepared. The billet can then be extruded, rolled, and punched to form a pellet or a washer, for example.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: September 25, 2018
    Assignees: Senju Metal Industry Co., Ltd., Denso Corporation
    Inventors: Naohiko Hirano, Akira Tanahashi, Yoshitsugu Sakamoto, Kaichi Tsuruta, Takashi Ishii, Satoshi Soga
  • Patent number: 10039184
    Abstract: A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface opposite to each other, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive via connecting the first and the second patterned circuit layers. The first build-up circuit structure is disposed on the upper surface of the core layer and covers the first patterned circuit layer, wherein the first build-up circuit structure at least has a cavity, the cavity exposes a portion of the first patterned circuit layer and a cross-sectional profile of an edge of a top surface of the portion of the first patterned circuit layer exposed by the cavity is a curved surface.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: July 31, 2018
    Assignee: Unimicron Technology Corp.
    Inventors: Ming-Hao Wu, Wen-Fang Liu
  • Patent number: 9865556
    Abstract: A semiconductor device has a semiconductor die with a die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: January 9, 2018
    Assignee: STATS ChipPAC Pte Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 9831572
    Abstract: A socketless land grid array (LGA) is provided that uses an adhesive material rather than a socket to secure the optical communications module to the LGA and to provide the clamping force that is needed to maintain contact between the module and the LGA and to maintain a flat profile for the module and the LGA. Eliminating the LGA socket eliminates the need to drill holes in the host circuit board and the need for additional hardware (e.g., backing plates, screws, etc.) to secure a socket to the host circuit board. This allows the area of the host circuit board underneath the array of electrical contacts of the LGA to be used for routing electrically-conductive pathways of the host circuit board (e.g., vias and traces) and reduces the amount of time and effort that are needed to secure modules to the respective LGAs.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: November 28, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Laurence R. McColloch
  • Patent number: 9284134
    Abstract: A method and apparatus for positioning, holding and moving formed adhesive elements (40) to a heated bonding part (42) are disclosed. The apparatus includes a hopper (12) movably positioned over a matrix plate (14). The matrix plate includes a nesting matrix (18) defined by formed adhesive element-receiving apertures (22). An ejector system (20) is fitted beneath the matrix plate and includes a body (24) having a vacuum chamber (26) with an air inlet (28) and an air exhaust (30). The chamber is fluidly continuous with the apertures formed in the matrix plate (14). The ejector system includes a lifting body to which ejector stamps (34, 34?) and an inlet shut off shaft are attached. Channels for the ejector stamps are formed in the body of the ejector system. The ejector stamps are movably fitted in the apertures and the channels. In operation, the hopper (12) slides over the matrix and deposits formed adhesive elements into the apertures (22), then slides away.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: March 15, 2016
    Assignee: A. Raymond Et Cie
    Inventors: Mathias Hansel, Herbert Le Pabic, Emilien Koelbert
  • Publication number: 20150146399
    Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.
    Type: Application
    Filed: November 25, 2013
    Publication date: May 28, 2015
    Inventors: LAKSHMINARAYAN VISWANATHAN, L.M. Mahalingam, David F. Abdo, Jaynal A. Molla
  • Patent number: 9004343
    Abstract: In a reflow soldering apparatus, air heated by heaters is blown by fans onto a printed circuit board. Temperature controllers that control temperature of the heaters supply operation amount thereof to a calculation unit that calculates consumed electric energy of soldering apparatus. Inverters that control revolution of fans supply a value of current to the calculation unit. A control unit supplies a coefficient of the consumed electric energy to the calculation unit. The calculation unit calculates a total amount of consumed electric energy of the reflow soldering apparatus based on the operation amount, value of current and coefficient of the consumed electric energy thus obtained. A display unit displays on an operation screen the total amount of consumed electric energy of the reflow soldering apparatus, which has been calculated by the calculation unit.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: April 14, 2015
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Hiroyuki Inoue, Tadayoshi Ohtashiro
  • Patent number: 8991680
    Abstract: The electrode array is a device for making electrical contacts with cellular tissue or organs. The electrode array includes an assembly of electrically conductive electrodes arising from a substrate where the electrodes are hermetically bonded to the substrate. A method of manufacture of an electrode array and associated circuitry is disclosed where the braze preform tab disappears during the braze bonding process and is completely drawn into the substrate feedthrough holes such that the braze perform tab is completely involved in the braze joint and is no longer connecting the adjacent electrodes.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: March 31, 2015
    Assignee: Alfred E. Mann Foundation for Scientific Research
    Inventors: Joseph H. Schulman, Guangqiang Jiang, Charles L. Byers
  • Publication number: 20150055312
    Abstract: Disclosed herein is an interposer substrate, including: a core layer and a through core via (TCV) penetrating through the core layer; circuit wirings formed on both surfaces of the core layer and a TCV upper pad and a TCV lower pad which are each bonded to upper and lower surfaces of the TCV formed on both surfaces of the core layer; upper insulating layers covering the TCV upper pad and the circuit wiring formed on one surface of the core layer and having the circuit wirings formed on upper surfaces thereof; a stack via penetrating through the upper insulating layers of each layer and having one end connected to the TCV upper pad; and a lower insulating layer covering the TCV lower pad and the circuit wiring formed on the other surface of the core layer and provided with an opening which exposes the TCV lower pad.
    Type: Application
    Filed: April 11, 2014
    Publication date: February 26, 2015
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jeong Ho LEE, Mi Jin PARK, Chang Bae LEE, Young Do KWEON
  • Patent number: 8960525
    Abstract: A brazing process and plate assembly are disclosed. The brazing process includes positioning a braze foil on a first workpiece, then securing the braze foil to the first workpiece to form a brazable component, then positioning a second workpiece proximal to the brazable component, and then brazing the second workpiece to the brazable component. Additionally or alternatively, the brazing process includes positioning the braze foil on a tube, then securing the braze foil to the tube to form a brazable tube, then positioning a plate of a plate assembly proximal to the brazable tube, and then brazing the plate to the brazable tube. The plate assembly includes a plate and a tube brazed to the plate by a braze foil secured to the tube.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: February 24, 2015
    Assignee: General Electric Company
    Inventors: David Edward Schick, Srikanth Chandrudu Kottilingam, Johnie Franklin McConnaughhay, Brian Lee Tollison, Yan Cui
  • Patent number: 8955735
    Abstract: A method is used for implanting solder balls of an integrated circuit by operating a ball implanting machine. The ball implanting machine includes a suction fixture, an evacuating device, two pivoting and inverting devices, a guide plate, a ball carrier, and a substrate. The suction fixture has a plurality of ball grooves. The guide plate has a plurality of guide holes each aligning with a respective one of the ball grooves of the suction fixture. The ball carrier contains a plurality of solder balls. Thus, each of the solder balls is extended through the respective guide hole of the guide plate into the respective ball groove of the suction fixture, so that the solder balls will not protrude outward from the guide plate and will not interfere with or jam each other during movement of the ball carrier.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: February 17, 2015
    Assignee: Zen Voce Corporation
    Inventors: Chao-Shang Chen, Yu-Kai Lin
  • Patent number: 8944309
    Abstract: A solder joint may be used to attach components of an organic vapor jet printing device together with a fluid-tight seal that is capable of performance at high temperatures. The solder joint includes one or more metals that are deposited over opposing component surfaces, such as an inlet side of a nozzle plate and/or an outlet side of a mounting plate. The components are pressed together to form the solder joint. Two or more of the deposited metals may be capable of together forming a eutectic alloy, and the solder joint may be formed by heating the deposited metals to a temperature above the melting point of the eutectic alloy. A diffusion barrier layer and an adhesion layer may be included between the solder joint and each of the components.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: February 3, 2015
    Assignee: The Regents of The University of Michigan
    Inventors: Stephen R. Forrest, Gregory McGraw
  • Patent number: 8944310
    Abstract: A soldering method achieves little void and good joint condition in soldering an insulated circuit board and a semiconductor chip using a tin-high antimony solder material. A method of manufacturing a semiconductor device includes the steps of preparing a solder plate having a U-shape; mounting the solder plate on a substrate; mounting a semiconductor chip on the solder plate; fusing the solder plate in a reducing gas atmosphere; and reducing a pressure of the reducing gas atmosphere to a pressure lower than the atmospheric pressure when melting the solder plate.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: February 3, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Takeshi Matsushita, Eiji Mochizuki, Tatsuo Nishizawa, Shunsuke Saito
  • Patent number: 8939347
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein magnetic particles distributed within a solder paste may be used to form a magnetic intermetallic compound interconnect. The intermetallic compound interconnect may be exposed to a magnetic field, which can heat a solder material to a reflow temperature for attachment of microelectronic components comprising the microelectronic packages.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: January 27, 2015
    Assignee: Intel Corporation
    Inventors: Rajasekaran Swaminathan, Ravindranath V. Mahajan
  • Patent number: 8925793
    Abstract: A method of bonding an electrical component to a substrate includes applying solder paste on to a substrate. Solder preform has an aperture is formed therethrough and is then urged into contact with the solder paste, such that solder paste is urged through the aperture. An electrical component is then urged into contact with the solder preform and into contact with the solder paste that has been urged through the aperture, thereby bonding the electrical component, the solder preform, and the substrate together to define a reflow subassembly.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: January 6, 2015
    Assignee: DunAn Microstaq, Inc.
    Inventors: Parthiban Arunasalam, Siddharth Bhopte, Joe Albert Ojeda, Sr.
  • Patent number: 8919634
    Abstract: A solder ball printing apparatus fills plural openings formed in a mask with solder balls using a squeegee and prints the solder balls on plural electrode portions formed on a surface of a substrate facing the mask. The solder ball printing apparatus includes: a substrate mounting table on which the substrate is mounted and on the back surface side of which plural hole portions are formed; a print table on which the substrate mounting table is mounted; an XY? stage which can drive the print table in a horizontal plane; a print table cylinder which can vertically drive the print table; a mask absorption portion which has members that can be fitted into the substrate mounting table; and a mask absorption cylinder which can vertically drive the mask absorption portion.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: December 30, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Akio Igarashi, Hirokuni Kurihara, Ryosuke Mizutori
  • Patent number: 8910853
    Abstract: In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Alexandre Blander, Peter J. Brofman, Donald W. Henderson, Gareth G. Hougham, Hsichang Liu, Eric D. Perfecto, Srinivasa S.N. Reddy, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof, Julien Sylvestre, Renee L. Weisman
  • Patent number: 8840007
    Abstract: The invention relates to a compound sealing method for glass plates, which is characterized by realizing the air-tight joint between compounded glass plates in a preset position by using a metal brazing technology. The invention provides a brand new technological method for the compound sealing between glass plates. The method has the advantages of firm connection in sealing positions, high air tightness, favorable thermal shock resistance and the like, and the annealing of toughened glass are avoided because of a lower brazing temperature used, thereby providing convenience to the processing of toughened vacuum glass, toughened insulated glass and other toughened compound glass products.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: September 23, 2014
    Assignee: Luoyang Landglass Technology Co., Ltd
    Inventor: Yanbing Li
  • Publication number: 20140262184
    Abstract: Two components necessary to make up a heat exchanger assembly generally need to be brazed. Two components may be secured which do not contain a cladded alloy. Staking or crimping is used to hold the two components together while securing a braze ring captured between the two components which acts as a brazing mechanism.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: CALSONICKANSEI NORTH AMERICA, INC.
    Inventors: James Dean Snow, William Tracey Guffey
  • Patent number: 8833636
    Abstract: A process and apparatus for forming and transferring metal arrays of balls and shapes is described incorporating molds, tape, injection molded metal such as solder, metal reflow and a mask on a substrate for shearing solidified metal of metal arrays into respective openings in the mask.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Peter A. Gruber, Paul A. Lauro, Jae-Woong Nah
  • Patent number: 8814030
    Abstract: Alloy formation systems and methods and a mechanism, strategy and design for power electronics having high operating temperatures. The system creates a bondline targeted for performance in power electronics. The system provides for sequential alloy growth in high temperature operating power electronics. The system is at least applicable to wafer-to-wafer, die-to-wafer, die-to-substrate, or die-to-die bonding.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 26, 2014
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventor: Sang Won Yoon
  • Publication number: 20140234649
    Abstract: The invention relates to a layered composite (10), in particular for connecting electronic components as joining partners, comprising at least one substrate film (11) and a layer assembly (12) applied to the substrate film. The layer assembly comprises at least one sinterable layer (13), which is applied to the substrate film (11) and which contains at least one metal powder, and a solder layer (14) applied to the sinterable layer (13). The invention further relates to a method for forming a layered composite, to a circuit assembly containing a layered composite (10) according to the invention, and to the use of a layered composite (10) in a joining method for electronic components.
    Type: Application
    Filed: September 21, 2012
    Publication date: August 21, 2014
    Inventors: Thomas Kalich, Frank Wetzl, Bernd Hohenberger, Rainer Holz, Christiane Frueh, Andreas Fix, Michael Guyenot, Andrea Feiock, Martin Rittner, Michael Guenther
  • Patent number: 8783544
    Abstract: A brazing alloy is provided in the form of a wire, rod or preform, and is made of, in weight percent: 3-7.5% P, 0.1-1.9% Zn, 0-74.7% Ag, 0-80% Au, 0-10% Sn, 0-5% Ni, 0-3% each of Si, Mn, Li, and Ge, and the balance copper in an amount of at least 21.7%. In additional embodiments, Zn may be present in an amount of 0.6-1.9%. A method of torch brazing is also provided. The method includes forming the alloy into a wire or rod, placing the tip of the wire or rod in contact with a surface of a joint, heating the joint surface using a torch flame, and contacting the tip of the wire or rod to the heated joint surface to melt and flow the alloy onto the joint surface and into the joint under capillary action.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 22, 2014
    Inventor: Joseph W. Harris
  • Patent number: 8781589
    Abstract: The invention is a method of hermetically bonding a ceramic part to a metal part by welding and brazing a component assembly comprised of metal parts, a ceramic part, and a metal ferrule having alignment lips. The ceramic part is preferably a hollow tube of partially-stabilized zirconia that is brazed to an alignment ferrule that is preferably titanium or a titanium alloy, such as Ti-6Al-4V. On one end the component assembly is brazed to an end cap for closure. On the other end the alignment ferrule is preferably brazed to a ring that is preferably comprised of a noble metal, such as platinum, iridium, or alloys of platinum and iridium. The ring is laser welded to an eyelet that is preferably comprised of a noble metal.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: July 15, 2014
    Assignee: Alfred E. Mann Foundation For Scientific Research
    Inventors: Guangqiang Jiang, Attila Antalfy
  • Publication number: 20140182932
    Abstract: A disk having at least one electric connecting element is described. The disk has a substrate, an electrically conductive structure on a region of the substrate, a connecting element containing at least chromium-containing steel, and a layer of a soldering compound that electrically connects the connecting element to sub-regions of the electrically conductive structure.
    Type: Application
    Filed: April 17, 2012
    Publication date: July 3, 2014
    Applicant: Saint-Gobain Glass France
    Inventors: Harald Cholewa, Christoph Degen, Bernhard Reul, Mitja Rateiczak, Andreas Schlarb, Lothar Lesmeister
  • Patent number: 8763880
    Abstract: A brazing sheet material including a core alloy layer bonded on at least one side with an aluminum brazing clad layer or layers forming a filler material of a 4000-series aluminum alloy. The core layer is made from an aluminum alloy having (in wt. %): Mg 1.0 to 3.0, Mn 0 to 1.8, Cu 0 to 0.8, Si 0 to 0.7, Fe 0 to 0.7, optionally one or more elements selected from the group (Zr, Cr, Hf, T), Zn 0 to 0.5, impurities and aluminum. The filler material forms a 4000-series aluminum alloy further including one or more wetting elements selected from Bi 0.03-0.5, Pb 0.03-0.5, Sb 0.03-0.5, Li 0.03-0.5, Se 0.03-0.5, Y 0.03-0.05, Th 0.03-0.05, wherein the sum of these elements being 0.5% or less.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: July 1, 2014
    Assignee: Aleris Rolled Products Germany GmbH
    Inventor: Adrianus Jacobus Wittebrood
  • Patent number: 8740046
    Abstract: A soldering system includes a track, a laying device, a boiler, a shelter, a transmission roller, a position sensor, a thermal radiation heating device, and a driving device. At least one hole is formed on the shelter, and a shape and a dimension of at least one hole on the shelter corresponds to a shape and a dimension of a DIP component. The transmission roller rotates the shelter according to a transmission speed of the track. The position sensor detects a position of a circuit board relative to the boiler. The thermal radiation heating device heats an area on a second surface of the circuit board different from a first surface adjacent to the DIP component through the at least one hole on the shelter continuously, so as to increase a temperature of the second surface when the first surface of the circuit board is passing through the boiler.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: June 3, 2014
    Assignee: Wistron Corporation
    Inventors: Hao-Chun Hsieh, Chia-Hsien Lee
  • Patent number: 8740041
    Abstract: A brazing ring with integrated fluxing product and methods for production thereof is described. The brazing ring has a c-shaped body with a plurality of channels extending the thickness of the ring and disposed about the circumference thereof. The channels are separated by radially extending flanges with enlarged distal ends that extend into the channels. The enlarged ends at least partially enclose the channels to aid in retention of a fluxing product disposed in therein. The c-shape may enable flexure of the ring for installation on a pipe or fitting and a friction fit to maintain an installed position. The brazing ring is formed by extruding a filler material to form a tube with the desired profile and compressing the fluxing product into the channels of the profile. The tube is subsequently sectioned perpendicularly to its length to produce a plurality of the brazing rings.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: June 3, 2014
    Assignee: Flux Brazing Schweiss-Und Lotstoffe USA, LLC
    Inventors: Jasper G. J. Visser, Jacobus C. B. Kotzé
  • Patent number: 8733620
    Abstract: A solder is deposited on a heat sink. The solder is first reflowed at a first temperature that is below about 120° C. The solder is second heat aged at a temperature that causes the first reflowed solder to have an increased second reflow temperature. The heat aging process results in less compressive stress in a die that uses the solder as a thermal interface material. The solder can have a composition that reflows and adheres to the die and the heat sink without the use of organic fluxes.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: May 27, 2014
    Assignee: Intel Corporation
    Inventors: Mukul Renavikar, Susheel G. Jadhav
  • Patent number: 8701973
    Abstract: A method of forming solder bumps on electrodes of a circuit board without producing bridging using a solder transfer sheet which does not require alignment includes superposing a circuit board and a solder transfer sheet having a solder layer adhered to at least one side of a supporting substrate, performing heating under pressure to a temperature lower than the solidus temperature of the solder to selectively perform solid phase diffusion bonding of the solder layer to electrodes, and peeling the transfer sheet from the circuit board. The solder layer is in the form of a continuous solder coating or in the form of a monoparticle layer of solder particles which are adhered to the supporting substrate by an adhesive layer.
    Type: Grant
    Filed: February 15, 2010
    Date of Patent: April 22, 2014
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Takeo Kuramoto, Kaichi Tsuruta, Takeo Saitou
  • Publication number: 20140099514
    Abstract: A continuous hot bonding method for producing a bi-material strip with a strong bond therebetween is provided. The method comprises sanding a first strip formed of steel; and applying a layer of first particles, typically formed of copper, to the sanded first strip. The method next includes heating the first strip and the layer of the first particles, followed by pressing a second strip formed of an aluminum alloy onto the heated layer of the first particles. The aluminum alloy of the second strip includes tin particles, and the heat causes the second particles to liquefy and dissolve into the melted first particles. The first particles and the second particles bond together to form bond enhancing metal particles, which typically comprise bronze.
    Type: Application
    Filed: October 10, 2013
    Publication date: April 10, 2014
    Applicant: Federal-Mogul Corporation
    Inventor: David Michael Saxton
  • Patent number: 8690041
    Abstract: A method of soldering a DIP component on a circuit board includes piercing the DIP component through the circuit board, laying fluxer on the circuit board, passing a first surface of the circuit board through a boiler so that molten tin from the boiler flows between the DIP component and the circuit board through the first surface of the circuit board, and heating a second surface of the circuit board different from the first surface so as to increase temperature of the second surface by a thermal radiation heating device to when the first surface of the circuit board passes through the boiler.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: April 8, 2014
    Assignee: Wistron Corporation
    Inventors: Hao-Chun Hsieh, Chia-Hsien Lee
  • Publication number: 20140092572
    Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: MD Altaf Hossain, Scott A. Gilbert
  • Patent number: 8684257
    Abstract: A plurality of conductor bars are positioned within slots of a laminated electric steel disc stack, and the ends of the conductor bars are brazed to end rings to manufacture a rotor. The method includes inserting the conductor bars into the slots of the disc stack, providing the end rings with slots for receiving the ends of the conductor bars; positioning spacers of braze material adjacent each end of each of the conductor bars to create a gap between the end rings and the steel disc stack; and applying heat to melt the braze material of the spacers whereby braze material is furnished by the spacers of braze material to braze the first and second ends of the conductor bars to the first and second end rings. Channels are provided in the face of the end rings facing the steel disc stack to drain away excess braze material.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: April 1, 2014
    Assignee: GM Global Technology Operations LLC
    Inventors: Richard J. Osborne, Qigui Wang, Yucong Wang
  • Patent number: 8678271
    Abstract: In one disclosed embodiment, the present method for preventing void formation in a solder joint formed between two metallic surfaces includes forming at least one slit in a layer of solder to form a slit solder layer, positioning the slit solder layer between the two metallic surfaces, and heating the slit solder layer to form the solder joint, wherein the at least one slit forms an outgas alley to prevent void formation in the solder joint. Where solder joint width is a concern, the present method includes applying external pressure concurrently with heating. The outgas alley is formed to provide a ready avenue of escape for flux gasses produced during formation of the solder joint.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: March 25, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Phanit Tameerug
  • Publication number: 20140061287
    Abstract: A lead-free solder ball for electrodes of a BGA or CSP comprising 0.5-1.1 mass % of Ag, 0.7-0.8 mass % of Cu, 0.05-0.08 mass % of Ni, and a remainder of Sn. Even when a printed circuit board to which the solder ball is bonded has Cu electrodes or Au-plated or Au/Pd-plated Ni electrodes, the solder ball has good resistance to drop impacts. The composition may further contain at least one element selected from Fe, Co, and Pt in a total amount of 0.003-0.1 mass % or at least one element selected from Bi, In, Sb, P, and Ge in a total amount of 0.003-0.1 mass %.
    Type: Application
    Filed: March 28, 2012
    Publication date: March 6, 2014
    Applicant: SENJU METAL INDUSTRY CO., LTD.
    Inventors: Tsukasa Ohnishi, Yoshie Yamanaka, Ken Tachibana