Lateral Structure, I.e., Current Flow Parallel To Main Device Surface Patents (Class 257/141)
  • Patent number: 10930650
    Abstract: In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: February 23, 2021
    Assignee: STMicroelectronics International N.V.
    Inventor: Vishal Kumar Sharma
  • Patent number: 10923589
    Abstract: A high voltage device includes: a crystalline silicon layer, a well, a body region, a gate, a source, and a drain. The body region has a P-type conductivity type, and is formed in the well. The gate is located on and in contact with the well. The source and the drain have an N-type conductivity type, and are located below, outside, and at different sides of the gate, and are located in the body region and the well respectively. An inverse region is defined in the body region between the source and the well, to serve as an inverse current channel in an ON operation. The inverse region includes a germanium distribution region which has a germanium atom concentration higher than 1*1013 atoms/cm2. Adrift region is defined in the well, between the body region and the drain, to serve as a drift current channel in an ON operation.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: February 16, 2021
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Kun-Huang Yu
  • Patent number: 10600911
    Abstract: A transistor includes a trench formed in a semiconductor substrate. A gate electrode is formed in the trench with a first edge of the gate electrode proximate to a first sidewall of the trench. A first field plate is formed in the trench with the first field plate located between a second edge of the gate electrode and a second sidewall of the trench. A dielectric material is formed in the trench with the dielectric material having a first thickness between the first sidewall and a first edge of the first field plate, and a second thickness between the second sidewall and a second edge of the first field plate, the second thickness larger than the first thickness.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: March 24, 2020
    Assignee: NXP USA, INC.
    Inventors: Bernhard Grote, Saumitra Raj Mehrotra, Ljubo Radic, Vishnu Khemka, Mark Edward Gibson
  • Patent number: 10593752
    Abstract: An integrated circuit and method has an isolated well with an improved isolated well contact. The well contact diffusion is isolated from a device diffusion of opposite conductivity type within the isolated well by an isolation transistor gate.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: March 17, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Bruce Lynn Pickelsimer, Patrick Robert Smith, Terry James Bordelon, Jr.
  • Patent number: 10453916
    Abstract: A semiconductor device includes: a semiconductor substrate with a first conductivity type; a semiconductor layer with a second conductivity type formed on the semiconductor substrate; a drain region with the second conductivity type and a source region with the second conductivity type formed to be spaced apart from each other in a surface region of the semiconductor layer; a drain buffer region with the second conductivity type formed in the semiconductor substrate directly under the drain region and in the semiconductor layer; a conductivity type well region with the second conductivity type formed on the semiconductor layer between the drain region and the drain buffer region; and a drain metal formed on the drain region to be electrically connected to the drain region and to overlap the well region in a plan view.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: October 22, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Daisuke Ichikawa
  • Patent number: 10290726
    Abstract: A lateral insulated gate bipolar transistor, comprising: a substrate (100), having a first conductivity type; an insulating layer (200), formed on the substrate (100); an epitaxial layer (300), having a second conductivity type and formed on the insulating layer (200); a field oxide layer (400), formed on the epitaxial layer (300); a first well (500), having the first conductivity type; a plurality of gate trench structures (600); second source doped regions (720), having the second conductivity type; first source doped regions (710), having the first conductivity type; a second well (800), having the second conductivity type; a first drain doped region (910), having the first conductivity type and formed on a surface layer of the second well (800); gate lead-out ends (10); a source lead-out end (20); a drain lead-out end (30).
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: May 14, 2019
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Yan Gu, Wei Su, Sen Zhang
  • Patent number: 10276673
    Abstract: The description relates to a semiconductor die having a stacking structure of silicon-metallic conductive layer-silicon, and the semiconductor die according to embodiments includes a stacking structure of first semiconductor layer-metallic conductive layer-second semiconductor layer, and first and second power semiconductor devices in the first semiconductor layer, in which the first power semiconductor device includes a first source bump and a first gate bump, first trench gate electrodes under the first source bump, and a first channel among the plurality of first trench gate electrodes, in which the second power semiconductor device includes a second source bump and a second gate bump, second trench gate electrodes under the second source bump, and a second channel among the plurality of second trench gate electrodes, and in which the metallic conductive layer includes a metal layer.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: April 30, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Myung Ho Park, Ui Kyu Seo, Young Ho Seo, Jae Sik Choi
  • Patent number: 10103349
    Abstract: The embodiments of the present invention provide an electroluminescent device and manufacturing method thereof, display substrate and display device, which relate to the field of display technology. The overall luminous efficiency of the OLED device is improved without reducing the thickness of the metal cathode, ensuring a good display effect of the OLED device. The electroluminescent device comprises a metal cathode layer, a functional layer and a transparent anode layer arranged on a basal substrate; the transparent anode layer is located on the light exit side of the electroluminescent device; the functional layer is located between the metal cathode layer and the transparent anode layer; the functional layer comprises an electron transport layer, an emitting layer and a hole transport layer sequentially arranged from the metal cathode layer.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: October 16, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Haidong Wu, Minghua Xuan, Weilin Lai, Xiang Feng
  • Patent number: 10057502
    Abstract: A photosensor includes a photoelectric converter including first and second electrodes and a photoelectric conversion layer therebetween; a transistor having a gate, a source and a drain; a connector electrically connecting the first electrode and the gate together; and one or more wiring layers including a part of the connector. The transistor outputs an electric signal from one of the source and the drain, the electric signal corresponding to a change in dielectric constant between the first electrode and the second electrode, the change being caused by incident light on the photoelectric conversion layer. The one or more wiring layers include a first line coupled to the one of the source and the drain and a second line supplied with a fixed voltage in a period during operation. A distance between the first line and the connector is less than a distance between the second line and the connector.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: August 21, 2018
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tokuhiko Tamaki, Takeyoshi Tokuhara
  • Patent number: 10038091
    Abstract: The present disclosure provides a semiconductor device including a substrate, a first well and a second well formed in the substrate, the first well being doped with dopants of a first conductivity type and the second well being doped with dopants of a second conductivity type, a third well within the first well, a gate structure partially formed over the first and second wells, and a first epi region on the third well and a drain region electrically coupled to the second well, the first epi region being doped with dopants of the second conductivity type.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 31, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Christian Schippel, Alban Zaka, Ignasi Cortes Mayol
  • Patent number: 9997599
    Abstract: A semiconductor device includes a substrate, a drift region, a source region, a gate region, a drain contact and a base region. The substrate is doped with a first dopant type. The drift region is disposed above the substrate, and is doped with the first dopant type. The source region, doped with the first dopant type. The gate region is disposed above the drift region and above the source region. The base region is disposed between the source region and the drift region. At least a portion of the base region includes at least one trench having a vertical wall and a horizontal wall. The base region is further configured to conduct current in a horizontal direction on the vertical wall and in a horizontal direction the horizontal wall.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: June 12, 2018
    Assignee: Purdue Research Foundation
    Inventor: James A. Cooper
  • Patent number: 9972679
    Abstract: To provide a semiconductor device having improved performances. A semiconductor substrate has, in the surface layer portion thereof, an n+ type semiconductor region for source and an n+ type semiconductor region for drain separated from each other. The semiconductor substrate has, on the main surface thereof between the n+ type semiconductor region for source and the n+ type semiconductor region for drain, a gate electrode via an insulating film as a gate insulating film. The semiconductor substrate has, in the main surface thereof between the channel formation region below the gate electrode and the n+ type semiconductor region for drain, a LOCOS oxide film and an STI insulating. Of the LOCOS oxide film and the STI insulating film, the LOCOS oxide film is located on the side of the channel formation region and the STI insulating film is on the side of the n+ type semiconductor region DR for drain.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: May 15, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Hajime Kataoka, Tatsuya Shiromoto, Tetsuya Nitta
  • Patent number: 9947746
    Abstract: A bipolar junction transistor (BJT) device includes a semiconductor substrate, a first doping region with a first conductivity, a second doping region with a second conductivity, a third doping region with the first conductivity, at least one stacked block and a conductive contact. The first doping region is formed in the semiconductor substrate. The second doping region is formed in the first doping region. The at least one stacked block is formed on and insulated from the second doping region. The third doping region is formed in the second doping region and disposed adjacent to the at least one stacked block. The conductive contact electrically connects the at least one stacked block with the third doping region.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: April 17, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Kai-Kuen Chang
  • Patent number: 9929259
    Abstract: A semiconductor device including: a P-type base region provided; an N-type emitter region provided inside the P-type base region; a P-type collector region that is provided on the surface layer portion of the N-type semiconductor layer and is separated from the P-type base region; a gate insulating film that is provided on the surface of the N-type semiconductor layer, and that contacts the P-type base region and the N-type emitter region; a gate electrode on the gate insulating film; a pillar shaped structure provided inside the N-type semiconductor layer between the P-type base region and the P-type collector region, wherein one end of the pillar shaped structure is connected to an N-type semiconductor that extends to the surface layer portion of the N-type semiconductor layer, and the pillar shaped structure includes an insulator extending in a depth direction of the N-type semiconductor layer.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: March 27, 2018
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hiroyuki Tanaka
  • Patent number: 9911928
    Abstract: A new class of blue emissive complexes are described. The compounds comprise pyridyl benzimidazole ligands with twisted aryl groups for improved color.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: March 6, 2018
    Assignee: Universal Display Corporation
    Inventors: Scott Beers, Geza Szigethy, Jason Brooks
  • Patent number: 9722021
    Abstract: An integrated circuit and method has an isolated well with an improved isolated well contact. The well contact diffusion is isolated from a device diffusion of opposite conductivity type within the isolated well by an isolation transistor gate.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: August 1, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bruce Lynn Pickelsimer, Patrick Robert Smith, Terry James Bordelon, Jr.
  • Patent number: 9633992
    Abstract: An ESD protection device is provided. Each of a first and a second well has a first conductive type. Each of a first and a second doping region has a second conductive type and is formed in the first well. A third doping region has the first conductive type. A fourth doping region has the second conductive type. The third and fourth doping regions are formed in the second doping region. Each of a fifth and a sixth doping region has the second conductive type and is formed in the second well. A seventh doping region has the first conductive type. An eighth doping region has the second conductive type. The seventh and eighth doping region are formed in the sixth doping region. A first and a second trigger gate are formed on the first and second wells and partially cover the second and sixth doping regions respectively.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: April 25, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yeh-Jen Huang, Yeh-Ning Jou, Geeng-Lih Lin
  • Patent number: 9431393
    Abstract: A semiconductor device includes: a first well provided in a semiconductor substrate; a second well provided in the semiconductor substrate, so as to be isolated from the first well; a Schottky barrier diode formed in the first well; and a PN junction diode formed in the second well, with an impurity concentration of the PN junction thereof set higher than an impurity concentration of the Schottky junction of the Schottky barrier diode, and being connected antiparallel with the Schottky barrier diode.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: August 30, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Dai Kanai, Taiji Ema, Kazushi Fujita
  • Patent number: 9431480
    Abstract: A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift layer (BDL) doped first type having a diluted BDL portion (DBDL) including dilution stripes. A semiconductor surface doped the second type is on the BDL. Dielectric isolation regions have gaps defining a first active area in a first gap region (first MOAT) and a second active area in a second gap region (second MOAT). A drain includes drain fingers in the second MOAT interdigitated with source fingers in the first MOAT each doped second type. The DBDL is within a fingertip drift region associated drain fingertips and/or source fingertips between the first and second MOAT. A gate stack is on the semiconductor surface between source and drain. The dilution stripes have stripe widths that increase monotonically with a drift length at their respective positions.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: August 30, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yongxi Zhang, Sameer P. Pendharkar, Scott G. Balster
  • Patent number: 9368500
    Abstract: A CMOS device includes a substrate, a pMOS transistor and an nMOS transistor formed on the substrate, and a gated diode. The gated diode includes a floating gate formed on the substrate in between the pMOS transistor and the nMOS transistor and a pair of a p-doped region and an n-doped region formed in the substrate and between the pMOS transistor and the nMOS transistor. The n-doped region is formed between the floating gate and the nMOS transistor, and the p-doped region is formed between the floating gate and the pMOS transistor.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: June 14, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chang-Tzu Wang, Yu-Chun Chen, Tien-Hao Tang, Kuan-Cheng Su
  • Patent number: 9322061
    Abstract: A technique includes forming a gradient channel with width and depth gradients. A mask is disposed on top of a substrate. The mask is patterned with at least one elongated channel pattern having different elongated channel pattern widths. A channel is etched in the substrate in a single etching step, the channel having a width gradient and a corresponding depth gradient both simultaneously etched in the single etching step according to the different elongated channel pattern widths in the mask.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: April 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jingwei Bai, Qinghuang Lin, Gustavo A. Stolovitzky, Chao Wang, Deqiang Wang
  • Patent number: 9318372
    Abstract: One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: April 19, 2016
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS, STMicroelectronics, Inc.
    Inventors: Olivier Nier, Denis Rideau, Pierre Morin, Emmanuel Josse
  • Patent number: 9305828
    Abstract: One or more embodiments of the invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a surface of a semiconductor structure having a stressed semiconductor layer and an insulator layer, at least two first trenches in a first direction delimiting a first dimension of at least one first transistor to be formed in the semiconductor structure; performing a first anneal to decrease the viscosity of the insulating layer; and forming, in the surface after the first anneal, at least two second trenches in a second direction delimiting a second dimension of the at least one transistor.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: April 5, 2016
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Denis Rideau, Emmanuel Josse, Olivier Nier
  • Patent number: 9171763
    Abstract: An improved semiconductor is provided whereby n-grade and the p-top layers are defined by a series of discretely placed n-type and p-type diffusion segments. Also provided are methods for fabricating such a semiconductor.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: October 27, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Ching-Lin Chan, Chen-Yuan Lin, Cheng-Chi Lin, Shih-Chin Lien
  • Patent number: 9153574
    Abstract: Provided is a semiconductor device including a deep doped region of a first conductivity type, a well region of a second conductivity type, a base region of the first conductivity type, an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor (MOS). The well region is disposed in the deep doped region. The base region is disposed in the well region and is not connected to the deep doped region. The IGBT is disposed on the well region at the first side of the base region, and includes a first doped region of the second conductivity type disposed in the base region. The MOS is disposed on the well region and the deep well region at the second side of the base region, and includes a second doped region of the second conductivity type disposed in the base region.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: October 6, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Ying-Chieh Tsai, Wing-Chor Chan, Jeng Gong
  • Publication number: 20150145592
    Abstract: A method includes biasing a first gate voltage to enable unipolar current to flow from a first region of a transistor to a second region of the transistor according to a field-effect transistor (FET)-type operation. The method also includes biasing a body terminal to enable bipolar current to flow from the first region to the second region according to a bipolar junction transistor (BJT)-type operation. The unipolar current flows concurrently with the bipolar current to provide dual mode digital and analog device in complementary metal oxide semiconductor (CMOS) technology.
    Type: Application
    Filed: March 26, 2014
    Publication date: May 28, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Xia Li, Daeik Daniel Kim, Bin Yang, Jonghae Kim, Daniel Wayne Perry
  • Publication number: 20150108542
    Abstract: A bipolar transistor includes a substrate and a first well in the substrate, the first well having a first dopant type. The bipolar transistor further includes a split collector region in the first well. The split collector region includes a highly doped central region having a second dopant type opposite the first dopant type; and a lightly doped peripheral region having the second dopant type, the lightly doped peripheral region surrounding the highly doped central region. A dopant concentration of the lightly doped peripheral region is less than a dopant concentration of the highly doped central region.
    Type: Application
    Filed: October 17, 2013
    Publication date: April 23, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fu-Hsiung YANG, Long-Shih LIN, Kun-Ming HUANG, Chih-Heng SHEN, Po-Tao CHU
  • Patent number: 9000519
    Abstract: An improved semiconductor is provided whereby n-grade and the p-top layers are defined by a series of discretely placed n-type and p-type diffusion segments. Also provided are methods for fabricating such a semiconductor.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: April 7, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Ching-Lin Chan, Chen-Yuan Lin, Cheng-Chi Lin, Shih-Chin Lien
  • Patent number: 8994067
    Abstract: The present invention relates to a technique of semiconductor devices, and provides a semiconductor device, which uses two controllable current sources to control the electron current and the hole current of the voltage-sustaining region of a thyristor under conduction state, making the sum of the two currents from anode to cathode close to a saturated value under high voltage, thus avoiding the current crowding effect in local region and increasing the reliability of the device. Besides, it further provides a method of implementing the two current sources in the device and a method to improve the switching speed.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: March 31, 2015
    Assignee: Cheng Dian Intelligent-Power Microelectronics Design Co., Ltd of Chengdu
    Inventor: Xingbi Chen
  • Publication number: 20150076555
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate; and a body region and a drift region formed in the semiconductor substrate. The semiconductor device also includes a bulk region and a source region formed in the body region. Further, the semiconductor device includes a drain region and a first shallow trench isolation structure having a ladder-like bottom formed in the drift region. Further, the semiconductor device also includes a gate structure spanning over an edge of the body region and an edge of the drift region formed on the semiconductor substrate and covering a portion of the first shallow trench isolation structure.
    Type: Application
    Filed: February 18, 2014
    Publication date: March 19, 2015
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Guangli YANG, Qianrong YU, Ming WANG, Xianyong PU
  • Publication number: 20150069464
    Abstract: A lateral bipolar transistor with deep emitter and deep collector regions is formed using multiple epitaxial layers of the same conductivity type. Deep emitter and deep collector regions are formed without the use of trenches. Vertically aligned diffusion regions are formed in each epitaxial layer so that the diffusion regions merged into a contiguous diffusion region after annealing to function as emitter or collector or isolation structures. In another embodiment, a lateral trench PNP bipolar transistor is formed using trench emitter and trench collector regions. In yet another embodiment, a lateral PNP bipolar transistor with a merged LDMOS transistor is formed to achieve high performance.
    Type: Application
    Filed: November 12, 2014
    Publication date: March 12, 2015
    Inventors: Shekar Mallikarjunaswamy, Francois Hebert
  • Patent number: 8969913
    Abstract: A high voltage laterally diffused metal-oxide-semiconductor (HV LDMOS) device, particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate having at least one highly doped buried portion, a first doped well grown over the substrate, a gate structure formed on the first well, a source and a drain formed on either side of the gate structure, and a second doped well having a U-shaped cross section formed in the first well. A portion of the drain is formed over the first well outside of the second well.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Maufacturing Company, Ltd.
    Inventors: Ker Hsiao Huo, Chih-Chang Cheng, Ru-Yi Su, Jen-Hao Yeh, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 8956925
    Abstract: Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: February 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Alain Loiseau
  • Patent number: 8946769
    Abstract: A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: February 3, 2015
    Assignee: MaxPower Semiconductor Inc.
    Inventors: Mohamed N. Darwish, Amit Paul
  • Publication number: 20150028385
    Abstract: The disclosed lateral bipolar transistor is manufactured by a manufacturing process of self-alignedly implanting an impurity to a gate electrode and thermally diffusing the impurity to form a base layer and an emitter layer. The gate electrode is utilized as an independent fourth terminal in addition to base, emitter, and collector terminals, whereby hfe can be controlled and enhanced by a gate potential. Accordingly, the present invention can provide a bipolar transistor that is hardly affected by a manufacturing variation, or that can be corrected by the gate terminal, and that has a high gain.
    Type: Application
    Filed: July 29, 2014
    Publication date: January 29, 2015
    Inventors: Tomoyuki Miyoshi, Takayuki Ooshima, Youhei Yanagida
  • Publication number: 20150014744
    Abstract: In a current-prioritized IGBT, a collector conductive layer is connected to one collector active region included in a collector region by a plurality of contacts. The number of contacts through which the collector conductive layer is connected to the one collector active region is larger than the number of contacts through which the emitter conductive layer is connected to one base active region included in a base region.
    Type: Application
    Filed: February 16, 2012
    Publication date: January 15, 2015
    Inventors: Mikio Tsujiuchi, Tetsuya Nitta
  • Patent number: 8933531
    Abstract: A semiconductor device including a base substrate; a semiconductor layer which is disposed on the base substrate and has a 2-Dimensional Electron Gas (2DEG) generated within the semiconductor layer; a plurality of first ohmic electrodes which are disposed on the central region of the semiconductor layer and have island-shaped cross sections; a second ohmic electrode which is disposed on edge regions of the semiconductor layer; and a Schottky electrode part has first bonding portions bonded to the first ohmic electrodes, and a second bonding portion bonded to the semiconductor layer. A depletion region is provided to be spaced apart from the 2DEG when the semiconductor device is driven at an on-voltage and is provided to be expanded to the 2DEG when the semiconductor device is driven at an off-voltage, the depletion region being generated within the semiconductor layer by bonding the semiconductor layer and the second bonding portion.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: January 13, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Woo Cul Jeon, Jung Hee Lee, Young Hwan Park, Ki Yeol Park
  • Publication number: 20150008481
    Abstract: The invention generally relates to a lateral power semiconductor transistor for example in integrated circuits. In particular the invention relates to Lateral Insulated Gate Bipolar Transistors or other lateral bipolar devices such as PIN diodes. The invention also generally relates to a method of increasing switching speed of a lateral bipolar power semiconductor transistor. There is provided a lateral bipolar power semiconductor transistor comprising a first floating semiconductor region of the first conductivity type located laterally spaced to an anode/drain region and a second floating semiconductor region of the second conductivity type located laterally adjacent the first floating semiconductor region, and a floating electrode placed above and in direct contact to the first and second floating semiconductor regions.
    Type: Application
    Filed: July 2, 2013
    Publication date: January 8, 2015
    Inventors: Vasantha PATHIRANA, Nishad UDUGAMPOLA, Tanya TRAJKOVIC
  • Patent number: 8928032
    Abstract: A method includes growing an epitaxy semiconductor layer over a semiconductor substrate. The epitaxy semiconductor layer is of a first conductivity type. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is formed at a front surface of the epitaxy semiconductor layer. After the LIGBT is formed, a backside thinning is performed to remove the semiconductor substrate. An implantation is performed from a backside of the epitaxy semiconductor layer to form a heavily doped semiconductor layer. The heavily doped semiconductor layer is of a second conductivity type opposite the first conductivity type.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhy-Jyi Sze, Biay-Cheng Hseih, Shou-Gwo Wuu
  • Patent number: 8896021
    Abstract: An integrated circuit device includes a semiconductor substrate and a first transistor and a second transistor constructed in the semiconductor substrate. The first transistor has a first operating voltage higher than a second operating voltage of a second transistor. The first transistor includes a first drain structure, a first source structure, an isolation structure and a first gate structure. The first source structure includes a high voltage first-polarity well region, a first-polarity body region, a heavily doped first-polarity region, a second-polarity grade region and a heavily doped second-polarity region. The heavily doped second-polarity region is surrounded by the second-polarity grade region. The second-polarity grade region is surrounded by the first-polarity body region. The second transistor includes a second drain structure, a second source structure, a second gate structure and a first-polarity drift region.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: November 25, 2014
    Assignee: United Microelectronics Corporation
    Inventors: Chung-I Huang, Pao-An Chang, Ming-Tsung Lee
  • Publication number: 20140339602
    Abstract: In a trench-gate-type insulated gate bipolar transistor, a current will not flow down to a lower portion of a trench, a high electrical field at the lower portion of the trench is suppressed even if a high voltage is applied, such as at a time of turning off, an increase in on-state resistance and a decrease in breakdown resistance and withstand voltage are suppressed. In the semiconductor device, a plurality of trenches is disposed to reach a rear surface of a drift layer, and a collector layer is disposed at a tip end side in an extended direction of the trenches in a surface layer portion of the drift layer. When a gate electrode is applied with a predetermined voltage, a channel region is formed in a portion of the base layer contacting the trenches, and an electric current flows in the predetermined direction along the trenches.
    Type: Application
    Filed: February 18, 2013
    Publication date: November 20, 2014
    Inventors: Yasushi Higuchi, Masakiyo Sumitomo
  • Publication number: 20140327041
    Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer.
    Type: Application
    Filed: July 22, 2014
    Publication date: November 6, 2014
    Inventors: Kazuo SHIMOYAMA, Manabu TAKEI, Haruo NAKAZAWA
  • Publication number: 20140312384
    Abstract: A semiconductor device includes a first base layer of a first conductivity type formed on a semiconductor layer, a second base layer of a second conductivity type formed on a first surface of the first base layer, an emitter layer formed on the second base layer, a collector layer of the second conductivity type formed above the first base layer, and a barrier layer of the first conductivity type formed between the first base layer and the second base layer. The barrier layer has a depth from the first surface that is shallower than a depth of the second base layer from the first surface and a dopant concentration that is higher than a dopant concentration of the first base layer. The semiconductor device further includes an insulating film formed on the second base layer and a gate electrode formed on the insulating film.
    Type: Application
    Filed: February 6, 2014
    Publication date: October 23, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryo WADA, Kaori YOSHIOKA
  • Publication number: 20140299917
    Abstract: A semiconductor device includes a first conductive type semiconductor substrate, a second conductive type active region formed on a top surface side of the semiconductor substrate, a second conductive type inside VLD region formed to contact the active region on the top surface side in a plan view, and a second conductive type well region formed to contact a portion opposite to the portion contacting the active region of the inside VLD region on the top surface side in a plan view. The well region is formed to be deeper than the active region. The inside VLD region has the same depth as that of the active region in the portion contacting the active region, the depth gradually increasing from the active region toward the well region and becoming the same as the depth of the well region in the portion contacting the well region.
    Type: Application
    Filed: January 8, 2014
    Publication date: October 9, 2014
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Atsushi NARAZAKI
  • Patent number: 8853738
    Abstract: A power LDMOS device including a substrate, source and drain regions, gates and trench insulating structures is provided. The substrate has a finger tip area, a finger body area and a palm area. The source regions are in the substrate in the finger body area and further extend to the finger tip area. The neighboring source regions in the finger tip area are connected. The outmost two source regions further extend to the palm area and are connected. The drain regions are in the substrate in the finger body area and further extend to the palm area. The neighboring drain regions in the palm area are connected. The source and drain regions are disposed alternately. A gate is disposed between the neighboring source and drain regions. The trench insulating structures are in the substrate in the palm area and respectively surround ends of the drain regions.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: October 7, 2014
    Assignee: Episil Technologies Inc.
    Inventors: Chung-Yeh Lee, Pei-Hsun Wu, Shiang-Wen Huang
  • Patent number: 8835978
    Abstract: Representative implementations of devices and techniques provide a high-voltage device on a semiconductor substrate. An insulating polymer layer is formed on an opposite surface to the high-voltage device, the insulating polymer layer having a thickness of at least twice that of the semiconductor substrate.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: September 16, 2014
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Eric Graetz
  • Publication number: 20140252410
    Abstract: A power semiconductor module has four power terminals. An IGBT has a collector connected to the first power terminal and an emitter coupled to the third power terminal. An anti-parallel diode is coupled in parallel with the IGBT. A DC-link is connected between the second and fourth power terminals. The DC-link may involve two diodes and two IGBTs, where the IGBTs are connected in a common collector configuration. The first and second power terminals are disposed in a first line along one side of the module, and the third and fourth power terminals are disposed in a second line along the opposite side of the module. Two identical instances of the module can be interconnected together to form a three-level NPC phase leg having low stray inductances, where the phase leg has two parallel DC-links.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: IXYS Corporation
    Inventor: Andreas Laschek-Enders
  • Patent number: 8823051
    Abstract: A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage current away from the vertical parasitic transistor is provided.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: September 2, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jun Cai, Micheal Harley-Stead, Jim G. Holt
  • Patent number: 8809961
    Abstract: An electrostatic discharge (ESD) protection circuit structure includes several diffusion regions and a MOS transistor. The circuit structure includes a first diffusion region of a first type (e.g., P-type or N-type) formed in a first well of the first type, a second diffusion region of the first type formed in the first well of the first type, and a first diffusion region of a second type (e.g., N-type or P-type) formed in a first well of the second type. The first well of the second type is formed in the first well of the first type. The MOS transistor is of the second type and includes a drain formed by a second diffusion region of the second type formed in a second well of the second type bordering the first well of the first type.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Che Tsai, Jam-Wem Lee, Yi-Feng Chang
  • Patent number: 8803191
    Abstract: Methods and systems for lateral switched-emitter thyristors in a single-layer implementation. Lateral operation is advantageously achieved by using an embedded gate. Embedded gate plugs are used to controllably invert a portion of the P-base region, so that the electron population at the portion of the inversion layer which is closest to the anode will provide a virtual emitter, and will provide sufficient gain so that the combination of bipolar devices will go into latchup.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: August 12, 2014
    Assignee: Pakal Technologies LLC
    Inventor: Richard A. Blanchard