Lateral Structure, I.e., Current Flow Parallel To Main Device Surface Patents (Class 257/141)
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Publication number: 20140252410Abstract: A power semiconductor module has four power terminals. An IGBT has a collector connected to the first power terminal and an emitter coupled to the third power terminal. An anti-parallel diode is coupled in parallel with the IGBT. A DC-link is connected between the second and fourth power terminals. The DC-link may involve two diodes and two IGBTs, where the IGBTs are connected in a common collector configuration. The first and second power terminals are disposed in a first line along one side of the module, and the third and fourth power terminals are disposed in a second line along the opposite side of the module. Two identical instances of the module can be interconnected together to form a three-level NPC phase leg having low stray inductances, where the phase leg has two parallel DC-links.Type: ApplicationFiled: March 8, 2013Publication date: September 11, 2014Applicant: IXYS CorporationInventor: Andreas Laschek-Enders
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Patent number: 8823051Abstract: A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage current away from the vertical parasitic transistor is provided.Type: GrantFiled: May 15, 2006Date of Patent: September 2, 2014Assignee: Fairchild Semiconductor CorporationInventors: Jun Cai, Micheal Harley-Stead, Jim G. Holt
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Patent number: 8809961Abstract: An electrostatic discharge (ESD) protection circuit structure includes several diffusion regions and a MOS transistor. The circuit structure includes a first diffusion region of a first type (e.g., P-type or N-type) formed in a first well of the first type, a second diffusion region of the first type formed in the first well of the first type, and a first diffusion region of a second type (e.g., N-type or P-type) formed in a first well of the second type. The first well of the second type is formed in the first well of the first type. The MOS transistor is of the second type and includes a drain formed by a second diffusion region of the second type formed in a second well of the second type bordering the first well of the first type.Type: GrantFiled: October 17, 2013Date of Patent: August 19, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Che Tsai, Jam-Wem Lee, Yi-Feng Chang
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Patent number: 8803191Abstract: Methods and systems for lateral switched-emitter thyristors in a single-layer implementation. Lateral operation is advantageously achieved by using an embedded gate. Embedded gate plugs are used to controllably invert a portion of the P-base region, so that the electron population at the portion of the inversion layer which is closest to the anode will provide a virtual emitter, and will provide sufficient gain so that the combination of bipolar devices will go into latchup.Type: GrantFiled: October 15, 2012Date of Patent: August 12, 2014Assignee: Pakal Technologies LLCInventor: Richard A. Blanchard
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Patent number: 8791500Abstract: A semiconductor device having a lateral insulated gate bipolar transistor includes a first conductivity type drift layer, a second conductivity type collector region formed in a surface portion of the drift layer, a second conductivity type channel layer formed in the surface portion of the drift layer, a first conductivity type emitter region formed in a surface portion of the channel layer, and a hole stopper region formed in the drift layer and located between the collector region and the emitter region. Holes are injected from the collector region into the drift layer and flow toward the emitter region through a hole path. The hole stopper region blocks a flow of the holes and narrows the hole path to concentrate the holes.Type: GrantFiled: December 19, 2012Date of Patent: July 29, 2014Assignee: DENSO CORPORATIONInventors: Youichi Ashida, Shigeki Takahashi
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Patent number: 8791511Abstract: A semiconductor device is disclosed which has a high voltage isolation structure that is a RESURF structure, wherein it is possible to reduce a displacement current generated by dV/dt noise, and a method of manufacturing the semiconductor device. It is possible to increase a lateral resistance without changing the total amount of electric charges in the uppermost surface p-type diffusion layer by using an uppermost surface p-type diffusion layer configuring a double-RESURF structure being formed so that high concentration regions with a deep diffusion depth and low concentration regions with a shallow diffusion depth are alternately arranged adjacent to each other. As a result, it is possible to reduce a displacement current generated by dV/dt noise.Type: GrantFiled: May 15, 2013Date of Patent: July 29, 2014Assignee: Fuji Electric Co., Ltd.Inventor: Akihiro Jonishi
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Patent number: 8785969Abstract: A reduced surface field (RESURF) structure and a lateral diffused metal oxide semiconductor (LDMOS) device including the same are provided. The RESURF structure includes a substrate of a first conductivity type, a deep well region of a second conductivity type, an isolation structure, at least one trench insulating structure, and at least one doped region of the first conductivity type. The deep well region is disposed in the substrate. The isolation structure is disposed on the substrate. The trench insulating structure is disposed in the deep well region below the isolation structure. The doped region is disposed in the deep well region and surrounds a sidewall and a bottom of the trench insulating structure.Type: GrantFiled: June 27, 2011Date of Patent: July 22, 2014Assignee: Episil Technologies Inc.Inventors: Chung-Yeh Lee, Pei-Hsun Wu, Shiang-Wen Huang
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Patent number: 8786016Abstract: A semiconductor device may include a semiconductor substrate, a first conductive type well and a second conductive type drift region in the semiconductor substrate, the drift region including a first drift doping region and a second drift doping region, the second drift doping region vertically overlapping the well, and a first conductive type body region in the well, the body region being in contact with a side of the first drift doping region. The first drift doping region and the second doping region may include a first conductive type dopant and a second conductive type dopant, and an average density of the first conductive type dopant in the first drift doping region may be less than an average density of the first conductive type dopant in the second drift doping region.Type: GrantFiled: June 3, 2013Date of Patent: July 22, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Jae-June Jang
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Publication number: 20140183596Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a first well region, a gate structure, a second well region, a second well region, a second conductive region, and a deep well region. The first well region contains first type conducting carriers. The second well region is disposed within the first well region, and contains second type conducting carriers. The first conductive region is disposed on the surface of the first well region, and contains the second type conducting carriers. The deep well region is disposed under the second well region and the first conductive region, and contacted with the second well region. The deep well region contains the second type conducting carriers.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Chang-Tzu WANG, Yu-Chun CHEN, Tien-Hao TANG
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Publication number: 20140159110Abstract: A semiconductor device and an operating method for the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region, a fourth doped region and a first gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The first doped region is surrounded by the second doped region. The third doped region has the first type conductivity. The fourth doped region has the second type conductivity. The first gate structure is on the second doped region. The third doped region and the fourth doped region are in the second doped region and the first doped region on opposing sides of the first gate structure respectively.Type: ApplicationFiled: December 11, 2012Publication date: June 12, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ying-Chieh Tsai, Wing-Chor Chan, Jeng Gong
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Patent number: 8735937Abstract: A device includes a dielectric layer, and a heavily doped semiconductor layer over the dielectric layer. The heavily doped semiconductor layer is of a first conductivity type. A semiconductor region is over the heavily doped semiconductor layer, wherein the semiconductor region is of a second conductivity type opposite the first conductivity type. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is disposed at a surface of the semiconductor region.Type: GrantFiled: August 31, 2012Date of Patent: May 27, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhy-Jyi Sze, Biay-Cheng Hseih, Shou-Gwo Wuu
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Publication number: 20140097466Abstract: A semiconductor device includes a p-type collector region, a drift region arranged on the collector region, a base region arranged on the drift region, an emitter region arranged on the base region, a gate oxide film arranged on the bottom surface and side surface of a trench which penetrates the emitter region and the base region, and a gate electrode embedded in the inside of the trench so as to be opposed to the base region while interposing the gate oxide film therebetween, wherein the position of the lower surface of the base region is shallower in the region brought into contact with the gate oxide film than in the region spaced apart from the gate oxide film.Type: ApplicationFiled: September 26, 2013Publication date: April 10, 2014Applicant: Sanken Electric Co., Ltd.Inventor: Katsuyuki TORII
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Patent number: 8692290Abstract: Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer.Type: GrantFiled: September 7, 2011Date of Patent: April 8, 2014Assignee: International Business Machines CorporationInventors: Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Alain Loiseau
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Publication number: 20140077262Abstract: The invention relates to a semiconductor component comprising a semiconductor body, an insulation on the semiconductor body and a cell array arranged at least partly within the semiconductor body. The cell array has at least one p-n junction and at least one contact connection. The insulation is bounded in lateral direction of the semiconductor body by a circumferential diffusion barrier.Type: ApplicationFiled: September 20, 2013Publication date: March 20, 2014Applicant: Infineon Technologies AGInventors: Markus Zundel, Gabriela Brase, Peter Nelle, Guenther Schindler
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Patent number: 8674403Abstract: A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region.Type: GrantFiled: December 4, 2012Date of Patent: March 18, 2014Assignee: MaxPower Semiconductor, Inc.Inventors: Mohamed N. Darwish, Amit Paul
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Publication number: 20140070271Abstract: A lateral insulated gate bipolar transistor includes a semiconductor substrate including a drift layer, a collector region, a channel layer, an emitter region, a gate insulating layer, a gate electrode, a collector electrode, an emitter electrode, and a barrier layer. The barrier layer is disposed along either side of the collector region and is located to a depth deeper than a bottom of the channel layer. The barrier layer has an impurity concentration that is higher than an impurity concentration of the drift layer. The barrier layer has a first end close to the collector region and a second end far from the collector region. The first end is located between the channel layer and the collector region, and the second end is located on the bottom of the channel layer.Type: ApplicationFiled: November 12, 2013Publication date: March 13, 2014Applicant: DENSO CORPORATIONInventors: Shigeki TAKAHASHI, Norihito TOKURA, Satoshi SHIRAKI, Youichi ASHIDA, Akio NAKAGAWA
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Publication number: 20140061721Abstract: An improved MOS device is provided whereby the p-top layer is defined by a series of discretely placed p type top diffusion regions. The invention also provides methods for fabricating the MOS device of the invention.Type: ApplicationFiled: August 28, 2012Publication date: March 6, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ching-Lin Chan, Shyi-Yuan Wu, Cheng-Chi Lin, Shih-Chin Lien
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Patent number: 8659104Abstract: A field-effect magnetic sensor facilitates highly-sensitive magnetic field detection. In accordance with one or more example embodiments, current flow respectively between first and second source/drain terminals and a third source/drain terminal is controlled using inversion layers in separate channel regions for each of the first and second terminals. In response to a magnetic field, a greater amount of current is passed between the third source/drain terminal and one of the first and second source/drain terminals, relative to an amount of current passed between the third source/drain terminal and the other one of the first and second source/drain terminals.Type: GrantFiled: December 21, 2010Date of Patent: February 25, 2014Assignee: NXP B.V.Inventors: Gilberto Curatola, Victor Zieren, Anco Heringa
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Patent number: 8637924Abstract: A transistor includes a trench formed in a semiconductor body, the trench having sidewalls and a bottom. The transistor further includes a first semiconductor material disposed in the trench adjacent the sidewalls and a second semiconductor material disposed in the trench and spaced apart from the sidewalls by the first semiconductor material. The second semiconductor material has a different band gap than the first semiconductor material. The transistor also includes a gate material disposed in the trench and spaced apart from the first semiconductor material by the second semiconductor material. The gate material provides a gate of the transistor. Source and drain regions are arranged in the trench with a channel interposed between the source and drain regions in the first or second semiconductor material so that the channel has a lateral current flow direction along the sidewalls of the trench.Type: GrantFiled: June 29, 2011Date of Patent: January 28, 2014Assignee: Infineon Technologies Austria AGInventors: Franz Hirler, Andreas Peter Meiser
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Publication number: 20130320397Abstract: A device includes a dielectric layer, and a heavily doped semiconductor layer over the dielectric layer. The heavily doped semiconductor layer is of a first conductivity type. A semiconductor region is over the heavily doped semiconductor layer, wherein the semiconductor region is of a second conductivity type opposite the first conductivity type. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is disposed at a surface of the semiconductor region.Type: ApplicationFiled: August 31, 2012Publication date: December 5, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jhy-Jyi Sze, Biay-Cheng Hseih, Shou-Gwo Wuu
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Patent number: 8598624Abstract: A hybrid IGBT device having a VIGBT and LDMOS structures comprises at least a drain trenched contact filled with a conductive plug penetrating through an epitaxial layer, and extending into a substrate; a vertical drain region surrounding at least sidewalls of the drain trenched contact, extending from top surface of the epitaxial layer to the substrate, wherein the vertical drain region having a higher doping concentration than the epitaxial layer.Type: GrantFiled: August 21, 2012Date of Patent: December 3, 2013Assignee: Force Mos Technology Co., Ltd.Inventor: Fu-Yuan Hsieh
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Patent number: 8587071Abstract: An ESD protection circuit includes a MOS transistor of a first type, a MOS transistor of a second type, an I/O pad, and first, second, and third guard rings of the first, second, and first types, respectively. The MOS transistor of the first type has a source coupled to a first node having a first voltage, and a drain coupled to a second node. The MOS transistor of the second type has a drain coupled to the second node, and a source coupled to a third node having a second voltage lower than the first voltage. The I/O pad is coupled to the second node. The first, second, and third guard rings are positioned around the MOS transistor of the second type.Type: GrantFiled: April 23, 2012Date of Patent: November 19, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Che Tsai, Jam-Wem Lee, Yi-Feng Chang
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Publication number: 20130299871Abstract: Representative implementations of devices and techniques provide a high-voltage device on a semiconductor substrate. An insulating polymer layer is formed on an opposite surface to the high-voltage device, the insulating polymer layer having a thickness of at least twice that of the semiconductor substrate.Type: ApplicationFiled: May 14, 2012Publication date: November 14, 2013Inventors: Anton MAUDER, Eric GRAETZ
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Patent number: 8581339Abstract: A bipolar junction transistor and a manufacturing method for the same are provided. The bipolar junction transistor includes a well region, an emitter electrode, a base electrode, a collector electrode, and a conductive layer. The emitter electrode, the base electrode and the collector electrode are separated from each other by the well region. The conductive layer is on the well region between the base electrode and the collector electrode.Type: GrantFiled: August 8, 2011Date of Patent: November 12, 2013Assignee: Macronix International Co., Ltd.Inventors: Chin-Wei Chang, Ching-Lin Chan, Chin-Shien Lu, Ming-Tung Lee, Shuo-Lun Tu
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Patent number: 8569843Abstract: A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.Type: GrantFiled: November 29, 2012Date of Patent: October 29, 2013Assignee: Panasonic CorporationInventors: Manabu Yanagihara, Kazushi Nakazawa, Tatsuo Morita, Yasuhiro Uemoto
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Patent number: 8552469Abstract: There is a problem that a reverse off-leak current becomes too large in a Schottky barrier diode. A semiconductor device of the present invention includes P-type first and second anode diffusion layers formed in an N-type epitaxial layer, N-type cathode diffusion layers formed in the epitaxial layer, a P-type third anode diffusion layer formed in the epitaxial layer so as to surround the first and second anode diffusion layers and to extend toward the cathode diffusion layers, and a Schottky barrier metal layer formed on the first and second anode diffusion layers.Type: GrantFiled: September 27, 2007Date of Patent: October 8, 2013Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventors: Shuichi Kikuchi, Shigeaki Okawa, Kiyofumi Nakaya, Shuji Tanaka
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Patent number: 8546899Abstract: A light receiving element includes a waveguide that includes a waveguide core, a multi-mode interference waveguide that has a width larger than a width of the waveguide, the multi-mode interference waveguide receiving a first light from the waveguide core at a first end, and a photodetection portion that includes a first semiconductor layer and an absorption layer disposed on the first semiconductor layer, the first semiconductor layer including at least one layer and receiving a second light from the multi-mode interference waveguide at a second end, the absorption layer being disposed above the first semiconductor layer and absorbing the second light. A distance from the first end of the multi-mode interference waveguide to the second end of the photodetection portion is longer than 70% of a first length and shorter than 100% of the first length, the first length being a length where self-imaging occurs in the multi-mode interference waveguide.Type: GrantFiled: February 21, 2012Date of Patent: October 1, 2013Assignee: Fujitsu LimitedInventor: Kazumasa Takabayashi
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Patent number: 8487343Abstract: A horizontal-type IGBT having a large current density, which is formed on a SOI substrate, has an emitter region, which is made up with two (2) or more of base-layers of a second conductivity-type on an oxide film groove, wherein the base-layers of the second conductivity-type in the emitter region are covered with a layer of a first conductivity-type, being high in the conductivity than a drift layer, and length of a gate electrode on the oxide film groove is reduced than the length of the gate electrode on the collector, and further the high-density layer of the first conductivity-type is formed below the base layer of the second conductivity-type on the collector, thereby achieving the high density of the layer of the first conductivity-type while maintaining an endurable voltage, and an increase of the current density.Type: GrantFiled: June 29, 2010Date of Patent: July 16, 2013Assignee: Hitachi, Ltd.Inventors: Shinji Shirakawa, Junichi Sakano, Kenji Hara
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Publication number: 20130175576Abstract: Methods and systems for lateral switched-emitter thyristors in a single-layer implementation. Lateral operation is advantageously achieved by using an embedded gate. Embedded gate plugs are used to controllably invert a portion of the P-base region, so that the electron population at the portion of the inversion layer which is closest to the anode will provide a virtual emitter, and will provide sufficient gain so that the combination of bipolar devices will go into latchup.Type: ApplicationFiled: October 15, 2012Publication date: July 11, 2013Applicant: PAKAL TECHNOLOGIES, LLCInventor: Pakal Technologies, LLC
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Patent number: 8482031Abstract: This invention generally relates to lateral insulated gate bipolar transistors (LIGBTs), for example in integrated circuits, methods of increasing switching speed of an LIGBT, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT, and methods of fabricating an LIGBT. In particular, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT comprises selecting a current gain ?v for a vertical transistor of a parasitic thyristor of the LIGBT such that in at least one predetermined mode of operation of the LIGBT ?v<1??p where ?p is a current gain of a parasitic bipolar transistor having a base-emitter junction formed by a Schottky contact between the a semiconductor surface and a metal enriched epoxy die attach.Type: GrantFiled: December 29, 2009Date of Patent: July 9, 2013Assignee: Cambridge Semiconductor LimitedInventors: Florin Udrea, Vasantha Pathirana, Tanya Trajkovic, Nishad Udugampola
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Publication number: 20130161689Abstract: A high voltage laterally diffused metal-oxide-semiconductor (HV LDMOS) device, particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate having at least one highly doped buried portion, a first doped well grown over the substrate, a gate structure formed on the first well, a source and a drain formed on either side of the gate structure, and a second doped well having a U-shaped cross section formed in the first well. A portion of the drain is formed over the first well outside of the second well.Type: ApplicationFiled: November 9, 2012Publication date: June 27, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Taiwan Semiconductor Manufacturing Company, L
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Patent number: 8426939Abstract: The present invention provides a semiconductor device including: a base substrate; a first semiconductor layer which is disposed on the base substrate and has a front surface and a rear surface opposite to the front surface; first ohmic electrodes disposed on the front surface of the first semiconductor layer; a second ohmic electrode disposed on the rear surface of the first semiconductor layer; a second semiconductor layer interposed between the first semiconductor layer and the first ohmic electrodes; and a Schottky electrode part which covers the first ohmic electrodes on the front surface of the first semiconductor layer.Type: GrantFiled: January 8, 2010Date of Patent: April 23, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Woo Chul Jeon, Jung Hee Lee, Young Hwan Park, Ki Yeol Park
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Patent number: 8415712Abstract: This invention generally relates to LIGBTs, ICs comprising an LIGBT and methods of forming an LIGBT, and more particularly to an LIGBT comprising a substrate region of first conductivity type and peak dopant concentration less than about 1×1017/cm3; a lateral drift region of a second, opposite conductivity type adjacent the substrate region and electrically coupled to said substrate region; a charge injection region of the first conductivity type to inject charge toward said lateral drift region; a gate to control flow of said charge in said lateral drift region; metal enriched adhesive below said substrate region; and an intermediate layer below said substrate region to substantially suppress charge injection into said substrate region from said metal enriched adhesive.Type: GrantFiled: December 29, 2009Date of Patent: April 9, 2013Assignee: Cambridge Semiconductor LimitedInventors: Florin Udrea, Vasantha Pathirana, Tanya Trajkovic, Nishad Udugampola
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Patent number: 8415746Abstract: In a lateral bipolar transistor including an emitter, a base and a collector which are formed in a semiconductor thin film formed on an insulating substrate, the semiconductor thin film is a semiconductor thin film which is crystallized in a predetermined direction. In addition, in a MOS-bipolar hybrid transistor formed in a semiconductor thin film formed on an insulating substrate, the semiconductor thin film is a semiconductor thin film which is crystallized in a predetermined direction.Type: GrantFiled: May 31, 2011Date of Patent: April 9, 2013Assignee: Sharp Kabushiki KaishaInventor: Genshiro Kawachi
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Patent number: 8390070Abstract: The ESD protection device includes a substrate, a well, a first doped region and a second doped region. The substrate has a first conductive type, and the substrate is electrically connected to a first power node. The well has a second conductive type, and is disposed in the substrate. The first doped region has the first conductive type, and is disposed in the well. The first doped region and the well are electrically connected to a second power node. The second doped region has the second conductive type, and is disposed in the substrate. The second doped region is in a floating state.Type: GrantFiled: April 6, 2011Date of Patent: March 5, 2013Assignee: Nanya Technology Corp.Inventor: Wei-Fan Chen
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Patent number: 8390068Abstract: A silicon control rectifier and an electrostatic discharge protection device of an integrated circuit including the silicon control rectifier. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.Type: GrantFiled: January 30, 2012Date of Patent: March 5, 2013Assignee: International Business Machines CorporationInventors: Robert J. Gauthier, Jr., Junjun Li, Souvick Mitra, Mahmoud A. Mousa, Christopher Stephen Putnam
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Patent number: 8373245Abstract: Disclosed is a semiconductor device including: a base substrate; a semiconductor layer disposed on the base substrate; an ohmic electrode part which has ohmic electrode lines disposed in a first direction, on the semiconductor layer; and a Schottky electrode part which is disposed to be spaced apart from the ohmic electrode lines on the semiconductor layer and includes Schottky electrode lines disposed in the first direction, wherein the Schottky electrode lines and the ohmic electrode lines are alternately disposed in parallel, and the ohmic electrode part further includes first ohmic electrodes covered by the Schottky electrode lines on the semiconductor layer.Type: GrantFiled: January 8, 2010Date of Patent: February 12, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Woo Chul Jeon, Jung Hee Lee, Young Hwan Park, Ki Yeol Park
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Patent number: 8354691Abstract: A N-channel lateral insulated-gate bipolar transistor includes a semiconductor substrate, a drift layer, a collector region, a channel layer, an emitter region, a gate insulation film, a gate electrode, a collector electrode, an emitter electrode. The collector region includes a high impurity concentration region having a high impurity concentration and a low impurity concentration region having a lower impurity concentration than the high impurity concentration region. The collector electrode is in ohmic contact with the high impurity concentration region and in schottky contact with the low impurity concentration region.Type: GrantFiled: September 7, 2011Date of Patent: January 15, 2013Assignee: DENSO CORPORATIONInventors: Norihito Tokura, Shigeki Takahashi, Youichi Ashida, Akio Nakagawa
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Patent number: 8344463Abstract: A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.Type: GrantFiled: July 10, 2009Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventors: Manabu Yanagihara, Kazushi Nakazawa, Tatsuo Morita, Yasuhiro Uemoto
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Patent number: 8330186Abstract: A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region.Type: GrantFiled: April 30, 2009Date of Patent: December 11, 2012Assignee: MaxPower Semiconductor, Inc.Inventors: Mohamed N. Darwish, Amit Paul
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Patent number: 8319309Abstract: The present invention provides a semiconductor device including: a base substrate; a semiconductor layer which is disposed on the base substrate and has a 2-Dimensional Electron Gas (2DEG) formed therewithin; a first ohmic electrode disposed on a central region of the semiconductor layer; a second ohmic electrode which is formed on the edge regions of the semiconductor layer in such a manner to be disposed to be spaced apart from the first ohmic electrodes, and have a ring shape surrounding the first ohmic electrode; and a Schottky electrode part which is formed on the central region to cover the first ohmic electrode and is formed to be spaced apart from the second ohmic electrode.Type: GrantFiled: January 8, 2010Date of Patent: November 27, 2012Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Woo Chul Jeon, Jung Hee Lee, Young Hwan Park, Ki Yeol Park
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Patent number: 8283696Abstract: An integrated low leakage diode suitable for operation in a power integrated circuit has a structure similar to a lateral power MOSFET, but with the current flowing through the diode in the opposite direction to a conventional power MOSFET. The anode is connected to the gate and the comparable MOSFET source region which has highly doped regions of both conductivity types connected to the channel region to thereby create a lateral bipolar transistor having its base in the channel region. A second lateral bipolar transistor is formed in the cathode region. As a result, substantially all of the diode current flows at the upper surface of the diode thereby minimizing the substrate leakage current. A deep highly doped region in contact with the layers forming the emitter and the base of the vertical parasitic bipolar transistor inhibits the ability of the vertical parasitic transistor to fully turn on.Type: GrantFiled: November 2, 2010Date of Patent: October 9, 2012Assignee: Fairchild Semiconductor CorporationInventor: Jun Cai
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Patent number: 8278683Abstract: Current density in an insulated gate bipolar transistor (L-IGBT) may be increased by adding a second gate, and the corresponding MOS transistors, to the source area, which increases the base current compared to a L-IGBT with a single MOS gate. The current density may be further increased by extending the base of the bipolar transistor in the L-IGBT vertically to the bottom surface of the silicon on insulator (SOI) film in which the L-IGBT is fabricated. Adding a buffer diffused region around the sinks in the source improves the base current spatial uniformity, which improves the safe operating area (SOA) of the L-IGBT. A L-IGBT of either polarity may be formed with the inventive configurations. A method of forming the inventive L-IGBT is also disclosed.Type: GrantFiled: August 6, 2009Date of Patent: October 2, 2012Assignee: Texas Instruments IncorporatedInventors: Hideaki Kawahara, Philip Leland Hower
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Patent number: 8253163Abstract: A high voltage semiconductor device includes a semiconductor substrate, a p type base region in a first main surface, an n+ type emitter region in the p type base region, an n+ type cathode region adjacent to an end surface of the semiconductor substrate and not penetrating the semiconductor substrate, a p+ type collector region in a second main surface, a first main electrode, a second main electrode, a third main electrode, and a connection portion connecting the second main electrode and the third main electrode. A resistance between the p type base region and the n+ type cathode region is greater than a resistance between the p type base region and the p+ type collector region. In the high voltage semiconductor device in which an IGBT and a free wheel diode are formed in a single semiconductor substrate, occurrence of a snap-back phenomenon is suppressed.Type: GrantFiled: October 7, 2010Date of Patent: August 28, 2012Assignee: Mitsubishi Electric CorporationInventors: Shigeru Kusunoki, Junji Yahiro, Yoshihiko Hirota
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Patent number: 8253164Abstract: A lateral insulated gate bipolar transistor (LIGBT) includes a drain-anode adjoining trenched contact penetrating through an insulating layer and extending into an epitaxial layer, directly contacting to a drain region and an anode region, and the drain region vertically contacting to the anode region along sidewall of the drain-anode adjoining trenched contact. The LIGBT further comprises a breakdown voltage enhancement doping region wrapping around the anode region. The LIGBTs in accordance with the invention offer the advantages of high breakdown voltage and low on-resistance as well as high switching speed.Type: GrantFiled: December 23, 2010Date of Patent: August 28, 2012Assignee: Force MOS Technology Co., Ltd.Inventor: Fu-Yuan Hsieh
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Patent number: 8242537Abstract: An IGBT with a fast reverse recovery time rectifier includes an N-type drift epitaxial layer, a gate, a gate insulating layer, a P-type doped base region, an N-type doped source region, a P-type doped contact region, and a P-type lightly doped region. The P-type doped base region is disposed in the N-type drift epitaxial layer, and the P-type doped contact region is disposed in the N-type drift epitaxial layer. The P-type lightly doped region is disposed between the P-type contact doped region and the N-type drift epitaxial layer, and is in contact with the N-type drift epitaxial layer.Type: GrantFiled: November 10, 2009Date of Patent: August 14, 2012Assignee: Anpec Electronics CorporationInventors: Wei-Chieh Lin, Jen-Hao Yeh, Ho-Tai Chen
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Publication number: 20120161201Abstract: A lateral insulated gate bipolar transistor (LIGBT) includes a drain-anode adjoining trenched contact penetrating through an insulating layer and extending into an epitaxial layer, directly contacting to a drain region and an anode region, and the drain region vertically contacting to the anode region along sidewall of the drain-anode adjoining trenched contact. The LIGBT further comprises a breakdown voltage enhancement doping region wrapping around the anode region. The LIGBTs in accordance with the invention offer the advantages of high breakdown voltage and low on-resistance as well as high switching speed.Type: ApplicationFiled: December 23, 2010Publication date: June 28, 2012Applicant: FORCE MOS TECHNOLOGY CO., LTD.Inventor: Fu-Yuan HSIEH
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Patent number: 8188511Abstract: A semiconductor device and a method of forming the semiconductor device include a substrate and an n drift layer on the substrate with an insulator film placed between them. A trench is provided in a section between a p base region and an n buffer layer on the surface layer of the n drift layer. Moreover, the distance between the bottom of the trench and the insulator film on the substrate is 1 ?m or more and 75% or less than the thickness of the n drift layer. This reduces the ON-state Voltage Drop and enhances the device breakdown voltage and the latch up current in a lateral IGBT or a lateral MOSFET.Type: GrantFiled: June 1, 2008Date of Patent: May 29, 2012Assignee: Fuji Electric Co., Ltd.Inventor: Noriyuki Iwamuro
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Patent number: 8164111Abstract: A high voltage semiconductor device includes a semiconductor substrate, a p type base region in a first main surface, an n+ type emitter region in the p type base region, an n+ type cathode region adjacent to an end surface of the semiconductor substrate and not penetrating the semiconductor substrate, a p+ type collector region in a second main surface, a first main electrode, a second main electrode, a third main electrode, and a connection portion connecting the second main electrode and the third main electrode. A resistance between the p type base region and the n+ type cathode region is greater than a resistance between the p type base region and the p+ type collector region. In the high voltage semiconductor device in which an IGBT and a free wheel diode are formed in a single semiconductor substrate, occurrence of a snap-back phenomenon is suppressed.Type: GrantFiled: October 7, 2010Date of Patent: April 24, 2012Assignee: Mitsubishi Electric CorporationInventors: Shigeru Kusunoki, Junji Yahiro, Yoshihiko Hirota
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Patent number: 8148758Abstract: A high-voltage field-effect device contains an extended drain or “drift” region including an embedded stack of JFET regions separated by intervening layers of the drift region. Each of the JFET regions is filled with material of an opposite conductivity type to that of the drift region, and the floor and ceiling of each JFET region is lined with an oxide layer. When the device is blocking a voltage in the off condition, the semiconductor material inside the JFET regions and in the drift region that separates the JFET regions is depleted. This improves the voltage-blocking ability of the device while conserving chip area. The oxide layer prevents dopant from the JFET regions from diffusing into the drift region.Type: GrantFiled: December 16, 2010Date of Patent: April 3, 2012Assignee: Alpha and Omega Semiconductor Inc.Inventor: Hamza Yilmaz