Abstract: The invention relates to a semiconductor component having a first semiconductor zone of a first conduction type, a second semiconductor zone of a second conduction type and a drift zone arranged between the first and second semiconductor zones, which drift zone has at least two semiconductor zones doped complementarily to one another, the degree of compensation varying at least in a section of the drift zone in a direction perpendicular to a current flow direction running between the first and second semiconductor zones.

Abstract: A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage current away from the vertical parasitic transistor is provided.

Abstract: One aspect of the present subject matter relates to a memory cell, or more specifically, to a scalable GLTRAM cell that provides DRAM-like density and SRAM-like performance. According to various embodiments, the memory cell includes an access transistor and a gated, lateral thyristor integrally formed above the access transistor. The access transistor has a drain region, a raised source region, and a gate. The thyristor has a first end that is formed with the raised source region of the access transistor. In various embodiments, the lateral thyristor is fabricated using a metal-induced lateral crystallization technique (MILC) adopted for thin-film-transistor (TFT) technology. In various embodiments, the stacked lateral thyristor is integrated by raising the source region of the access transistor using a selective epitaxy process for raised source-drain technology. Other aspects are provided herein.

Abstract: A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure over the SiC substrate.

Abstract: A vertical or lateral semiconductor component derives a signal from a high load voltage. This signal can be used directly for driving the semiconductor component or, alternatively, a control device.

Abstract: To protect against electrostatic discharges in monolithic integrated circuits in CMOS technology, a lateral thyristor structure is presented which has a much lower firing voltage compared to conventional thyristor structures.

Abstract: A method of manufacturing a liquid crystal display device is intended to decrease the number of manufacturing steps. The liquid crystal display device is arranged so that in each pixel area provided on a liquid-crystal-side surface of one of a pair of substrates disposed to oppose each other with a liquid crystal interposed therebetween, a signal from a drain line is applied to a pixel electrode via a drain electrode and a source electrode which are formed in a layer overlying a semiconductor layer of a thin film transistor, by the supply of a scanning signal from a gate electrode which is positioned as an underlying layer with respect to the semiconductor layer.

Abstract: A semiconductor substrate includes a first principal plane and a second principal plane opposite this first principal plane. A first semiconductor region is formed on the first principal plane of the semiconductor substrate. Second and third semiconductor regions are formed separately from each other on the first semiconductor region. A gate electrode is formed, via a gate insulator, on the first semiconductor region between the second semiconductor region and the third semiconductor region. An electric conductor is formed up to the semiconductor substrate from the second semiconductor region and electrically connects the second semiconductor region with the semiconductor substrate. A first main electrode is formed on the second principal plane of the semiconductor substrate and is electrically connected to the semiconductor substrate. A second main electrode is formed on the first semiconductor region via insulators and is electrically connected to the third semiconductor region.

Abstract: A reverse-blocking power semiconductor component includes a drift path subdivided into a source-side area and a drain-side area by a region with opposite doping. Provided above this region is a gate. Alternatively, the body zone of the one conduction type is subdivided into a source-side part and a drain-side part by a region of the other conduction type. This region acts as an electron collector. The reverse-blocking power semiconductor component can be incorporated in compensation components, and power transistors. Methods for producing power semiconductor components are also provided.

Abstract: A bidirectional semiconductor component having two symmetrical MOS transistor structures integrated laterally in a substrate and connected antiserially, their drain terminals being connected to one another. A zone having the same type of conductivity as the drain region yet a higher doping than that of the drain region is situated upstream from a pn junction of one of the MOS transistors in a junction area with the drain region.

Abstract: A SJ-LDMOST device offers significantly improved on-state, off-state, and switching characteristics of lateral power devices for power integrated circuits applications. The device is fabricated on an insulator substrate. The proposed structure achieves charge compensation in the drift region by terminating the bottom of the SJ structure by a dielectric hence eliminating the undesirable vertical electric field component and preventing any substrate-assisted-depletion. The device structural arrangement thereby achieve a uniform distribution of the electric field thus maximizing the BV for a given drift region length.

Abstract: A MOS power transistor formed in an epitaxial layer of a first conductivity type, the MOS power transistor being formed on the front surface of a heavily-doped substrate of the first conductivity type, including a plurality of alternate drain and source fingers of the second conductivity type separated by a channel, conductive fingers covering each of the source fingers and of the drain fingers, a second metal level connecting all the drain metal fingers and substantially covering the entire source-drain structure. Each source finger includes a heavily-doped area of the first conductivity type in contact with the epitaxial layer and with the corresponding source finger, and the rear surface of the substrate is coated with a source metallization.

Abstract: In an ESD protection device using a LVTSCR-like structure, the holding voltage is increased by placing the p+ emitter outside the drain of the device, thereby retarding the injection of holes from the p+ emitter. The p+ emitter may be implemented in one or more emitter regions formed outside the drain. The drain is split between a n+ drain and a floating n+ region near the gate to avoid excessive avalanche injection and resultant local overheating.

Abstract: An organic light emitting device is provided. The device includes an anode, a cathode, and an emissive layer disposed between the anode and the cathode. The emissive layer includes material having the structure: M is a metal having an atomic weight greater than 40, m is at least 1, n is at least zero, R″ is H or any substituent, X is an ancillary ligand, and A is selected from the group consisting of aryl and heteroaryl rings, and B is an aryl ring. A material including the photoactive ligand of the above material is also provided.

Abstract: A buried channel and a method of fabricating a buried channel in a substrate including depositing a layer of masking material onto a surface of a substrate, etching a groove in the masking layer, etching a channel into the substrate through the groove, and depositing a cover layer over the masking layer and groove such that the covering layer at least substantially closes over the groove.

Abstract: An embedded SCR in conjunction with a Gated-NMOS is created for protecting a chip input or output pad from ESD, by inserting a p+ diffusion and the n-well in the drain side and a part of the drain to forms a low-trigger, high efficiency SCR. The device layout is such that the drain connection is tightly tied together at the p+ diffusion and the n+ drain making that connection very short and, thereby, preventing latch-up. The parasitic SCR is contained entirely within the n+ diffusion (the source of the grounded gate NMOS transistor) at either side of the structure and, therefore, called an embedded SCR. For a 12 volt I/O device each of two n+ drains is placed in its own n-type doped drain (ndd) area straddling halfway the n-well. The structure is repeated as required and a p+ diffusion is implanted at both perimeters and connected to the nearest n+ source and a reference voltage.

Abstract: Described is a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and self-aligned silicide (salicide) fabrication technology. The UMOS gate is located in a p-substrate and is surrounded by an n-well on either side. Adjacent to one side of the UMOS gate, a first n+ diffusion is formed which straddles the first n-well. The n+ diffusion together with a p+ pickup diffused next to it form the cathode of the SCR (thyristor). Adjacent to the other side of the UMOS gate, a second n+ and p+ diffusion are formed in a second n-well. The second n+ and p+ diffusion together with the UMOS gate form the anode of the SCR and the input terminal of the circuit to be protected. The SCR is formed by the first n+ diffusion/n-well (cathode), the p-substrate, the second n-well and the second p+/n+ diffusion (anode).

Abstract: A T-RAM array having a planar cell structure is presented which includes a plurality of T-RAM cells. Each of the plurality of T-RAM cells is fabricated by using doped polysilicon to form a self-aligned diffusion region to create a low-contact resistance p+ diffusion region. A silicided p+ polysilicon wire is preferably used to connect each of the plurality of the T-RAM cells to a reference voltage Vref. A self-aligned junction region is formed between every two wordlines by implanting a n+ implant into a gap between every two wordlines. The self-aligned junction region provides for a reduction in the T-RAM cell size from a cell size of 8F2 for a prior art T-RAM cell to a cell size of less than or equal to 6F2. Preferably, the T-RAM array is built on a semiconductor silicon-on-insulator (SOI) wafer to reduce junction capacitance and improve scalability.

Abstract: When an ESD surge positive against a ground terminal is loaded on the input/output pad, a breakdown current of the n-channel MOS transitor flows via forward-biased diodes consist of a p+ diffusion layer and N well from the input/output pad. As a result, a SCR that comprises a p+ diffusion layer serving as the anodes of the diodes, N well, P well, and n+ diffusion layer serving as the source of the transistor is activated, and then the ESD surge is released to the ground terminal.

Abstract: The holding voltage (the minimum voltage required for operation) of a triac is increased to a value that is greater than a dc bias on to-be-protected nodes. The holding voltage is increased by inserting a voltage drop between each p+ region and a to-be-protected node. As a result, the triac can be utilized to provide ESD protection to power supply pins.

Abstract: An NMOS-trigger silicon controlled rectifier in silicon-on-insulator (SOI-NSCR) SOI-NSCR includes a P-type well and an N-type well. A first P+ doping region and a first N+ doping region are in the N-type well and form the anode of the SOI-NSCR. A second P+ doping region and a second N+ doping region are in the P-type well and form the cathode of the SOI-NSCR. The first P+ doping region, the N-type well, the P-type well and the second N+ doping region form a lateral SCR. A third N+ doping region is across the N-type well and the P-type well. A gate is in the P-type well, and the third N+ doping region, the gate and the second N+ doping region form an NMOS. A dummy gate is in the N-type well for isolating the first P+ doping region and the third N+ doping region. When a voltage is applied to the gate of the NMOS that turns on the NMOS, a forward bias is created from the N-type well to the P-type well that turns on the SOI-NSCR.

Abstract: The transistor includes an emitter region 17 disposed in a first isolating well 11, 150 formed in a semiconductor bulk. An extrinsic collector region 16 is disposed in a second isolating well 3, 150 formed in the semiconductor bulk SB and separated laterally from the first well by a bulk separator area 20. An intrinsic collector region is situated in the bulk separator area 20 in contact with the extrinsic collector region. An intrinsic base region 100 is formed which is thinner laterally than vertically and in contact with the intrinsic collector region and in contact with the emitter region through bearing on a vertical flank of the first isolating well facing a vertical flank of the second isolating well. An extrinsic base region 60 is formed which is substantially perpendicular to the intrinsic base region in the top part of the bulk separator area, and contact terminals C, B, E respectively in contact with the extrinsic collector region, the extrinsic base region, and the emitter region.

Abstract: A lateral high-voltage sidewall transistor configuration includes a low-doped semiconductor substrate of a first conductivity type and a low-doped epitaxial layer of a second conductivity type disposed on the semiconductor substrate. First semiconductor layers of the first conductivity type and second semiconductor layers of the second conductivity type are disposed in an alternating configuration in the epitaxial layer. A source region and a drain region of the second conductivity type extend through the first and second semiconductor layers as far as the semiconductor substrate. A gate electrode includes a gate insulating layer lining a gate trench and includes a conductive material which fills the gate trench. The gate electrode extends through the first and second semiconductor layers as far as the semiconductor substrate and is disposed adjacent to the source region toward the drain region.

Abstract: The invention concerns a semiconductor component with at east one lateral region which is provided to accommodate a lateral electric field strength, whereby the semiconductor body within the body and/or in regions proximal to the surface of the semiconductor body at least over regions thereof has a lateral three-dimensional structure which has vertical recesses in the semiconductor body within which there are electrical conductors which are smaller than in the intervening spaces of the semiconductor body between the recesses, as well as a method for making and of using the semiconductor component.

Abstract: Three diode structures on a metal-oxide-semiconductor (MOS) wafer. Each diode structure is capable of reducing parasitic current through the wafer and hence increasing the power conversion efficiency of a voltage step-up circuit.

Abstract: The holding voltage (the minimum voltage required for operation) of a low-voltage triggering silicon-controlled rectifier (LVTSCR) is increased to a value that is greater than a dc bias on a to-be-protected node. The holding voltage is increased by inserting a voltage drop between the to-be-protected node and the emitter of the pnp transistor of the LVTSCR. As a result, the LVTSCR can be utilized to provide ESD protection to power supply pins.

Abstract: The invention provides a PIN diode having a laterally extended I-region. The invention also provides a method of fabricating the inventive PIN diode compatible with modem RF technologies such as silicon-germanium BiCMOS processes.

Abstract: A semiconductor body (11) has first and second opposed major surfaces (11a and 11b). First and second main regions (13 and 14) meet the second major surface (11b) and a voltage-sustaining zone is provided between the first and second regions (13 and 14). The voltage-sustaining zone has a semiconductor region (11) of one conductivity type forming a rectifying junction (J) with a region (15) of the device such that, when the rectifying junction is reverse-biased in one mode of operation, a depletion region extends in the semiconductor region of the voltage-sustaining zone. A number of conductive regions (22) are isolated from and extend through the semiconductor region (11) in a direction transverse to the first and second major surfaces (11a and 11b) so as to be spaced apart in a direction between first and second main regions.

Abstract: A gate-controlled thyristor in which an IGBT in a first cell and a thyristor in a main cell are connected together in ouch a way that the first cell and the main cell form a lateral FET with a channel of a first conducting type. In an emitter zone of the thyristor, there is a layer embedded that increases the charge carrier recombination in order to reduce the start-up resistance of the gate-controlled thyristor. Trenches, filled with insulated gate electrodes, can be introduced into the lateral FET, so that the FET is a side wall FET.

Abstract: To reduce ON-state resistance with desired withstand voltage secured, a semiconductor device provided with a gate electrode formed on a semiconductor substrate via a gate insulating film, an LP layer (a P-type body region) formed so that the LP layer is adjacent to the gate electrode, an N-type source region and a channel region respectively formed in the LP layer, an N-type drain region formed in a position apart from the LP layer and an LN layer (a drift region) formed so that the LN layer surrounds the drain region is characterized in that a P-type layer ranging to the LP layer is formed under the gate electrode.

Abstract: To protect against electrostatic discharges in monolithic integrated circuits in CMOS technology, a lateral thyristor structure is presented which has a much lower firing voltage compared to conventional thyristor structures.

Abstract: An n-channel type MIS field effect transistor is fabricated on a p-type well defined in a standard p-type silicon substrate, and is expected to respond to a high- frequency signal, wherein a heavily- doped p-type well contact region is formed outside of the p-type well for increasing the substrate resistance, and a capacitor is coupled to the heavily-doped p-type well contact region for increasing the impedance so that the insertion loss is reduced by virtue of the large impedance of the silicon substrate.

Abstract: A thin film transistor for an antistatic circuit includes: wells formed on a silicon substrate; insulating layers for electrical isolation between electrodes formed within the wells; low density impurity diffused regions respectively interposed between the insulating layers; a first high-density impurity diffused region formed within one low-density impurity diffused region; a second high-density impurity diffused region formed within the other low-density impurity diffused region; interlevel insulating layers formed on the insulating layers and the low-density impurity diffused layers; and metal gate electrodes formed on the low-density impurity diffused layers and the interlevel insulating layers; at least one of the first high-density impurity diffused region and the second high-density impurity diffused region being arranged to overlap on active region, inward from outside edges of the active region.

Abstract: A semiconductor device is herein disclosed which comprises a plurality of element regions 50 formed on a first conductive type semiconductor substrate 60, element isolation regions 58 for isolating the element regions from each other, and gate electrodes 54 on parts of the element regions, the element regions being in contact with the element isolation regions at side surfaces 68 of the element regions, wherein in the element region under each gate electrode, the concentration of a first conductive type impurity is high in an element region top surface edge area (in the vicinity of 66), and on the side surfaces of each element region, except the portions under the gate electrode, the concentration of the first conductive type impurity is equal to or lower than that of the first conductive type impurity in the body of the element region.

Abstract: An integrated SCR-LDMOS device (10) having a p+ region (13) in the drain region (12), but otherwise similar to a conventional LDMOS transistor. The device (10) may be implemented as a modification of a non-planar LDMOS (FIGS. 1 and 2). An alternate embodiment, device (30), may be implemented as a modification of a planar LDMOS (FIG. 3). In either case, the added p+ region (13, 37) provides the device (10, 30) with two parasitic bipolar transistors in an SCR configuration (FIGS. 4A and 4B).

Abstract: Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.

Abstract: A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively.

Abstract: An Insulated Gate Bipolar Transistor has a gate in the form of a trench positioned in a p region in a silicon body. The device operates in a thyristor mode having a virtual emitter which is formed during operation by the generation of an inversion layer at the bottom of the trench within the p region. The device is inherently safe and turns off rapidly as removal of a gate signal collapses the emitter. As the trench gate is situated within the p region, it can withstand high voltages when turned off as the reverse electric field is prevented from reaching the trench gate.

Abstract: A semiconductor device includes a p channel MOS transistor with a p.sup.- diffusion region, a p.sup.+ diffusion region and a gate electrode formed on the main surface of an n.sup.- layer on a buried oxide film. The p.sup.- diffusion region includes a plurality of branch-like regions to be connected to a p.sup.+ diffusion region. A source electrode is formed at the p.sup.+ diffusion region. An n.sup.+ diffusion region is formed within the p.sup.+ diffusion region. A drain electrode is connected to the p.sup.+ diffusion region and the n.sup.+ diffusion region. According to this structure, the depletion layer between the source electrode and the drain electrode is expanded. A semiconductor device is achieved that is improved in the breakdown voltage at the time of an off operation, or that is improved in on driving current at the time of an on operation with improved breakdown voltage at the time of an off operation.

Abstract: Silicon carbide power devices include a semiconductor substrate of first conductivity type (e.g., N-type) having a face thereon and a blocking voltage supporting region of first conductivity type therein extending to the face. The voltage supporting region is designed to have a much lower majority carrier conductivity than an underlying and highly conductive "bypass" portion of the semiconductor substrate. This bypass portion of the substrate supports large lateral currents with low on-state voltage drop. First and second semiconductor devices are also provided having respective first and second active regions of first conductivity type therein. These first and second active regions extend on opposing sides of the voltage supporting region and are electrically coupled to the bypass portion of the semiconductor substrate which underlies and extends opposite the voltage supporting region relative to the face of the substrate.

Abstract: In a composite controlled semiconductor device having an insulated gate and a power conversion device using the same, a p type semiconductor region forming no channel is provided in the composite device structure between a plurality of p type semiconductor regions forming a channel and the potential of the p type semiconductor region in an ON state takes a value high enough to inject holes into an n type semiconductor region adjacent to the p type semiconductor region.

Abstract: A high-breakdown-voltage semiconductor device has a first offset layer and a second offset layer the dosage of which is higher than that of the first offset layer. When the gate is in the ON state, the first offset layer functions as a resurf layer. When the gate is in the OFF state, part of the charge in the first offset layer is neutralized by a drain current flowing through an element having a low ON-resistance, however, the second offset layer functions as a resurf layer. When the drain current is ?Acm.sup.-1 !, the amount of charge of electrons is q?C!, and the drift speed of carriers is .upsilon..sub.drift ?cms.sup.-1 !, the dosage n.sub.2 of the second offset layer is given by n.sub.2 .gtoreq.I.sub.D /(q.upsilon..sub.drift)?cms.sup.-2 !.

Abstract: A sub-gate electrode is arranged to face, through a gate insulating film, a surface of a first p-type base layer which is interposed between a first n-type source layer and an n-type drift layer, and a surface of a second p-type base layer which is interposed between a second n-type source layer and the n-type drift layer and faces the first p-type base layer. A main gate electrode is arranged to face, through a gate insulating film, a surface of the second p-type base layer which is interposed between the second n-type source layer and the n-type drift layer and does not face the first p-type base layer. Three n-type MOSFETs are constructed such that one n-type channel is to be formed in the first p-type base layer and two n-type channels are to be formed in the second p-type base layer. The three channels are to be formed, so that the channel width is effectively enlarged and the current density is increased. The second p-type base layer has a length of 10 .mu.m or less in the drifting direction.

Abstract: A lateral insulated gate bipolar transistor has an emitter region that is displaced from a main path for passing carriers from a collector region to a base region through a first semiconductor layer. This arrangement suppresses the operation of a parasitic transistor composed of the emitter region, base region, and first semiconductor layer and prevents a latch-up. The width of the gate electrode of covering the first semiconductor layer serving as a drift region of carriers may be widened to form a carrier accumulation layer in the first semiconductor layer adjacent to the gate electrode. The accumulation layer increases the total number of carriers in the drift region, to reduce a saturation voltage between the collector region and the emitter region. As a result, the lateral insulated gate bipolar transistor operates with a low voltage to reduce power consumption.

Abstract: An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.

Abstract: A dual transistor CMOS inverter can be built wherein a single gate is shared by two MOS transistors but only one transistor can be turned on at a time. A CMOS inverter function is provided. Further, a dual transistor logic function is described incorporating a combination of a lateral bipolar transistor (LBT) and a metal-oxide-semiconductor transistor (MOST). The gate of the MOST is used to turn on and off the base of the LBT. When the base is turned on, the LBT is turned on and off depending on the base voltage. This device has, thus, two inputs and can perform logic functions such as OR or NAND, which would typically require four transistors. The invention solves the problem of device density to perform logic by forming stacked devices with shared electrodes.

Abstract: An LIGBT includes an LDMOST structure in which the drain/anode 9, 13 is provided with a pn junction which injects charge carriers into the drift region 8. To prevent latch-up, the base region 6 of the LDMOST is provided with deep zones 6b of the same conductivity type as the base region which extend locally comparatively far into the drift region. These zones collect charge carriers injected by the anode into the drift region and form a low-ohmic connection to the source contact 11 for these charge carriers. Since these zones are provided locally only, the threshold voltage of the LDMOST is not or at least substantially not influenced by the deep zones. In a modification, a ballast series resistance is provided in the source zone, so that latch-up is counteracted also at high temperatures.

Abstract: A high breakdown voltage semiconductor device. The device includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, an active region formed on the insulating film, drain and base regions formed in a surface portion of the active region, and a source region formed in a surface portion of the base region. First and second gate insulating films are formed on inner surfaces of first and second grooves penetrating the base region so as to come in contact with the source region and reaching the active region, with first and second electrodes being buried in the first and second grooves. Two or more channel regions are formed in a MOS structure constructed by the gate insulating film, the gate electrode, the source region, the base region and the active region.

Abstract: A hybrid schottky injection field effect transistor is provided. A first diffusion region of a second conductivity type and a second diffusion region of a first conductivity type are separately formed at a main surface of a silicon layer. A third diffusion region of a first conductivity type is formed within the first diffusion region. An insulating layer covers part of the second diffusion region and the third diffusion region. A gate electrode is formed on the insulating layer and is situated over the first and third diffusion regions and the silicon layer. A cathode electrode is commonly connected to the third diffusion region and the first diffusion region. An anode electrode comprises a trench filled with electrode material and is formed in the silicon layer along side of the second diffusion area and a gate insulating layer.

Abstract: A bidirectional lateral insulated gate bipolar transistor (IGBT) includes two gate electrodes. The IGBT can conduct current in two directions. The IGBT relies on a RESURF operation to provide high voltage blocking in both directions. The IGBT is symmetrical, having N-type drift region in contact with an oxide layer. A P-type region is provided above the N-type-drift region, having a portion more heavily doped with P-type dopants. The RESURF operation can be provided by a buried oxide layer or by a P substrate or by a horizontal PN junction. The IGBT can be utilized in various power operations, including a matrix switch or a voltage source converter.