With Extended Latchup Current Level (e.g., Gate Turn Off "gto" Device) Patents (Class 257/147)
  • Patent number: 5917203
    Abstract: A lateral gate, vertical drift region transistor including a drain positioned on one surface of a substrate and a doped structure having a buried region therein positioned on the other surface of the substrate. The buried region defining a drift region in the doped structure extending vertically from the substrate and further defining a doped region in communication with the drift region and adjacent the surface of the doped structure. A source positioned on the doped structure in communication with the doped region and an implant region positioned in the doped region adjacent the surface and in communication with the source and buried region. An insulating layer positioned on the doped structure with a metal gate positioned on the insulating layer so as to define an inversion region in the implant region extending laterally adjacent the control terminal and communicating with the drift region and the source.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: June 29, 1999
    Assignee: Motorola, Inc.
    Inventors: Mohit Bhatnagar, Charles E. Weitzel
  • Patent number: 5910664
    Abstract: Emitter-switched transistor structures are described which have only three terminals. A part of the drain current is used to provide the base current of an emitter-switched NPN transistor and to concurrently cause the injection of holes to conductivity-modulate the emitter-switching MOSFET of the NPN transistor. The reduced on-resistance of the emitter-switching MOSFET causes the emitter-switched NPN transistor to inject more electrons, which in turn leads to more hole injection via a positive feedback mechanism, resulting in a low on-state voltage drop for the device. In another embodiment of the invention, a thyristor structure is provided with the anode switched by a high-voltage MOSFET. Yet another embodiment of the invention provides a four terminal bidirectional device with no diffusions required on the backside of the wafer.
    Type: Grant
    Filed: November 5, 1997
    Date of Patent: June 8, 1999
    Assignee: International Rectifier Corporation
    Inventor: Janardhanan S. Ajit
  • Patent number: 5894140
    Abstract: A gate structure including semiconductor regions each having a high impurity-concentration and being formed within respective one of recessed portions provided in a surface of a first semiconductor substrate, and then a second semiconductor substrate is brought into contact with the surface of the first semiconductor substrate. The gate structure may be formed such that each of the recessed portions is completely or partially filled with the gate structure. When the gate structure includes electrically good-conductive films of a high melting point metal or the like each formed in respective one of the recessed portions, the gate resistance can be further decreased.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 13, 1999
    Assignee: NGK Insulators, Ltd.
    Inventor: Yoshio Terasawa
  • Patent number: 5856683
    Abstract: A MOS-gate switched power semiconductor component with a semiconductor body that has a number of unit cells arranged side-by-side and switched in parallel and consisting of a p-emitter zone adjacent to the anode, an adjoining, weakly doped n-base zone, then a p-base zone and an adjoining n-emitter zone. Incorporated in the n-emitter zone of the unit cells are pairs of p.sup.+ zones (5a, 5b) which, together with the n zone between them and an insulated gate situated above, form a lateral p-channel MOSFET (M1). The n-emitter zone (4) is equipped with a floating cathode contact (K') which at the same time constitutes the electrode of the p.sup.+ region serving as source. The p+ region serving as drain is connected to an external cathode (K), which has no contact with the n-emitter zone. Another MOSFET is formed by the surface region of the p-base zone (3) and the intervening region of the n-emitter zone (4b) together with an insulating gate.
    Type: Grant
    Filed: August 5, 1996
    Date of Patent: January 5, 1999
    Assignee: Daimler-Benz Aktiengesellschaft
    Inventor: Heinrich Schlangenotto
  • Patent number: 5844259
    Abstract: An MCT is formed as a four-layer device, using alternating cells of: (a) P diffusions in an N.sup.- wafer having lower N.sup.+ and P.sup.+ layers with N.sup.+ cathode regions in the P diffusions, and (b) shallow P.sup.+ diverter cells. A cathode electrode is connected to the N.sup.+ cathodes, but not to the P diffusions containing the N.sup.+ cathode regions. The alternating cells are arranged in checkerboard fashion with the cells of any given row having a narrow spacing to define a narrow turn-off channel and the rows being more widely spaced to define a conduction channel having a reduced inherent JFET resistance.
    Type: Grant
    Filed: March 19, 1996
    Date of Patent: December 1, 1998
    Assignee: International Rectifier Corporation
    Inventors: Daniel M. Kinzer, Weizuo Zhang
  • Patent number: 5831293
    Abstract: There is provided a semiconductor substrate which includes a pair of main surfaces, a first semiconductor layer of a first conductivity type adjacent to one of the main surface, a second semiconductor layer of a second conducting type of which impurity concentration is lower than that of the first semiconductor layer and which is adjacent to the first semiconductivity, a third semiconductor layer of the first conductivity type adjacent to the second semiconductor, and a fourth semiconductor of the second conductivity type of which impurity concentration is higher than that of the third semiconductor and which is adjacent to the other of the main surfaces and the third semiconductor.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: November 3, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuo Mizoguchi, Masahiro Nagasu, Hideo Kobayashi, Tsutomu Yatsuo
  • Patent number: 5796124
    Abstract: On one major surface of an n.sup.- -type semiconductor substrate, a p-type region is formed in a semiconductor substrate, and an n-type emitter region is formed in the p-type base region. A p-type source region is formed near the p-type base region. A cathode electrode has a so-called shorted emitter structure in which the cathode electrode is connected to the p-type source region, the p-type base region, and the n-type emitter region. The p-type source region preferably has a pattern adjacent the p-type base region. The p-type base region is preferably constituted by a plurality of diffusion layers which are electrically connected to each other. Therefore, turn-off characteristics of a device can be improved, and turn-on characteristics are improved without degrading the turn-off characteristics, thereby improving trade-off between the turn-on characteristics and the turn-off characteristics.
    Type: Grant
    Filed: February 29, 1996
    Date of Patent: August 18, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidetoshi Nakanishi, Yasunori Usui, Shigenori Yakushiji
  • Patent number: 5793065
    Abstract: Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 11, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Shinohe, Kazuya Nakayama, Minami Takeuchi, Masakazu Yamaguchi, Mitsuhiko Kitagawa, Ichiro Omura, Akio Nakagawa
  • Patent number: 5780878
    Abstract: A lateral gate, vertical drift region transistor including a drain positioned on one surface of a substrate and a doped structure having a buried region therein positioned on the other surface of the substrate. The buried region defining a drift region in the doped structure extending vertically from the substrate and further defining a doped region in communication with the drift region and adjacent the surface of the doped structure. A source positioned on the doped structure in communication with the doped region. An insulating layer positioned on the doped structure with a metal gate positioned on the insulating layer so as to define an accumulation region extending laterally adjacent the control terminal and communicating with the drift region and the source.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: July 14, 1998
    Assignee: Motorola, Inc.
    Inventors: Mohit Bhatnagar, Charles E. Weitzel
  • Patent number: 5780917
    Abstract: In a composite controlled semiconductor device having an insulated gate, a p type semiconductor region forming no channel is provided between a plurality of p type semiconductor regions forming a channel and the potential of the p type semiconductor region in an ON state takes a value high enough to inject holes into an n type semiconductor region adjacent to the p type semiconductor region.
    Type: Grant
    Filed: April 2, 1993
    Date of Patent: July 14, 1998
    Assignee: Hitachi, Ltd.
    Inventor: Mitsuhiro Mori
  • Patent number: 5757037
    Abstract: The power thyristor of this invention has a cellular emitter structure. Each cell also has a FET assisted turn-on gate integrated into the cell. A turn-on gate voltage of one polarity is applied to a FET gate element that overlies the surface of the cell and to the turn-on gate integrated into the cell. When this voltage is so applied, a channel underlying the FET gate element becomes conductive, which allows the integrated turn-on gate to provide drive to the upper base-upper emitter junction of the thyristor cell thereby turning the thyristor cell on.
    Type: Grant
    Filed: February 1, 1995
    Date of Patent: May 26, 1998
    Assignee: Silicon Power Corporation
    Inventors: Dante E. Piccone, Harshad Mehta
  • Patent number: 5757036
    Abstract: A four-region semiconductor device (that is, a p-n-p-n or n-p-n-p device) including at least one further region utilizes integral FET structure for diverting carriers away from an interior region of the device and shunting them to a main current-carrying electrode of the device, whereby the device is provided with a turn-off capability. The device requires only a small amount of energy for its turn-off control gate, and utilizes a high percentage of its semiconductor body for carrying current through the device. High speed turn-off is achieved in a particular embodiment of the device.
    Type: Grant
    Filed: July 15, 1994
    Date of Patent: May 26, 1998
    Assignee: Harris Corporation
    Inventor: Victor Albert Keith Temple
  • Patent number: 5757035
    Abstract: In a surface of a silicon substrate of one conductivity type, there are formed a plurality of depressions or recesses, gate regions of opposite conductivity type are formed at bottoms of respective recesses, gate electrodes are provided on respective gate regions, and an electrically conductive block is joined to the surface of the semiconductor substrate. Between the surface of the semiconductor substrate and the electrically conductive block a contact region having a high impurity concentration and/or an electrically conductive material layer may be provided in order to improve electrical and mechanical properties of the contact between the semiconductor substrate and the electrically conductive block. The gate region can have a high impurity concentration and a distance between a channel region and the electrically conductive block can be very small.
    Type: Grant
    Filed: December 24, 1996
    Date of Patent: May 26, 1998
    Assignee: NGK Insulators, Ltd
    Inventor: Yoshio Terasawa
  • Patent number: 5751024
    Abstract: It is an object to obtain an insulated gate semiconductor device with an unreduced current value capable of being turned off while adopting structure for reducing the ON voltage, and a manufacturing method thereof. An N layer (43) is provided in close contact on a surface of an N.sup.- layer (42), a P base layer (44) is provided in close contact on the surface of the N layer (43), and a trench (47) which passes at least through the P base layer (44) is provided, and a gate electrode (49) is provided in the trench (47) through a gate insulating film (48). The carrier distribution of the N.sup.- layer (42) becomes closer to the carrier distribution of a diode, and an ON voltage is decreased and a current value capable of being turned off is not decreased when turning off. Accordingly, there are provided an insulated gate semiconductor device with low power consumption, small size, large capacity and high reliability.
    Type: Grant
    Filed: November 28, 1995
    Date of Patent: May 12, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hideki Takahashi
  • Patent number: 5751022
    Abstract: A semiconductor device is disclosed having a thyristor region coupled to a semiconductor switching device and a semiconductor rectifier. During turn-off operation, holes are drained from the p-type base region of the thyristor region through the semiconductor rectifier and to the cathode of the thyristor. During turn-on, electrons are supplied to an n-type emitter region of the thyristor from the cathode electrode through the semiconductor switching device.
    Type: Grant
    Filed: February 25, 1997
    Date of Patent: May 12, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Norio Yasuhara, Akio Nakagawa, Tomoko Matsudai, Hideyuki Funaki
  • Patent number: 5744830
    Abstract: A semiconductor device made of a lightly doped region of a first conductivity type has a well formed of a second conductivity type. The well extends to the surface of the device. First, second and third heavily doped regions of the first conductivity type are in the surface of the well. An electrode is fixed to the first heavily doped region of the first conductivity type. The third heavily doped region of the first conductivity type adjoins the lightly doped region of the first conductivity type. The first and second heavily doped regions of the first conductivity type are spaced apart from one another so that a portion of the well extends to the surface of the device therebetween. A first gate electrode is fixed via an insulating layer to a portion of the well extending between the first and second heavily doped regions. The first and third heavily doped regions of the first conductivity type are spaced apart from one another so that a portion of the well extends therebetween.
    Type: Grant
    Filed: November 13, 1995
    Date of Patent: April 28, 1998
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Sankaranarayanan Ekkanath-Madathil, Qin Huang, Gehan Anil Joseph Amaratunga, Naoki Kumagai
  • Patent number: 5739556
    Abstract: In a pressure contact housing for semiconductor components, the gate electrode contact ring 4 is provided with spiral recesses 5. The latter can absorb axial movements produced during the assembly of the housing, without loading the material. A good and durable electrical contact between the gate electrode and the gate electrode contact ring is obtained thereby.
    Type: Grant
    Filed: February 1, 1996
    Date of Patent: April 14, 1998
    Assignee: Asea Brown Boveri AG
    Inventor: Fabio Bolgiani
  • Patent number: 5736753
    Abstract: To provide a field-effect transistor having a large power conversion capacity and its fabrication method by decreasing the leakage current between the source and the drain of a semiconductor device made of hexagonal-system silicon carbide when the gate voltage of the semiconductor device is turned off and also decreasing the electrical resistance of the semiconductor device when the gate voltage of the semiconductor device is turned on. The main current path of the field-effect transistor is formed so that the current flowing between the source and the drain of, for example, a field-effect transistor flows in the direction parallel with the {0001} plane and a channel forming plane is parallel with the {1120} plane. ?Selected Drawing!FIG.
    Type: Grant
    Filed: August 30, 1995
    Date of Patent: April 7, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Toshiyuki Ohno, Yohsuke Inoue, Daisuke Kawase, Yuzo Kozono, Takaya Suzuki, Tsutomu Yatsuo
  • Patent number: 5723882
    Abstract: An insulated gate field effect transistor comprising a semiconductor substrate having one side on which a cell area is composed of a plurality of first wells of a first conductivity type, each of the first wells containing a source region of a second conductivity type. A channel region is defined in the surface portion of the semiconductor substrate adjoining to the source region, and a gate electrode is formed, via a gate insulating film, at least over the channel region. A source electrode is in common contact with the respective source regions of the plurality of first wells. The semiconductor substrate has a drain electrode provided on another side. A current flows between the source electrode and the drain electrode through the channel being controlled by a voltage applied to the gate electrode. A guard ring area is disposed on the one side of the semiconductor substrate so as to surround the cell area.
    Type: Grant
    Filed: March 10, 1995
    Date of Patent: March 3, 1998
    Assignee: Nippondenso Co., Ltd.
    Inventors: Naoto Okabe, Naohito Kato
  • Patent number: 5714775
    Abstract: A p-type emitter layer having a low resistivity is arranged on a bottom surface of an n-type base layer having a high resistivity. A p-type base layer is formed in a top surface of the n-type base layer. Trenches are formed in the p-type base layer and the n-type base layer such that each trench penetrates the p-type base layer and reaches down to a halfway depth in the n-type base layer. Inter-trench regions made of semiconductor are defined between the trenches. An n-type emitter layer having a low resistivity is formed in a surface of the p-type base layer to be in contact with the upper part of each trench. A gate electrode is buried via a gate insulating film in each trench. That side surface of each inter-trench region which faces the gate electrode consists of a {100} plane.
    Type: Grant
    Filed: April 19, 1996
    Date of Patent: February 3, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoki Inoue, Ichiro Omura, Hiromichi Ohashi
  • Patent number: 5714774
    Abstract: In a semiconductor device, in addition to a first emitter layer, a second emitter layer is formed on the surface side of a p-type base in spaced-apart relation with the first emitter layer. The first emitter layer is the source region of a first MOSFET, while the second emitter layer is the source region of a second MOSFET. Through signals imparted to first and second gate electrodes, the device, when turned on, operates with a low on-state voltage drop in a thyristor state and, when turned off, undergoes a turn-off in a short time by changing to a transistor state. The main current in the transistor state flows by being offset toward the first emitter layer side with respect to a main-current path on the lower side of the second emitter layer in the thyristor state. Since the current paths in each mode are separated, it is possible to reduce the resistance in the current path in the transistor state without increasing the on-voltage, thereby making it possible to obtain a large latch-up withstand capability.
    Type: Grant
    Filed: March 28, 1994
    Date of Patent: February 3, 1998
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Masahito Otsuki, Katsunori Ueno
  • Patent number: 5710443
    Abstract: A merged power device structure, of the emitter-switching type, in which the emitter of the bipolar power transistor has a minimum-width pattern which is aligned to the trenches of a trench control transistor. Thus the current density of the bipolar is maximized, since the emitter edge length per unit area is increased. The parasitic base resistance of the bipolar can also be reduced.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: January 20, 1998
    Assignee: SGS-Thompson Microelectronics, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 5710445
    Abstract: A GTO is specified which, starting from the anode-side main surface (2), comprises an anode emitter (6), a barrier layer (11), an n-base (7), a p-base (8) and a cathode emitter (9). The anode emitter (6) is designed as a transparent emitter and has anode short-circuits (10). By virtue of the combination of the barrier layer, the transparent anode emitter and the anode short-circuits, a GTO is obtained which can be operated at high switching frequencies, the substrate thickness of which can be reduced and which nevertheless exhibits no increase in the switching losses.
    Type: Grant
    Filed: June 27, 1995
    Date of Patent: January 20, 1998
    Assignee: Asea Brown Boveri AG
    Inventors: Friedhelm Bauer, Simon Eicher
  • Patent number: 5705835
    Abstract: A second region 3 is formed via a buffer layer 3a on a first region 2 formed with an anode electrode 1 on the rear and a third region 4 like a well is formed on the surface of the second region 3. A fourth region 15 like a well is formed at the center on the surface of the third region 4 and a fifth region 16 is formed along the well end. A sixth region 17 like a well is formed on the surface of the fourth region 15. Cathode electrodes 18 as metal electrodes of the first layer come in conductive contact with the fifth region 16 and the sixth region 17. A MOSFET 12 of n channel type for injecting majority carriers (electrons) is disposed from the first region 16 to the surfaces of the third region 4 and the second region 3, and a MOSFET 23 of p channel type is disposed from the sixth region 17 to the surfaces of the fourth region 16 and the third region 4. The second MOSFET 23 has a double diffusion type structure.
    Type: Grant
    Filed: November 24, 1995
    Date of Patent: January 6, 1998
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Akira Nishiura, Masahito Otsuki
  • Patent number: 5684306
    Abstract: An insulated gate thyristor is provided which includes a first-conductivity-type base layer having a high resistivity, a first and a second second-conductivity-type base region separately formed in a surface layer of the first-conductivity-type base layer, a first-conductivity-type source region formed in a surface layer of the first second-conductivity-type base region, and a first-conductivity-type emitter region formed in a surface layer of the second second-conductivity-type base region. A gate electrode is formed through an insulating film on exposed portions of the first second-conductivity-type base region, the first-conductivity-type base layer, and the second second-conductivity-type base region, which exposed portions are interposed between the first-conductivity-type source region and the first-conductivity-type emitter region. A first main electrode is held in contact with both the first second-conductivity-type base region and the first-conductivity-type source region.
    Type: Grant
    Filed: April 2, 1996
    Date of Patent: November 4, 1997
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Noriyuki Iwamuro
  • Patent number: 5682044
    Abstract: The present invention provides a reverse conducting (RC) thyristor of a planar-gate structure for low-and-medium power use which is relatively simple in construction because of employing a planar structure for each of thyristor and diode regions, permits simultaneous formation of the both region and have high-speed performance and a RC thyristor of a buried-gate or recessed-gate structure which has a high breakdown voltage by the use of a buried-gate or recessed-gate structure, permits simultaneous formation of thyristor and diode regions and high-speed, high current switching performance, and the RC thyristor of the planar-gate structure has a construction which comprises an SI thyristor or miniaturized GTO of a planar-gate structure in the thyristor region and an SI diode of a planar structure in the diode region, the diode region having at its cathode side a Schottky contact between n emitters or diode cathode shorted region and the thyristor region having at its anode side an SI anode shorted structure fo
    Type: Grant
    Filed: January 19, 1996
    Date of Patent: October 28, 1997
    Assignees: Takashige Tamamushi, Toyo Denki Seizo Kabushiki Kaisha
    Inventors: Takashige Tamamushi, Kimihiro Muraoka, Yoshiaki Ikeda, Keun Sam Lee, Naohiro Shimizu, Masashi Yura, Kinji Yoshioka
  • Patent number: 5668385
    Abstract: A power semiconductor component is specified which provides for a significant reduction in the thickness of the semiconductor substrate (1) whilst at the same time optimizing the switching losses. A transparent emitter (6) and a stop layer (7) are arranged to provide a thin semiconductor and optimized switching losses. The means can be used both in semiconductor switches such as IGBT, MCT or GTO and in diodes.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: September 16, 1997
    Assignee: Asea Brown Boveri AG
    Inventors: Friedhelm Bauer, Klas Lilja
  • Patent number: 5659185
    Abstract: Improved breakdown withstand capability is realized in a double gate insulated gate thyristor with low on-voltage in the thyristor operation mode and high-speed turn-off in the IGBT operation mode. Turn-off current through the lateral MOSFET using a second gate electrode is reduced, and breakdown withstand capability of the insulated gate thyristor is improved by inclusion of a gap in the (n) type source region, by contacting a part of the cathode directly to the (p) type base layer, and by connecting the bipolar transistor and the thyristor in parallel, for a part of the turn-off current to flow through the bipolar transistor to the cathode. A trench-type first gate electrode is preferred.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 19, 1997
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Noriyuki Iwamuro
  • Patent number: 5654561
    Abstract: A high-concentration n-type buffer layer and a low-concentration n-type buffer layer are provided between a p-type collector layer and a high-resistance n-type base layer, and respective impurity concentrations of the low-concentration n-type buffer layer and the high-concentration n-type buffer layer are set so that concentrations of carriers that propagate through the low-concentration n-type buffer layer and the high-concentration n-type buffer layer are in excess of the respective impurity concentrations thereof in an ON state. Thus, an insulated gate bipolar transistor having excellent withstand voltage, ON-state voltage and turn-off characteristics is obtained.
    Type: Grant
    Filed: November 22, 1995
    Date of Patent: August 5, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kiyoto Watabe
  • Patent number: 5652467
    Abstract: An auxiliary cathode lead is contacted to a cathode buffer electrode which contacts to an unit GTO arranged at the most remote region from a gate pressure contacting portion of a GTO pellet and the push-into effect of the auxiliary cathode current during the turn-off can be remarkably performed. Without inviting bad affects such as the increase in "on" voltage, it is proposed a package structure of a semiconductor which the unit GTO arranged remote from a gate is easily to perform the turn-off. The maximum turn-off current can be heightened, it can easily correspond to the increase in the diameter of the pellet according to the large current of the unit element. Further, a condenser of a snubber circuit as a protection circuit of the unit GTO in a power inverter can be small, and the snubber loss can be lessened.
    Type: Grant
    Filed: July 27, 1995
    Date of Patent: July 29, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Hidekatsu Onose, Shuroku Sakurada
  • Patent number: 5648665
    Abstract: A P.sup.+ layer is formed on the lower surface of an N.sup.- substrate, and recesses are defined in the upper surface of the N.sup.- substrate. Then, P.sup.+ gate regions and bottom gate regions are formed in side walls and bottoms of the recesses. The N.sup.- substrate and an N.sup.- substrate are ultrasonically cleaned to remove impurities therefrom, then cleaned by pure water, and dried by a spinner. Then, while lands on the upper surface of the N.sup.- substrate are being held against the surface of the N.sup.- substrate, the N.sup.- substrate are joined to each other by heating then at 800.degree. C. in a hydrogen atmosphere.
    Type: Grant
    Filed: April 26, 1995
    Date of Patent: July 15, 1997
    Assignee: NGK Insulators, Ltd.
    Inventor: Yoshio Terasawa
  • Patent number: 5644150
    Abstract: A double gate type insulated gate thyristor is provided which improves the breakdown withstand capability by turning on at low on-voltage by a thyristor operation mode and by turning off at high speed by an IGBT operation mode. In the insulated gate thyristor, a part of an n.sup.+ source region is removed and a p-base region is directly connected with a part of a cathode so as to connect a bipolar transistor with a main thyristor in parallel. A part of a switching-off current flows through the bipolar transistor to the cathode and the switching-off current which flows through a lateral MOSFET to the second gate electrode is reduced. By this configuration, the breakdown withstand capability is improved.
    Type: Grant
    Filed: March 16, 1995
    Date of Patent: July 1, 1997
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Noriyuki Iwamuro
  • Patent number: 5644149
    Abstract: A thyristor according to the invention comprises a layer sequence containing an n-type emitter layer (4), a p-type base layer (5), an n-type base layer (6) and a p-type emitter layer (7) in a semiconductor substrate (3) between an anode (1) and a cathode (2). The p-type emitter layer (7) is perforated by anode short-circuit zones (8) and is thereby subdivided into sections. In this arrangement, the anode short circuits (8) short-circuit the n-type base layer (6) to the anode (1). Disposed between the anode short circuits (8) and the p-type emitter layer (7) is a p-type barrier layer (9), also referred to as p-type soft layer. According to the invention, said p-type barrier layer (9) has gaps (12) in which the n-type base (6) is contacted by the anode (1) either directly or via an anode short circuit (8).
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: July 1, 1997
    Assignee: Asea Brown Boveri AG
    Inventor: Peter Streit
  • Patent number: 5640024
    Abstract: A compression-type semiconductor device comprises a silicon substrate in which crystal orientation between main faces opposite to each other is not larger than <1,0,0> .+-.27.5.degree.; cathode and gate electrodes formed on one of the main faces of the silicon substrate; an anode electrode formed on the other of the main faces of the silicon substrate; a cathode thermal compensation plate for the cathode and gate electrodes; and an anode thermal compensation plate for the anode electrode.
    Type: Grant
    Filed: December 8, 1995
    Date of Patent: June 17, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuhiro Morishita, Kazuhisa Ide, Futoshi Tokunoh
  • Patent number: 5621226
    Abstract: In a complex semiconductor device, an IGBT and a thyristor are formed in an identical semiconductor substrate to be connected in parallel with each other between main electrodes such that an end of the thyristor on the cathode side is connected to the main electrode via an insulated gate electrode of the IGBT. Thanks to the complex of the IGBT and the thyristor, there is attained a semiconductor device having a satisfactory ignition characteristic, a low on-state voltage, and a high breakdown voltage.
    Type: Grant
    Filed: April 26, 1994
    Date of Patent: April 15, 1997
    Assignee: Hitachi, Ltd.
    Inventor: Hideo Kobayashi
  • Patent number: 5616938
    Abstract: In an MOS-controlled power semiconductor component having a multiplicity of cathode cells, the surface area proportion of the cathode cells relative to the total component surface area is selected at between 0.1% and 10% in the case of circular cell geometry and between 0.4% and 40% in the case of strip-shaped cell geometry. As a result of this, the susceptibility to oscillation caused by small inductances can be reduced. (FIG.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: April 1, 1997
    Assignee: Asea Brown Boveri AG
    Inventor: Friedhelm Bauer
  • Patent number: 5614738
    Abstract: An emitter switched thyristor (EST) has improved turn-off withstand capability without deteriorating its on-voltage. The EST obtains a potential drop through a resistor disposed between the main electrode and the base region and facilitates uniformly recovering the reverse-blocking ability of the PN junction, in contrast to the ESTs of the prior art which obtain the potential drop by the current in Z-direction for latching up the thyristor from the IGBT mode. The present EST may be formed also in a horizontal device or a trench structure.
    Type: Grant
    Filed: March 31, 1995
    Date of Patent: March 25, 1997
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Noriyuki Iwamuro
  • Patent number: 5608238
    Abstract: A semiconductor device and a method for operating the same includes a first P-type semiconductor layer and a first N-type semiconductor layer provided thereon. A plurality of second P-type semiconductor layers and a plurality of third P-type semiconductor layers are formed on the surface of the first N-type semiconductor layer. A plurality of second N-type semiconductor layers are formed on their respective surfaces of the third P-type semiconductor layers. Emitter electrodes are provided on the second P-type semiconductor layers and second N-type semiconductor layers. A plurality of first gate electrodes is each provided above the first N-type semiconductor layer between the adjacent third P-type semiconductor layers. A plurality of second gate electrodes are each provided above the first N-type semi-conductor layer between the second P-type semiconductor layer and the third P-type semiconductor layer. A collector electrode is provided under the first P-type semiconductor layer.
    Type: Grant
    Filed: October 18, 1995
    Date of Patent: March 4, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideo Matsuda
  • Patent number: 5606183
    Abstract: A semiconductor device having a thyristor structure including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type and a fourth semiconductor region of the second conductivity type; a first MISFET capable of injecting majority carriers from the fourth semiconductor region into the second semiconductor region; and a second MISFET capable of being turned on and off independently of the first MISFET and extracting majority carriers from the third semiconductor region into the fourth semiconductor region, wherein the fourth semiconductor region is divided into the source region of the first MISFET and the source region of the second MISFET, the latter being formed in a portion isolated from the former, characterized in that the depth of the source region of the second MISFET is different from that of the drain region thereof.
    Type: Grant
    Filed: December 9, 1994
    Date of Patent: February 25, 1997
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Masahito Otsuki, Katsunori Ueno
  • Patent number: 5591991
    Abstract: After selectively forming P.sup.+ -type gate regions 14 in the upper surface of a first N.sup.- -type semiconductor substrate 10, gate electrodes 30 are selectively formed on the P.sup.+ -type gate regions. A P.sup.+ -type layer 12 is formed in the lower surface of the N.sup.- -type substrate 10. Recessed portions 26 which can house the gate electrodes are formed in the lower surface of the second N.sup.- -type semiconductor substrate 20 and an N.sup.+ -type layer 22 is formed in the upper surface thereof. After removing impurities from the surfaces of the first and second semiconductor substrates 10 and 20 by RCA cleaning, the surfaces are cleaned with a pure water and are dried by a spinner. Then the substrates 10 and 20 are joined to each other by heating the substrates 10 and 20 at 700-1100.degree. C. in an H.sub.2 atmosphere, while the upper surface of the first semiconductor substrate 10 is brought into contact with projected portions 29 on the lower surface of the second semiconductor substrate 20.
    Type: Grant
    Filed: March 28, 1995
    Date of Patent: January 7, 1997
    Assignee: NGK Insulators, Ltd.
    Inventor: Yoshio Terasawa
  • Patent number: 5587594
    Abstract: To provide thermal relief, particularly of the edge of disk-shaped gate-turn-off GTO thyristors (GTO) as are used in converters in power electronics, at least one cooling segment which is isolated from a GTO cathode metallization of the GTO thyristor segment (GTO) by a gate electrode metallization of a gate electrode is arranged on the edge and laterally adjacent to the GTO thyristor segment (GTO). An insulation layer is provided between a cooling segment metallization and the gate electrode metallization. Cooling segments in an lo outer annular zone can be alternately arranged with GTO thyristor segments (GTO) or offset towards the outside in the radial direction or perpendicular direction thereto. Instead of cooling segments, a p.sup.+ -type GTO emitter layer of the GTO thyristor segments (GTO) can be shortened at the edge in the outer annular zone.
    Type: Grant
    Filed: January 20, 1995
    Date of Patent: December 24, 1996
    Assignee: ABB Management AG
    Inventors: Andre Jaecklin, Ezatollah Ramezani, Peter Roggwiller, Andreas Ruegg, Thomas Stockmeier, Peter Streit, Jurg Waldmeyer
  • Patent number: 5574297
    Abstract: In order to compatibly implement improvement in withstand voltage and ON-state resistance as well as reduction in turnon loss and improvement in di/dt resistance, an n buffer layer (12) is locally exposed on a lower surface of a semiconductor substrate (160), while a polysilicon additional resistive layer (104) is formed to cover the exposed surface. An anode electrode (101) covering the lower surface of the semiconductor substrate (160) is connected to a p emitter layer (11) and the additional resistive layer (104). Thus, the n buffer layer (12) and the anode electrode (101) are connected with each other through the additional resistive layer (104), whereby a gate trigger current is reduced. Thus, turnon loss is reduced and di/dt resistance is increased. At the same time, the withstand voltage and the ON-state resistance are excellent due to provision of the n buffer layer (12).
    Type: Grant
    Filed: March 21, 1995
    Date of Patent: November 12, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nozomu Sennenbara, Kouji Niinobu, Kazuhiko Niwayama, Futoshi Tokunoh
  • Patent number: 5554863
    Abstract: A gate turn-off thyristor including: an n-type emitter semiconductor layer divided into a plurality of n-type areas; a p-type base semiconductor layer which cooperates with the n-type emitter semiconductor layer to form a first main circular surface; an n-type base semiconductor layer; and a p-type emitter semiconductor layer cooperating with the n-type base semiconductor layer to form a second main circular surface. An outer diameter of the p-type emitter semiconductor layer is smaller than that of the n-type emitter semiconductor layer. A first main electrode put in low resistance contact with the n-type emitter semiconductor layer is formed on the first main surface. A second main electrode put in low resistance contact with the p-type emitter layer and the n-type base semiconductor layer is formed on the second main surface. A control electrode is formed in the p-type base semiconductor on the first main surface.
    Type: Grant
    Filed: June 15, 1994
    Date of Patent: September 10, 1996
    Assignees: Hitachi, Ltd., Hitachi Haramachi Electronics Co., Ltd.
    Inventors: Sigeyasu Kouzuchi, Shuroku Sakurada, Takashi Saitoh, Hitoshi Komuro
  • Patent number: 5548133
    Abstract: An auxiliary MOSFET is integrated into a lateral IGBT structure with the source and drain of the auxiliary MOSFET in parallel with the emitter-base circuit of the IGBT. A driver, integrated with the IGBT chip, turns off the base emitter voltage to the IGBT before turning off the auxiliary MOSFET during turn off. The auxiliary MOSFET is turned off again at the beginning of the conduction period to ensure full conductivity modulation of the DMOS drain and maximum gain of the PNP transistor. Short circuit protection and overtemperature protection circuits are also integrated into the chip.
    Type: Grant
    Filed: September 19, 1994
    Date of Patent: August 20, 1996
    Assignee: International Rectifier Corporation
    Inventor: Daniel M. Kinzer
  • Patent number: 5543639
    Abstract: On one major surface of an n.sup.- -type semiconductor substrate, a p-type base region is formed in a semiconductor substrate, and an n-type emitter region is formed in the p-type base region. A p-type source region is formed near the p-type base region. A cathode electrode has a so-called shorted emitter structure in which the cathode electrode is connected to the p-type source region, the p-type base region, and the n-type emitter region. The p-type source region preferably has a pattern adjacent the p-type base region. The p-type base region is preferably constituted by a plurality of diffusion layers which are electrically connected to each other. Therefore, turn-off characteristics of a device can be improved, and turn-on characteristics are improved without degrading the turn-off characteristics, thereby improving trade-off between the turn-on characteristics and the turn-off characteristics.
    Type: Grant
    Filed: October 8, 1993
    Date of Patent: August 6, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidetoshi Nakanishi, Yasunori Usui, Shigenori Yakushiji
  • Patent number: 5539217
    Abstract: The SiC thyristor has a substrate, an anode, a drift region, a gate, and a cathode. The substrate, the anode, the drift region, the gate, and the cathode are each preferably formed of silicon carbide. The substrate is formed of silicon carbide having one conductivity type and the anode or the cathode, depending on the embodiment, is formed adjacent the substrate and has the same conductivity type as the substrate. A drift region of silicon carbide is formed adjacent the anode or cathode and has an opposite conductivity type as the anode or cathode. A gate is formed adjacent the drift region or the cathode, also depending on the embodiment, and has an opposite conductivity type as the drift region or the cathode. An anode or cathode, again depending on the embodiment, is formed adjacent the gate or drift region and has an opposite conductivity type than the gate.
    Type: Grant
    Filed: August 9, 1993
    Date of Patent: July 23, 1996
    Assignee: Cree Research, Inc.
    Inventors: John A. Edmond, John W. Palmour
  • Patent number: 5497011
    Abstract: In this semiconductor device, first, fifth and fourth impurity regions of a second conductivity type are formed on a main surface of a semiconductor layer of a first conductivity type with a predetermined space between each other. Second and third impurity regions of the first conductivity type are formed on the main surface of the first impurity region with a predetermined space between each other. A second gate electrode is formed between the second and third impurity regions. A first gate electrode is formed between the third impurity region and the semiconductor layer. A cathode electrode is connected to the third impurity region, and a short-circuit electrode is connected to first and second impurity regions. The first and fifth impurity regions are electrically short-circuited.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: March 5, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tomohide Terashima
  • Patent number: 5485022
    Abstract: An Insulated Gate Bipolar Transistor (IGBT) having a new structure capable of performing a low on-voltage and a high-speed turn-off is provided. A P-type collector region 1 of IGBT is not formed on the entire reverse surface of an N-type base region 2, but formed only on its part, and a metal collector electrode 9 is electrically connected only with the surface to which the P-type collector region 1 exposes. An area of a diffusion window in a collector region is relatively reduced, whereby the impurity concentration of the entire collector region is set at a lower value and hole injection efficiency is decreased. At the same time it is possible to obtain high surface concentration with deep diffusion depth of the collector region required to form a favorable ohmic contact.
    Type: Grant
    Filed: July 12, 1994
    Date of Patent: January 16, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tadashi Matsuda
  • Patent number: 5471075
    Abstract: A semiconductor switching device includes a plurality of adjacent and parallel-connected switching cells in a semiconductor substrate. Each cell includes a thyristor having a floating emitter region and a trench-gate field effect transistor (TFET) for providing turn-on and turn-off control of the thyristor. In one embodiment of the switching device, parasitic thyristor latch-up is suppressed by using a dual-channel TFET which forms both inversion-layer and accumulation-layer channel connections in series between respective floating emitter regions and the cathode contact. In another embodiment, parasitic thyristor latch-up is prevented by joining floating emitter regions of a pair of adjacent cells to thereby eliminate a parasitic P-N-P-N path between the anode and cathode contacts.
    Type: Grant
    Filed: May 26, 1994
    Date of Patent: November 28, 1995
    Assignee: North Carolina State University
    Inventors: Mallikarjunaswamy S. Shekar, B. Jayant Baliga, Jacek Korec
  • Patent number: 5464994
    Abstract: Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.
    Type: Grant
    Filed: August 16, 1994
    Date of Patent: November 7, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Shinohe, Kazuya Nakayama, Minami Takeuchi, Masakazu Yamaguchi, Mitsuhiko Kitagawa, Ichiro Omura, Akio Nakagawa