Having Narrow Energy Band Gap (<<1ev) Layer (e.g., Pbsnte, Hgcdte, Etc.) Patents (Class 257/188)
  • Patent number: 10811549
    Abstract: A quantum-dot based avalanche photodiode (QD-APD) may include a silicon substrate and a waveguide on which a quantum dot (QD) stack of layers is formed having a QD light absorption layer, a charge multiplication layer (CML), and spacer layers. The QD stack may be formed within a p-n junction. The waveguide may include a mode converter to facilitate optical coupling and light transfer from the waveguide to the QD light absorption layer. The QD absorption layer and the CML layer may be combined or separate layers. The CML may generate electrical current from the absorbed light with more than 100% quantum efficiency when the p-n junction is reverse-biased.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: October 20, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Geza Kurczveil, Di Liang, Bassem Tossoun, Chong Zhang, Xiaoge Zeng, Zhihong Huang, Raymond Beausoleil
  • Patent number: 10714653
    Abstract: Disclosed is a method of manufacturing a compound semiconductor solar cell according to an embodiment of the invention. The method of manufacturing the compound semiconductor solar cell according to the embodiment of the invention includes forming a plurality of compound semiconductor layers of at least two elements and including a base layer and an emitter layer, the base layer including a first conductivity type dopant to have a first conductivity type and the emitter layer including a second conductivity type dopant to have a second conductivity type. The forming of the plurality of compound semiconductor layers includes at least one of a process-temperature change period and a growth-rate change period.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: July 14, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Wonseok Choi, Gunho Kim
  • Patent number: 10326030
    Abstract: Some embodiments of the present disclosure provide an optical sensor. The optical sensor includes a semiconductive block having a front side and a back side, a wave guide region, and a light sensing region. The wave guide region is positioned over the back side of the semiconductive block and having a core layer. The wave guide region is configured to guide an incident light. The light sensing region is positioned in the semiconductive block, having a multi-junction photodiode. The light sensing region is configured to sense emission lights from the wave guide region.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: June 18, 2019
    Assignee: PERSONAL GENOMICS, INC.
    Inventor: Teng-Chien Yu
  • Patent number: 10170564
    Abstract: Provided is a manufacturing method of a semiconductor device including a vertical MOSFET having a planar gate. The manufacturing method of a semiconductor device includes forming a n-type gallium nitride layer on a gallium nitride monocrystalline substrate, and forming an impurity-implanted region that contains impurities at a uniform concentration in a direction parallel to a main surface of the gallium nitride monocrystalline substrate, by ion-implanting the impurities into the n-type gallium nitride layer, where the impurities include at least one type selected from among magnesium, beryllium, calcium and zinc. Here, at least part of the impurity-implanted region serves as a channel forming region of the vertical MOSFET.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: January 1, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Katsunori Ueno, Shinya Takashima
  • Patent number: 9761682
    Abstract: In order to improve the characteristics of a semiconductor device including: a channel layer and a barrier layer formed above a substrate; and a gate electrode arranged over the barrier layer via a gate insulating film, the semiconductor device is configured as follows. A silicon nitride film is provided over the barrier layer between a source electrode and the gate electrode, and is also provided over the barrier layer between a drain electrode and the gate electrode GE. The surface potential of the barrier layer is reduced by the silicon nitride film, thereby allowing two-dimensional electron gas to be formed. Thus, by selectively forming two-dimensional electron gas only in a region where the silicon nitride film is formed, a normally-off operation can be performed even if a trench gate structure is not adopted.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: September 12, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasuhiro Okamoto
  • Patent number: 9640701
    Abstract: A method of manufacturing a photodiode including a useful layer made of a semi-conductor alloy. The useful layer has a band gap value which decreases from its upper face to its lower face. A step of producing a first doped region forming a PN junction with a second doped region of the useful layer, said production of a first doped region including a first doping step, so as to produce a base portion; and a second doping step, so as to produce at least one protuberance protruding from the base portion and in the direction of the lower face.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: May 2, 2017
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Olivier Gravrand, Johan Rothman
  • Patent number: 9536917
    Abstract: Methods and structures for providing single-color or multi-color photo-detectors leveraging cavity resonance for performance benefits. In one example, a radiation detector (110) includes a semiconductor absorber layer (210, 410A, 410B, 610, 810, 1010, 1030, 1210, 1230) having a first electrical conductivity type and an energy bandgap responsive to radiation in a first spectral region, a semiconductor collector layer (220, 630, 830, 1020, 1040) coupled to the absorber layer (210, 410A, 41013, 610, 810, 1010, 1030, 1210, 1230) and having a second electrical conductivity type, and a resonant cavity coupled to the collector layer (220, 630, 830, 1020, 1040) and having a first mirror (240) and a second mirror (245).
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: January 3, 2017
    Assignee: RAYTHEON COMPANY
    Inventors: Justin Gordon Adams Wehner, Edward P. Smith, Stephanie Bostwick
  • Patent number: 9240429
    Abstract: An image pickup device includes a light-receiving device unit, a processing portion, a first connection body, and a second connection body. The first connection body electrically connects a first electrode of the light-receiving device unit to a corresponding second electrode of the processing portion. The first connection body includes an indium-containing solder portion disposed between the first electrode and the second electrode, and a barrier layer for suppressing alloying of the solder portion with the first electrode and the second electrode. The second connection body includes an alloy portion formed by alloying with a solder containing a material having a melting point equal to or higher than a melting point of the first connection body and a hardness higher than that of the first connection body.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: January 19, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hiroki Mori, Masaki Migita, Youichi Nagai
  • Patent number: 9231137
    Abstract: Using a highly doped Cap layer of the same composition as the Contact material in an nBn or pBp infrared photodetector allows engineering of the energy band diagram to facilitate minority carrier current flow in the contact region and block minority current flow outside the Contact region. The heavily doped Cap layer is disposed on the Barrier between the Contacts but electrically isolated from the Contact material.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: January 5, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Hasan Sharifi, Terence J. De Lyon, Rajesh D. Rajavel
  • Patent number: 9224734
    Abstract: A device includes a first semiconductor layer, and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer and the second semiconductor layer comprise different materials. A semiconductor region is overlying and contacting the second semiconductor layer, wherein a bottom surface of the semiconductor region contacts a first top surface of the second semiconductor layer. The semiconductor region and the second semiconductor layer comprise different material. The bottom surface of the semiconductor region has a slanted portion contacting a (551) surface plane of the second semiconductor layer.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 9006786
    Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material having the first lattice constant; a middle portion between the lower portion and upper portion, wherein the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; and a pair of notches extending into opposite sides of the middle portion; and an isolation structure surrounding the fin structure, wherein a top surface of the isolation structure is higher than a top surface of the pair of notches.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Zhiqiang Wu, Carlos H. Diaz, Jean-Pierre Colinge
  • Publication number: 20140319580
    Abstract: A device including at least one heterostructure p/n diode, including a substrate based on HgCdTe including for each diode: a first part having a first cadmium concentration; a concentrated part, having a second cadmium concentration, greater than the first concentration, forming a heterostructure with the first part; a p+ doped zone situated in the concentrated part and extending into the first part, forming a p/n junction with an n-doped position of the first part, or a base plate; and the concentrated part is only located in the p+ doped zone and forms a substantially constant cadmium concentration well.
    Type: Application
    Filed: November 26, 2012
    Publication date: October 30, 2014
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    Inventors: Laurent Mollard, Nicolas Baier, Johan Rothman
  • Patent number: 8860083
    Abstract: A low noise infrared photodetector has an epitaxial heterostructure that includes a photodiode and a transistor. The photodiode includes a high sensitivity narrow bandgap photodetector layer of first conductivity type, and a collection well of second conductivity type in contact with the photodetector layer. The transistor includes the collection well, a transfer well of second conductivity type that is spaced from the collection well and the photodetector layer, and a region of first conductivity type between the collection and transfer wells.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: October 14, 2014
    Assignee: Sensors Unlimited, Inc.
    Inventor: John Alfred Trezza
  • Patent number: 8691618
    Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate including a surface region. A first electrode layer is formed overlying the surface region. A copper layer is formed overlying the first electrode layer and an indium layer overlying the copper layer to form a multi-layered structure. The method subjects at least the multi-layered structure to a thermal treatment process in an environment containing a sulfur bearing species and form a copper indium disulfide material. The copper indium disulfide material includes a thickness of substantially copper sulfide material. The thickness of the copper sulfide material is removed to expose a surface region having a copper poor surface characterized by a copper to indium atomic ratio of less than about 0.95:1. The method subjects the copper poor surface to a metal cation species to convert the copper poor surface from an n-type semiconductor characteristic to a p-type semiconductor characteristic.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: April 8, 2014
    Assignee: Stion Corporation
    Inventor: Howard W. H. Lee
  • Patent number: 8686471
    Abstract: Disclosed are minority carrier based mercury-cadmium telluride (HgCdTe) infrared detectors and arrays, and methods of making, are disclosed. The constructions provided by the invention enable the detectors to be used at higher temperatures, and/or be implemented on less expensive semiconductor substrates to lower manufacturing costs. An exemplary embodiment a substrate, a bottom contact layer disposed on the substrate, a first mercury-cadmium telluride layer having a first bandgap energy value disposed on the bottom contact layer, a second mercury-cadmium telluride layer having a second bandgap energy value that is greater than the first bandgap energy value disposed on the first mercury-cadmium telluride layer, and a collector layer disposed on the second mercury-cadmium telluride layer, wherein the first and second mercury-cadmium telluride layers are each doped with an n-type dopant.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: April 1, 2014
    Assignee: DRS RSTA, Inc.
    Inventors: Michael A. Kinch, Christopher A. Schaake
  • Patent number: 8669588
    Abstract: A unit cell for use in an imaging system may include an absorber layer of semiconductor material formed on a semiconductor substrate, at least one contact including semiconductor material formed on the semiconductor substrate and electrically coupled to the absorber layer, and a cap layer of semiconductor material formed on the semiconductor substrate and electrically coupled to and formed between the absorber layer and the at least one contact. The absorber layer may be configured to absorb incident photons such that the absorbed photons excite electrons in the absorber layer to generate a photocurrent. The at least one contact may be configured to conduct the photocurrent to one or more electrical components external to the unit cell. The cap layer may be configured to conduct the photocurrent between the absorber layer and the at least one contact.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: March 11, 2014
    Assignee: Raytheon Company
    Inventors: Edward Peter Gordon Smith, Gregory Mark Venzor, Eric J. Beuville
  • Patent number: 8628989
    Abstract: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 8610170
    Abstract: An array structure solves issues that exist in conventional compound semiconductor photodiode arrays, such as large cross talk, large surface leaks, large stray capacitance, narrow detection wavelength bands, and bad manufacturing yield, simultaneously. A photodiode array has, laminated upon a semiconductor substrate, a buffer layer (8) with a broad forbidden band width, an I-type (low concentration photosensitive layer (2) with a narrow forbidden band width, and an n-type semiconductor window layer (3) with a broad forbidden band width, wherein photodiode elements are electrically separated from adjacent elements, by doping the periphery of the p-type impurity, and the detection wavelength band is expanded, by making the n-type window layer (3) on the photosensitive layer (2) a thinner layer with crystal growth.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: December 17, 2013
    Assignee: Irspec Corporation
    Inventors: Katsuhiko Nishida, Mutsuo Ogura
  • Patent number: 8513775
    Abstract: Provided is a CdTe-based semiconductor substrate for epitaxial growth, which is capable of growing good-quality epitaxial crystals without urging a substrate user to implement etching treatment before the epitaxial growth. A CdTe-based semiconductor substrate, in which tracks of linear polishing damage with a depth of 1 nm or more are not observed within a viewing range of 10 ?m×10 ?m when a surface of the substrate is observed by an atomic force microscope, and orange peel defects are not observed when the surface of the substrate is visually observed under a fluorescent lamp, can grow the good-quality epitaxial crystals.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: August 20, 2013
    Assignee: JX Nippon Mining & Metals Corporation
    Inventors: Kenji Suzuki, Hideyuki Taniguchi, Hideki Kurita, Ryuichi Hirano
  • Patent number: 8502271
    Abstract: A barrier-type photo-detector is provided with a Barrier between first and second layers. One of the layers is delineated into pixels without fully removing the non-pixel portions of the delineated layer. Delineation may be accomplished through material modification techniques such as ion damage, selective doping, ion induced disordering or layer material growth. Some variations may employ partial material removal techniques.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: August 6, 2013
    Assignee: Lockheed Martin Corporation
    Inventor: Jeffrey Winfield Scott
  • Publication number: 20130062663
    Abstract: A dichromatic photodiode and method for dichromatic photodetection are disclosed. A wide bandgap junction comprises a lattice matched junction operable to detect a first light spectrum. A narrow bandgap junction is coupled to the wide bandgap junction, and comprises a photodiode structure. The narrow bandgap junction is operable to detect a second light spectrum.
    Type: Application
    Filed: September 13, 2011
    Publication date: March 14, 2013
    Inventors: Ping Yuan, Xiaogang Bai, Rengarajan Sudharsanan
  • Patent number: 8373156
    Abstract: Provided is a biological component detection device with which a biological component can be detected at high sensitivity by using an InP-based photodiode in which a dark current is reduced without using a cooling mechanism and the sensitivity is extended to a wavelength of 1.8 ?m or more. An absorption layer 3 has a multiple quantum well structure composed of group III-V semiconductors, a pn-junction 15 is formed by selectively diffusing an impurity element in the absorption layer, and the concentration of the impurity element in the absorption layer is 5×1016/cm3 or less, the diffusion concentration distribution control layer has an n-type impurity concentration of 2×1015/cm3 or less before the diffusion, the diffusion concentration distribution control layer having a portion adjacent to the absorption layer, the portion having a low impurity concentration.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: February 12, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Youichi Nagai, Yasuhiro Iguchi
  • Patent number: 8330187
    Abstract: A GaN-based field effect transistor (MOSFET) is comprised of a channel layer comprised of p-type GaN, an electron supply layer, a surface layer having band gap energy smaller than that of the electron supply layer, sequentially laminated on a substrate, and recess section is formed by removing a part of the drift layer, the electron supply layer, and the surface layer down to a depth that reaches to the channel layer. A source electrode and a drain electrode are formed so that the recess section positions between them, a gate insulation film is formed on the surface layer and on inner-surface of the recess section including the channel layer, and a gate electrode is formed on the gate insulating film in the recess section.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: December 11, 2012
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Nomura Takehiko, Sato Yoshihiro, Kambayashi Hiroshi, Kaya Shusuke, Iwami Masayuki, Kato Sadahiro
  • Publication number: 20120286328
    Abstract: An array structure solves issues that exist in conventional compound semiconductor photodiode arrays, such as large cross talk, large surface leaks, large stray capacitance, narrow detection wavelength bands, and bad manufacturing yield, simultaneously. A photodiode array has, laminated upon a semiconductor substrate, a buffer layer (8) with a broad forbidden band width, an I-type (low concentration photosensitive layer (2) with a narrow forbidden band width, and an n-type semiconductor window layer (3) with a broad forbidden band width, wherein photodiode elements are electrically separated from adjacent elements, by doping the periphery of the p-type impurity, and the detection wavelength band is expanded, by making the n-type window layer (3) on the photosensitive layer (2) a thinner layer with crystal growth.
    Type: Application
    Filed: January 11, 2011
    Publication date: November 15, 2012
    Applicant: IRSPEC CORPORATION
    Inventors: Katsuhiko Nishida, Mutsuo Ogura
  • Publication number: 20120273838
    Abstract: Disclosed are minority carrier based mercury-cadmium telluride (HgCdTe) infrared detectors and arrays, and methods of making, are disclosed. The constructions provided by the invention enable the detectors to be used at higher temperatures, and/or be implemented on less expensive semiconductor substrates to lower manufacturing costs. An exemplary embodiment a substrate, a bottom contact layer disposed on the substrate, a first mercury-cadmium telluride layer having a first bandgap energy value disposed on the bottom contact layer, a second mercury-cadmium telluride layer having a second bandgap energy value that is greater than the first bandgap energy value disposed on the first mercury-cadmium telluride layer, and a collector layer disposed on the second mercury-cadmium telluride layer, wherein the first and second mercury-cadmium telluride layers are each doped with an n-type dopant.
    Type: Application
    Filed: December 14, 2011
    Publication date: November 1, 2012
    Inventors: Michael A. Kinch, Christopher A. Schaake
  • Patent number: 8299497
    Abstract: A photodetector is disclosed for the detection of near-infrared light with a wavelength in the range of about 0.9-1.7 microns. The photodetector, which can be formed as either an nBp device or a pBn device on an InP substrate, includes an InGaAs light-absorbing layer, an InAlGaAs graded layer, an InAlAs or InP barrier layer, and an InGaAs contact layer. The photodetector can detect near-infrared light with or without the use of an applied reverse-bias voltage and is useful as an individual photodetector, or to form a focal plane array.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: October 30, 2012
    Assignee: Sandia Corporation
    Inventors: John F. Klem, Jin K. Kim
  • Patent number: 8274096
    Abstract: The present invention is directed to a semiconductor device that includes at least one p-n junction including a p-type material, an n-type material, and a depletion region. The at least one p-n junction is configured to generate bulk photocurrent in response to incident light. The at least one p-n junction is characterized by a conduction band energy level, a valence band energy level and a surface Fermi energy level. The surface Fermi energy level is pinned either near or above the conduction band energy level or near or below the valence band energy level. A unipolar barrier structure is disposed in a predetermined region within the at least one p-n junction.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: September 25, 2012
    Assignee: University of Rochester
    Inventor: Gary W. Wicks
  • Patent number: 8169003
    Abstract: A semiconductor device is provided that includes a substrate, a first active layer disposed over the substrate, and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A termination layer, which is disposed on the second active layer, includes InGaN. Source, gate and drain contacts are disposed on the termination layer.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: May 1, 2012
    Assignee: Power Integrations, Inc.
    Inventors: Michael Murphy, Milan Pophristic
  • Patent number: 8134179
    Abstract: A photodiode in which a pn junction is formed between the doped region (DG) formed in the surface of a crystalline semiconductor substrate and a semiconductor layer (HS) deposited above said doped region. An additional doping (GD) is provided in the edge region of the doped zone, by means of which additional doping the pn junction is shifted deeper into the substrate (SU). With the greater distance of the pn junction from defects at phase boundaries that is achieved in this way, the dark current within the photodiode is reduced.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: March 13, 2012
    Assignee: austriamicrosystems AG
    Inventors: Jochen Kraft, Bernhard Löffler, Gerald Meinhardt
  • Patent number: 8093559
    Abstract: The present invention provides a two-terminal infrared detector capable of detecting a plurality of bands, such as three bands, over the visible and short-wave infrared bands. Detection of three colors enables one to construct composite imagery that provide significantly added contract in comparison to typical grayscale images. In some variations, the device includes multiple absorber and barrier layers that consist of distinct engineered semiconductor alloys which are closely lattice matched to InP.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: January 10, 2012
    Assignee: HRL Laboratories, LLC
    Inventor: Rajesh D. Rajavel
  • Publication number: 20110233609
    Abstract: The invention relates to a method for producing an infrared radiation sensor, said sensor comprising an infrared photodiode array formed in a first material and a reading circuit formed in a second material, said method comprising the steps of: sticking, through molecular adhesion, a first material side surface onto an optically transparent crystalline material side surface having infrared radiation and a coefficient of thermal expansion similar to that of the second material, give or take 20%; thinning the body of the first material side surface so that the latter is less that 25 ?m; producing infrared-sensitive photodiodes onto the thus-thinned first material side surface; depositing contact ball bearings onto the infrared photodiodes; and mounting the reading circuit onto the first material side surface through flip chip technology.
    Type: Application
    Filed: November 27, 2009
    Publication date: September 29, 2011
    Applicant: Sagem Defense Securite
    Inventors: Arnaud Cordat, Herve Sik, Stéphane Demiguel
  • Publication number: 20110156097
    Abstract: A photo-detector comprising: a photo absorbing layer comprising an n-doped semiconductor exhibiting a valence band energy level; a barrier layer, a first side of the barrier layer adjacent a first side of the photo absorbing layer, the barrier layer exhibiting a valence band energy level substantially equal to the valence band energy level of the doped semiconductor of the photo absorbing layer; and a contact area comprising a doped semiconductor, the contact area being adjacent a second side of the barrier layer opposing the first side, the barrier layer exhibiting a thickness and a conductance band gap sufficient to prevent tunneling of majority carriers from the photo absorbing layer to the contact area and block the flow of thermalized majority carriers from the photo absorbing layer to the contact area. Alternatively, a p-doped semiconductor is utilized, and conductance band energy levels of the barrier and photo absorbing layers are equalized.
    Type: Application
    Filed: February 23, 2011
    Publication date: June 30, 2011
    Inventor: Shimon Maimon
  • Patent number: 7943963
    Abstract: The present invention provides a top emission type organic light-emitting display device in a production of which it is possible to prevent the organic film from being oxidized when the upper transparent electrode is formed, and which is capable of emitting light at a low voltage. This organic light-emitting display device contains an organic light-emitting layer and an upper electrode and a lower electrode sandwiching the organic light-emitting layer, and is of a structure in which the emitted light is taken out from the upper electrode side, and a buffer layer mainly made of an oxide producing less oxygen by decomposition in the film-forming process than the upper electrode material is provided between the organic light-emitting layer and the upper electrode.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: May 17, 2011
    Assignee: Hitachi Displays, Ltd.
    Inventors: Hajime Murakami, Masao Shimizu, Sukekazu Aratani, Etsuko Nishimura, Masahiro Tanaka
  • Patent number: 7939853
    Abstract: A semiconductor device is provided that includes a substrate, a first active layer disposed over the substrate, and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A termination layer, which is disposed on the second active layer, includes InGaN. Source, gate and drain contacts are disposed on the termination layer.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: May 10, 2011
    Assignee: Power Integrations, Inc.
    Inventors: Michael Murphy, Milan Pophristic
  • Publication number: 20110095334
    Abstract: A barrier-type photo-detector is provided with a Barrier between first and second layers. One of the layers is delineated into pixels without fully removing the non-pixel portions of the delineated layer. Delineation may be accomplished through material modification techniques such as ion damage, selective doping, ion induced disordering or layer material growth. Some variations may employ partial material removal techniques.
    Type: Application
    Filed: October 22, 2010
    Publication date: April 28, 2011
    Applicant: Lockheed Martin Corporation
    Inventor: Jeff Winfield Scott
  • Patent number: 7928473
    Abstract: The invention relates to a photo-detector with a reduced G-R noise, which comprises a sequence of a p-type contact layer, a middle barrier layer and an n-type photon absorbing layer, wherein the middle barrier layer has an energy bandgap significantly greater than that of the photon absorbing layer, and there is no layer with a narrower energy bandgap than that in the photon-absorbing layer.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: April 19, 2011
    Assignee: An Elbit Systems-Rafael Partnership
    Inventor: Philip Klipstein
  • Patent number: 7892879
    Abstract: This invention relates to the manufacture of Cadmium Mercury Telluride (CMT) on patterned silicon, especially to growth of CMT on silicon substrates bearing integrated circuitry. The method of the invention involves growing CMT in selected growth windows on the silicon substrate by first growing one or more buffer layers by MBE and then growing the CMT by MOVPE. The growth windows may be defined by masking the area outside of the growth windows. Growth within the growth windows is crystalline whereas any growth outside the growth windows is polycrystalline and can be removed by etching. The invention offers a method of growing CMT structures directly on integrated circuits removing the need for hybridisation.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: February 22, 2011
    Assignee: Qinetiq Limited
    Inventors: Louise Buckle, John W Cairns, Jean Giess, Neil T Gordon, Andrew Graham, Janet E Hails, David J Hall, Colin J Hollier, Graham J Pryce, Andrew J Wright
  • Patent number: 7829915
    Abstract: The present invention changes layer polarities of an epitaxy structure of an avalanche photodiode into n-i-n-i-p. A transport layer is deposed above an absorption layer to prevent absorbing photon and producing electrons and holes. A major part of electric field is concentrated on a multiplication layer for producing avalanche and a minor part of the electric field is left on the absorption layer for transferring carrier without avalanche. Thus, bandwidth limit from a conflict between RC bandwidth and carrier transferring time is relieved. Meanwhile, active area is enlarged and alignment error is improved without sacrificing component velocity too much.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: November 9, 2010
    Assignee: National Central University
    Inventors: Jin-Wei Shi, Yen-Hsiang Wu
  • Patent number: 7823118
    Abstract: A computer readable medium comprising multiple instructions stored in a computer readable device, upon executing these instructions, a computer performing the following steps: providing a semiconductor layout and a circuit pattern; setting a forbidden area of the circuit pattern according to a restriction condition; defining at least a virtual pattern arrangement area on a portion of the semiconductor layout which does not correspond to the forbidden area; and providing a virtual pattern array in the virtual pattern arrangement area.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: October 26, 2010
    Assignee: United Microelectronics Corp.
    Inventor: Yan-Liang Ji
  • Patent number: 7799592
    Abstract: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: September 21, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Publication number: 20100230720
    Abstract: The present invention is directed to a semiconductor device that includes at least one p-n junction including a p-type material, an n-type material, and a depletion region. The at least one p-n junction is configured to generate bulk photocurrent in response to incident light. The at least one p-n junction is characterized by a conduction band energy level, a valence band energy level and a surface Fermi energy level. The surface Fermi energy level is pinned either near or above the conduction band energy level or near or below the valence band energy level. A unipolar barrier structure is disposed in a predetermined region within the at least one p-n junction.
    Type: Application
    Filed: February 16, 2010
    Publication date: September 16, 2010
    Applicant: UNIVERSITY OF ROCHESTER
    Inventor: Gary W. Wicks
  • Patent number: 7795640
    Abstract: The invention relates to a photo-detector with a reduced G-R noise, which comprises a sequence of a p-type contact layer, a middle barrier layer and an n-type photon absorbing layer, wherein the middle barrier layer has an energy bandgap significantly greater than that of the photon absorbing layer, and there is no layer with a narrower energy bandgap than that in the photon-absorbing layer.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: September 14, 2010
    Assignee: Semi-Conductor Devices-An Elbit Systems-Rafael Partnership
    Inventor: Philip Klipstein
  • Patent number: 7795639
    Abstract: A photodiode designed to capture incident photons includes a stack of at least three superposed layers of semiconductor materials having a first conductivity type. The stack includes: an interaction layer designed to interact with incident photons so as to generate photocarriers; a collection layer to collect the photocarriers; a confinement layer designed to confine the photocarriers in the collection layer. The collection layer has a band gap less than the band gaps of the interaction layer and confinement layer. The photodiode also includes a region which extends transversely relative to the planes of the layers. The region is in contact with the collection layer and confinement layer and has a conductivity type opposite to the first conductivity type so as to form a p-n junction with the stack.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: September 14, 2010
    Assignee: Commissariat A l'Energie Atomique
    Inventor: Johan Rothman
  • Patent number: 7728352
    Abstract: A damascene approach may be utilized to form an electrode to a lower conductive line in a phase change memory. The phase change memory may be formed of a plurality of isolated memory cells, each including a phase change memory threshold switch and a phase change memory storage element.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: June 1, 2010
    Assignee: Ovonyx, Inc.
    Inventor: Charles H. Dennison
  • Patent number: 7687874
    Abstract: In a mesa type PIN-PD formed using a heavily doped semiconductor material, a high frequency response is degraded as slow carriers occur in a heavily doped layer when light incident into a light receiving section transmits through an absorbing layer and reaches the heavily doped layer on a side near the substrate. In a p-i-n multilayer structure, a portion corresponding to a light receiving section of a heavily doped layer on a side near a substrate is previously made thinner than the periphery of the light receiving section by an etching or selective growth technique, over which an absorbing layer and another heavily doped layer are grown to form the light receiving section of mesa structure. This makes it possible to form a good ohmic contact and to realize a PIN-PD with excellent high frequency response characteristics.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: March 30, 2010
    Assignee: Opnext Japan, Inc.
    Inventors: Kazuhiro Komatsu, Yasushi Sakuma, Daisuke Nakai, Kaoru Okamoto, Ryu Washino
  • Patent number: 7615477
    Abstract: Ball Grid Array packages having decreased adhesion of the BGA pad to the laminate surface and methods for producing same are provided.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: November 10, 2009
    Assignee: International Business Machines Corporation
    Inventors: John U. Knickerbocker, Voya R. Markovich, Thomas R. Miller, William J. Rudik
  • Patent number: 7608825
    Abstract: There is provided an image pickup device which picks up an image of an object by absorbing light in a near infrared region reflected from the object and which has semiconductor photodetectors including an absorption layer of a bandgap wavelength in the range of 1.65 to 3.0 ?m.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: October 27, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Youichi Nagai, Yasuhiro Iguchi, Hiroshi Inada
  • Patent number: 7592654
    Abstract: CMOS image sensor having high sensitivity and low crosstalk, particularly at far-red to infrared wavelengths, and a method for fabricating a CMOS image sensor. A CMOS image sensor has a substrate, an epitaxial layer above the substrate, and a plurality of pixels extending into the epitaxial layer for receiving light. The image sensor also includes at least one of a horizontal barrier layer between the substrate and the epitaxial layer for preventing carriers generated in the substrate from moving to the epitaxial layer, and a plurality of lateral barrier layers between adjacent ones of the plurality of pixels for preventing lateral diffusion of electrons in the epitaxial layer.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: September 22, 2009
    Assignee: Aptina Imaging Corporation
    Inventors: Sandeep R. Bahl, Fredrick P. LaMaster, David W. Bigelow
  • Patent number: 7525131
    Abstract: Disclosed is a photoelectric surface including: a first group III nitride semiconductor layer that produces photoelectrons according to incidence of ultraviolet rays; and a second group III nitride semiconductor layer provided adjacent to the first group III nitride semiconductor layer and made of a thin-film crystal having c-axis orientation in a thickness direction, the second group III nitride semiconductor layer having an Al composition higher than that of the first group III nitride semiconductor layer.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: April 28, 2009
    Assignees: National University Corporation Shizuoka University, Hamamatsu Photonics K.K.
    Inventors: Masatomo Sumiya, Shunro Fuke, Tokuaki Nihashi, Minoru Hagino
  • Patent number: 7504672
    Abstract: A photodiode for detection of preferably infrared radiation wherein photons are absorbed in one region and detected in another. In one example embodiment, an absorbing P region is abutted with an N region of lower doping such that the depletion region is substantially (preferably completely) confined to the N region. The N region is also chosen with a larger bandgap than the P region, with compositional grading of a region of the N region near the P region. This compositional grading mitigates the barrier between the respective bandgaps. Under reverse bias, the barrier is substantially reduced or disappears, allowing charge carriers to move from the absorbing P region into the N region (and beyond) where they are detected. The N region bandgap is chosen to be large enough that the dark current is limited by thermal generation from the field-free p-type absorbing volume, and also large enough to eliminate tunnel currents in the wide gap region of the diode.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: March 17, 2009
    Assignee: DRS Sensors & Targeting Systems, Inc.
    Inventor: Michael A. Kinch