Tri-gate field-effect transistors formed by aspect ratio trapping

Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.

Skip to: Description  ·  Claims  ·  References Cited  · Patent History  ·  Patent History

Description

RELATED APPLICATION

This application claims the benefit of and priority to U.S. Provisional Application Ser. No. 60/847,424 filed Sep. 27, 2006, the entire disclosure of which is hereby incorporated by reference in its entirety.

FIELD OF THE INVENTION

This invention relates generally to semiconductor processing and particularly to the formation of tri-gate field-effect transistors.

BACKGROUND

Due to the increasing difficulty in shrinking complementary metal-oxide-semiconductor (CMOS) transistor gate lengths while simultaneously controlling leakage current, the traditional single-gate metal-oxide-semiconductor field-effect transistor (MOSFET) structure (where the inversion layer is formed only in the plane of the wafer surface) may be supplanted by dual- or triple-gate MOSFET structures. These structures, by increasing the gate's control of the channel potential, allow greater ability to turn off MOSFETs with ultra-short channel lengths. Of the various multi-gate MOSFETs structures explored in recent years, the most promising in terms of manufacturability and performance are typically variations of the so-called “FinFET” structure; these variations are known by such terms as “Tri-gate,” “Omega-FET,” or “MuGFET.” Generally, for each of these device types, a strip or “fin” of silicon (Si) is formed; subsequently the gate material is deposited and etched, so that the resulting gate surrounds the fin on the three exposed sides. The channel region of the device is located in the fin. To introduce strain into such a strip or fin, researchers have explored process-inducement methods similar to those employed in single-gate MOSFETs, such as, for example, epitaxially raised silicon germanium (SiGe) or silicon carbide (SiC) source and drain regions. There are, however, limitations to such methods, including limitations on how much strain can be introduced into the channel.

SUMMARY

In various embodiments, the invention includes methods and structures for introducing strain into FinFET-type devices by exploiting differences in natural lattice constants between the channel region in the fin and a substantially relaxed semiconductor region below the channel.

Accordingly, an aspect of the invention features a method for forming a structure. The method includes forming a dielectric layer over a semiconductor substrate comprising a first semiconductor material. A trench is defined in the dielectric layer, extending to a surface of the substrate, and having a height h and a width w; the ratio of h to w is preferably ≧0.5.

A crystalline material is formed in the trench. The crystalline material includes (i) a first layer comprising a second semiconductor material and (ii) a second layer comprising a third semiconductor material. A majority of dislocation defects in the crystalline material terminate within the trench. A portion of the dielectric layer is removed to expose a side portion of the crystalline material, and a gate is defined over the crystalline material.

One or more of the following features may be included. The second and third semiconductor materials may have different lattice constants; the difference between lattice constants may be less than 1%. The second semiconductor material may be relaxed and the third semiconductor material may be strained. Removing a portion of the dielectric layer may include exposing at least a portion of a sidewall of the second layer. The second semiconductor material may include SiGe, and/or the third semiconductor material may include at least one of Si and Ge.

The second semiconductor material may have a bandgap of at least 0.5 eV. It may include at least one of a III-V compound, such as aluminum antimonide (AlSb), indium aluminum antimonide (InAlSb), gallium antimonide (GaSb), or a II-VI compound, such as cadmium selenide (CdSe), zinc telluride (ZnTe), or cadmium telluride (CdTe).

The third semiconductor material may have a bulk electron mobility greater than 2000 cm2/V·s and may include at least one of indium antimonide (InSb), indium arsenide (InAs), or indium gallium arsenide (InGaAs).

In another aspect, the invention features a method for forming a structure, in which a dielectric layer is formed over a semiconductor substrate including a first semiconductor material. A trench is defined in the dielectric layer, extending to a surface of the substrate, and having a height h and a width w; the ratio of h to w is preferably ≧0.5. A. At least one crystalline material layer including a second semiconductor material having a lattice mismatch with the first semiconductor material is formed in the trench, such that a majority of dislocation defects in the second semiconductor material terminate within the trench. A portion of the dielectric layer is removed to expose a side portion of the crystalline material, and a gate is defined over the crystalline material.

One or more of the following features may be included. The second semiconductor material may include at least one of a III-V compound or a II-VI compound. The second semiconductor material may have a bandgap of at least 0.5 eV and/or have a bulk electron mobility greater than 2000 cm2/V·s.

The crystalline material layer(s) may include a first layer comprising the second semiconductor material and a second layer comprising a third semiconductor material. The third semiconductor material may include at least one of a III-V compound or a II-VI compound, and the third semiconductor material may be different from the second semiconductor material. The second and third semiconductor materials may have different lattice constants. The second semiconductor material may be relaxed and the third semiconductor material may be strained. The third semiconductor material may include at least one element contained in the second semiconductor material. Defining the dielectric layer may include thermal oxidation and/or plasma-enhanced chemical vapor deposition (PECVD).

In yet another aspect, the invention features a method for forming a structure, including removing a portion of a semiconductor substrate comprising a first semiconductor material to define a fin. A dielectric layer is deposited over the substrate and the fin, and then planarized such that a top surface of the dielectric layer is substantially co-planar with a top surface of the fin. A trench is formed by removing at least a portion of the fin, the trench has a height h and a width w, and the ratio of h to w is preferably ≧0.5. A crystalline material is formed in the trench, and includes a second semiconductor material lattice-mismatched to the first semiconductor material. A majority of dislocation defects in the crystalline material terminating within the trench. A portion of the dielectric layer is removed to expose a side portion of the crystalline material, and a gate is defined over the second semiconductor material.

In still another aspect, the invention features a structure having a strained channel and including multiple semiconductor material layers at least partially disposed in a trench. The structure includes a dielectric layer disposed over a semiconductor substrate comprising a first semiconductor material. A trench is disposed in the dielectric layer. The trench (i) extends to a surface of the substrate, (ii) is defined by at least one sidewall having a height h at least equal to a predetermined distance H from the surface of the substrate, and (iii) has a width w. A crystalline material is at least partially disposed in the trench. The crystalline material includes a first layer comprising a second semiconductor material and a second layer comprising a third semiconductor material. A side portion of the crystalline material extends above the dielectric layer, and a gate is disposed over the crystalline material. The ratio of the height h to the width w is ≧0.5, and a majority of dislocation defects in the crystalline material terminate at or below the predetermined vertical distance H (with h≧H). The third semiconductor material defines a strained channel.

In another aspect, a semiconductor device includes a transistor structure formed above a defect trapping region. The semiconductor device includes a defect-trapping region comprising a trench including a dielectric sidewall. The defect-trapping region is proximate a substrate having a first lattice constant. A semiconductor material, disposed within the defect trapping region, has a second lattice constant different from the first lattice constant. A majority of crystalline defects in the semiconductor material terminate within the defect trapping region. A fin having a semiconducting sidewall is disposed above the semiconductor material disposed within the defect trapping region, and a transistor gate is disposed over the semiconducting sidewall and top surface of the fin.

Still another aspect of the invention features a method for forming a structure. The method includes the steps of forming a dielectric layer over a semiconductor substrate that itself includes a first semiconductor material, and defining a trench in the dielectric layer extending to a surface of the substrate. The trench is defined by at least one sidewall having a height h at least equal to a predetermined distance H from the surface of the substrate; the trench is substantially rectangular and has a width w. A crystalline material including a first layer and a second layer is formed in the trench. The first layer includes a second semiconductor material, and the second layer includes a third semiconductor material. A portion of the dielectric layer is removed to expose a side portion of the crystalline material, and a gate is defined over the crystalline material. The ratio of the height h of the trench to the width w of the trench is ≧0.5, e.g., ≧1, and dislocation defects in the crystalline material terminate at the sidewall of the trench at or below the predetermined distance H (h≧H).

The second and third semiconductor materials may have different lattice constants. The second semiconductor material may be relaxed and the third semiconductor material may be strained. Removing a portion of the dielectric layer may include exposing at least a portion of a sidewall of the second layer. The second semiconductor material may comprise SiGe, and the third semiconductor material may include at least one of Si and Ge.

The second semiconductor material may have a bandgap of at least 0.5 eV. The second semiconductor material may include at least one of a III-V material and a II-VI material, e.g., at least one of AlSb, InAlSb, GaSb, CdSe, ZnTe, and CdTe.

The third semiconductor material may have a bulk electron mobility greater than 2000 cm2/V·s. The third semiconductor material may include at least one of InSb, InAs, and InGaAs. The difference between a lattice constant of the second semiconductor material and a lattice constant of the third semiconductor material may be less than 1%.

In another aspect, the invention features a method for forming a structure. The method includes removing a portion of a semiconductor substrate including a first semiconductor material to define a fin, and depositing a dielectric layer over the substrate and the fin. The dielectric layer is planarized such that a top surface of the dielectric layer is substantially co-planar with a top surface of the fin. A trench is defined by removing at least a portion of the fin. The trench has at least one sidewall having a height h at least equal to a predetermined distance H from the bottom of the trench. The trench is substantially rectangular and has a width w. A crystalline material including a second semiconductor material is formed in the trench. A portion of the dielectric layer is removed to expose a side portion of the crystalline material, and a gate is defined over the second semiconductor material. The ratio of the height h of the trench to the width w of the trench is ≧0.5, e.g., ≧1, and dislocation defects in the crystalline material terminate at the sidewall of the trench at or below the predetermined distance H, and h≧H.

In another aspect, the invention features a structure including a dielectric layer disposed over a semiconductor substrate that itself includes a first semiconductor material. A trench is disposed in the dielectric layer and extends to a surface of the substrate. The trench is defined by at least one sidewall having a height h at least equal to a predetermined distance H from the surface of the substrate. The trench is substantially rectangular and has a width w. A crystalline material is at least partially disposed in the trench. The crystalline material comprises a first layer including a second semiconductor material and a second layer including a third semiconductor material. A side portion of the second layer extends above the dielectric layer, and a gate is disposed over the crystalline material. The ratio of the height h of the trench to the width w of the trench is ≧0.5, e.g., ≧1, dislocation defects in the crystalline material terminate at the sidewall of the trench at or below the predetermined distance H, h≧H, and the third semiconductor material defines a strained channel.

The second and third semiconductor materials may have different lattice constants. The second semiconductor material may be relaxed and the third semiconductor material may be strained. In some embodiments, the second semiconductor material may include SiGe and the third semiconductor material may include at least one of Si and Ge.

In another aspect, the invention features a structure including a dielectric layer disposed over a semiconductor substrate that itself includes a first semiconductor material. A trench is disposed in the dielectric layer and extends to a surface of the substrate. The trench is defined by at least one sidewall having a height h at least equal to a predetermined distance H from the surface of the substrate. The trench is substantially rectangular and has a width w. A crystalline material is at least partially disposed in the trench. The crystalline material comprises a first layer including a second semiconductor layer and a second layer including a third semiconductor material. A side portion of the second layer extends above the dielectric layer, and a gate is disposed over the crystalline material. The ratio of the height h of the trench to the width w of the trench is ≧0.5, e.g., ≧1, dislocation defects in the crystalline material terminate at the sidewall of the trench at or below the predetermined distance H, h≧H, and the second semiconductor material has a bandgap of at least 0.5 eV.

The second semiconductor material may include at least one of a III-V material and a II-VI material, e.g., at least one of AlSb, InAlSb, GaSb, CdSe, ZnTe, or CdTe. The third semiconductor material may have a bulk electron mobility greater than 2000 cm2/V·s, and may include, e.g., at least one of InSb, InAs, and InGaAs. The difference between a lattice constant of the second semiconductor material and a lattice constant of the third semiconductor material may be less than 1%.

BRIEF DESCRIPTION OF FIGURES

In the drawings, like reference characters generally refer to the same features throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.

FIGS. 1-2 are schematic perspective views illustrating a method for formation of a device on a semiconductor substrate in accordance with an aspect of the invention;

FIGS. 3-4 are schematic perspective views illustrating an alternative method for formation of a device on a semiconductor substrate in accordance with other aspects of the invention; and

FIGS. 5-7 are schematic perspective views illustrating another alternative method for formation of a device on a semiconductor substrate in accordance with another aspect of the invention.

DETAILED DESCRIPTION

Referring to FIG. 1, a substrate 100 includes a first semiconductor material S1. The substrate 100 may be, for example, a bulk Si wafer, a bulk germanium (Ge) wafer, a semiconductor-on-insulator (SOI) substrate, or a strained semiconductor-on-insulator (SSOI) substrate. The substrate 100 may include or consist essentially of the first semiconductor material, such as a group IV element, e.g., Ge or Si, a III-V compound, or a II-VI compound. In an embodiment, substrate 100 includes or consists essentially of (100) Si.

A dielectric layer 110 is formed over the semiconductor substrate 100. The dielectric layer 110 may include or consist essentially of a dielectric material, such as silicon nitride (Si3N4) or silicon dioxide (SiO2). The dielectric layer 110 may be formed by any suitable technique, e.g., thermal oxidation or PECVD. As discussed below, the dielectric layer may have a thickness t1 corresponding to a desired height h of crystalline material to be deposited in a trench formed through the dielectric layer. In some embodiments, the thickness t1 of the dielectric layer 110 may be in the range of, e.g., 25-1000 nm.

A mask (not shown), such as a photoresist mask, is formed over the substrate 100 and the dielectric layer 110. The mask is patterned to expose at least a portion of the dielectric layer 110. The exposed portion of the dielectric layer 110 is removed by, e.g., reactive ion etching (RIE) to define a defect trapping region, e.g., trench 120. Trench 120 extends to a surface of the substrate 100 and may be defined by at least one sidewall 130. The height h of the sidewall 130 corresponds to the thickness t1 of the dielectric layer 110, and may be at least equal to a predetermined vertical distance H from a top surface 135 of the substrate, calculated as described below.

It has been observed experimentally that dislocations in a mismatched cubic semiconductor grown on a Si (100) surface in the near vicinity (e.g., within approximately 500 nm or less) of a vertical dielectric sidewall surface bend toward that surface at approximately 30 degrees through 60 degrees. For example, the dislocations may bend toward that surface at approximately a 45-degree angle to that surface. Based on this relationship, the predetermined vertical distance H necessary to trap defects is, typically, approximately equal to a width between ½ w and 2 w, where w is the width of the trench. This range is based on the range of intersection angles of approximately 30 degrees through 60 degrees; then, tan(30°)w≦H≦tan(60°)w, which roughly corresponds to ½ w≦H≦2 w.

The trench may be substantially rectangular in terms of cross-sectional profile, a top view, or both, and have a width w that is smaller than a length l of the trench. For example, the width w of the trench may be less than about 500 nm, e.g., about 10-100 nm, and the length l of the trench may exceed each of w and H. The ratio of the height h of the trench to the width w of the trench 120 may be ≧0.5, e.g., ≧1.

A crystalline material 140 is formed in the trench 120. The crystalline material 140 may include or consist essentially of a group IV element or compound, a III-V compound, or a II-VI compound. Examples of suitable group IV elements or compounds include Ge, Si, SiGe, and SiC. Examples of suitable III-V compounds include gallium arsenide (GaAs), gallium nitride (GaN), InAs, InSb, InAlSb, AlSb, indium aluminum arsenide (InAlAs), indium phosphide (InP), and InGaAs. Examples of suitable II-VI compounds include CdSe, ZnTe, and CdTe.

The crystalline material 140 may be formed by selective epitaxial growth in any suitable epitaxial deposition system, including, but not limited to, metal-organic chemical vapor deposition (MOCVD), atmospheric-pressure CVD (APCVD), low- (or reduced-) pressure CVD (LPCVD), ultra-high-vacuum CVD (UHCVD), molecular beam epitaxy (MBE), or atomic layer deposition (ALD). In the CVD process, selective epitaxial growth typically includes introducing a source gas into the chamber. The source gas may include at least one precursor gas and a carrier gas, such as, for example, hydrogen. The reactor chamber may be heated by, for example, RF-heating. The growth temperature in the chamber may range from about 300° C. to about 900° C., depending on the composition of the crystalline material. The growth system may also utilize low-energy plasma to enhance the layer growth kinetics.

The epitaxial growth system may be a single-wafer or multiple-wafer batch reactor. Suitable CVD systems commonly used for volume epitaxy in manufacturing applications include, for example, an Aixtron 2600 multi-wafer system available from Aixtron, based in Aachen, Germany; an EPI CENTURA single-wafer multi-chamber systems available from Applied Materials of Santa Clara, Calif.; or an EPSILON single-wafer epitaxial reactor available from ASM International based in Bilthoven, The Netherlands.

Dislocation defects 150 in the crystalline material 140 reach and terminate at the sidewalls of the trench 120 in the dielectric material 110 at or below the predetermined vertical distance H from the surface 135 of the substrate, such that dislocations in the crystalline material 140 decrease in density with increasing distance from the bottom portion of the trench 120. Accordingly, the upper portion of the crystalline material is substantially exhausted of dislocation defects. Various dislocation defects such as threading dislocations, stacking faults, twin boundaries, or anti-phase boundaries may thus be substantially eliminated from the upper portion of the crystalline material.

A planarization step such as, e.g., CMP may be used to ensure that the top surface of the crystalline material 140 is substantially co-planar with the top surface of the dielectric material 110.

Referring to FIG. 2, a portion of the dielectric layer 110 is selectively removed to expose a side portion 200 of the crystalline material 140. A height hchannel of the exposed side portion 200 may be equivalent to the thickness of a channel region to be formed. Preferably, the portion of the dielectric layer 110 is removed by an isotropic etch, e.g., a wet etch employing, for example, HF. A dry etch may also be used, e.g., a plasma etch employing CF4 and H2.

The crystalline material 140 may be considered as having two portions: a lower portion for trapping dislocation defects and an upper portion for a channel portion of a tri-gate MOSFET incorporating the crystalline material 140. The height h of the crystalline material thus has two components: the height htrapping of the lower portion (where defects are concentrated) and the height hchannel of the upper portion (which is largely free of defects). The height htrapping of the trapping portion may be selected from a range of about ½ w≦htrapping≦2 w, to ensure effective trapping of dislocation defects. The actual value of htrapping required may depend upon the type of dislocation defects encountered, which, in turn, may depend on the materials used, and also upon the orientation of the trench sidewalls. In some instances, the height htrapping need not be greater than that required for effective defect trapping, in order to ensure that the dislocation defects are trapped at a sufficient distance away from the channel portion. In this way, the deleterious effects of dislocation defects upon device performance are not experienced. For example, htrapping may be, e.g., 10-100 nm greater than required for effective trapping of defects. For the channel portion, the height hchannel may typically be selected from the range of approximately ½ w≦hchannel≦10 w. In some cases, if hchannel is significantly less than ½ w, the device may no longer be considered a multi-gate device, i.e., if conduction occurs primarily on the top surface of the gates disposed over the channel portion. If hchannel is significantly greater than 10 w, subsequent device processing may be challenging, for example, because of possible mechanical instability of the fin during processing, or because of challenges in implanting ions in sidewalls of closely packed devices that include tall fins.

A gate 210 is defined over the crystalline material 140 by deposition and selective removal of a gate dielectric material 220 and a conductive gate material 230. The gate dielectric material may be, e.g., SiO2, Si3N4, HfO2, HfSiON, and/or HfSiO. The conductive gate material 230 may be, for example, polysilicon, amorphous Si, Ge, or SiGe gate material, or a metal or metal alloy. In a tri-gate device, gate 210 has three portions, one on each exposed side portion of the crystalline material 140 and one on a top surface of the crystalline material 140.

A source and a drain may be defined in source and drain regions 240, 250 of the crystalline material 140 proximate to the gate 210 and next to a channel 260 disposed under the gate 210. The resulting structure is a tri-gate MOSFET 270, employing the benefits of aspect ratio trapping (“ART”). As used herein, “ART” refers generally to the technique(s) of causing defects in a material to terminate on a side surface as the material grows vertically, e.g., at a dielectric sidewall, with the sidewall being sufficiently high with respect to a width of the growth area, such that it traps most, if not all, of the defects.

Referring to FIGS. 3 and 4, in some embodiments, the crystalline material 140 includes a first layer 300 and a second layer 310. The first layer 300 includes a second semiconductor material S2, and the second layer 310 includes a third semiconductor material S3. Each of the semiconductor material S2, S3 may include or consist essentially of one or more of a group IV element or compound, a III-V compound, or a II-VI compound. Examples of suitable group IV elements or compounds include Ge, SiGe, and SiC. Examples of suitable III-V compounds include GaAs, GaN, InAs, InSb, InAlSb, AlSb, InAlAs, rip, and InGaAs. Examples of suitable II-VI compounds include CdSe, ZnTe, and CdTe.

In an embodiment, the second and third semiconductor materials S2, S3 may be different materials having different lattice constants. The lattice mismatch may be selected from a range of, e.g., 0.2-4.0%. If the lattice mismatch is too low, the benefit to performance may not be significant. If the lattice mismatch is too high, the allowable thickness of the third semiconductor material S3 may be too limited, if gross relaxation of third semiconductor material S3 is to be avoided. The second semiconductor material S2 may be relaxed and the third semiconductor material S3 may be strained.

In one embodiment, the second semiconductor material S2 includes or consists essentially of relaxed SiGe, and the third semiconductor material S3 includes or consists essentially of Si. This combination results in tensile strain in the channel 260. The strain may be primarily uniaxial in the direction of current flow due to lateral elastic relaxation. This type of strain is particularly beneficial for n-type metal-oxide-semiconductor (NMOS) device performance.

In another embodiment, the second semiconductor material includes or consists essentially of relaxed SiGe, and the third semiconductor material S3 includes or consists essentially of Ge. This combination results in compressive strain in the channel 240. The strain may be primarily uniaxial in the direction of current flow due to lateral elastic relaxation. This type of strain is particularly beneficial for p-type metal-oxide-semiconductor (PMOS) device performance.

The resulting tri-gate MOSFET 270 or FinFET (FIG. 4) includes dielectric layer 110 disposed over the semiconductor substrate 100 including the first semiconductor material S1. Trench 120 is disposed in the dielectric layer 110, extends to the surface 135 of the substrate 100, and is defined by at least one sidewall 130. The sidewall 130 has a height h at least equal to a predetermined distance H from the surface of the substrate. The trench is substantially rectangular and has a width w. Crystalline material 140 is at least partially disposed in the trench. The crystalline material comprises a first layer 300 that includes a second semiconductor material, and a second layer 310 that includes a third semiconductor material. A side portion of the second layer extends above the dielectric layer. Gate 210 is disposed over the crystalline material. A ratio of the height h of the trench to the width w of the trench is preferably ≧0.5, dislocation defects in the crystalline material terminate at the sidewall of the trench at or below the predetermined distance H, h≧H, and the third semiconductor material defines a strained channel 260.

A height hS2 of the first layer 300 may be approximately equal to htrapping, and a height hs3 of the second layer 310 may be approximately equal to hchannel, with htrapping and hchannel being determined as discussed above with reference to FIG. 2. The height of the first layer hs2 and the height of the second layer hs3 may be selected so that the second semiconductor material S2 is relaxed and the third semiconductor material S3 is strained, or vice versa.

The following relationships may be taken into consideration when selecting hS2 and hs3. For compressively strained films, substantial relaxation occurs at a film thickness of approximately 3-4 times hc, where hc is the critical thickness for the appearance of misfit dislocations. For tensilely strained films, substantial relaxation occurs at a film thickness of about 10 hc.

Referring still to FIGS. 3 and 4, in another embodiment, the second and third semiconductor materials S2, S3 may be selected to allow the formation of a bi-layer tri-gate device with high-mobility channel material and suppressed junction leakage. For example, the second semiconductor material S2 may have a bandgap of at least 0.5 eV. The second semiconductor material S2 may include or consist essentially of a III-V material and/or a II-VI material, such as AlSb, InAlSb, GaSb, CdSe, ZnTe, and/or CdTe. The third semiconductor material S3 may have a high bulk electron mobility, e.g., greater than 2000 cm2/V·s. Materials that are suitable for NMOS and have high mobilities include, e.g., InSb, InAs, and InGaAs.

For some potential III-V channel materials, straining the channel may not lead to significant performance benefits. In such cases, preferably the second semiconductor material S2 and the third semiconductor material S3 have similar lattice constants. Matching lattice constants helps avoid significant defect formation at an interface 400 between these two materials, while also allowing a sufficient height hS3 (e.g., 20-200 nm) of the second layer 310 to make this layer suitable for use as a MOS channel. In a preferred embodiment, the difference between the lattice constant of the second semiconductor material and the lattice constant of the third semiconductor material is less than 1%.

In forming the tri-gate device 270, a source and a drain are defined in source and drain regions 240, 250, respectively. Preferably, bottom portions of the source and the drain are disposed in second semiconductor material S2, such that the relatively high bandgap of second semiconductor material S2 helps limit junction leakage.

Referring to FIGS. 5-7, in some circumstances, from the standpoint of photolithography, it may be easier to define a narrow line than a narrow trench. Accordingly, an alternative process sequence for creating trench 120 begins with formation of a mask (not shown) over semiconductor substrate 100. A portion of the semiconductor substrate 100 is removed to define a fin 500. Fin 500 may have dimensions substantially identically to the dimensions of trench 120. Dielectric layer 110 is deposited over the semiconductor substrate 100 and the fin 500. The dielectric layer 110 is then planarized by, e.g., chemical-mechanical polishing (CMP) such that a top surface of the dielectric layer is substantially co-planar with a top surface 510 of the fin 500.

Trench 120 is defined by removing at least a portion of the fin 500. The fin may be selectively removed with a wet or dry etch that removes semiconductor material S1 with respect to the dielectric layer 110. For example, if semiconductor material S1 primarily comprises Si, and dielectric layer 110 primarily comprises SiO2, a dry etch utilizing Cl2 and/or HBr may be used to selectively remove the Si. The etch may be a timed etch, thereby avoiding undercutting a bottom portion of the dielectric layer 110.

As discussed above with respect to FIG. 1, trench 120 is defined by at least one sidewall having a height h at least equal to a predetermined distance H from the bottom of the trench. The trench may be substantially rectangular and have a width w. The ratio of the height h of the trench to the width w of the trench is preferably ≧1, dislocation defects in the crystalline material terminate at the sidewall of the trench at or below the predetermined distance H, and h≧H. A crystalline material 140 is formed in the trench. The crystalline material includes second semiconductor material S2.

Referring to FIG. 7, a portion of the dielectric layer 110 is removed to expose a side portion of the crystalline material. A gate dielectric 220 and a gate 210 are formed over the second semiconductor material S2, to define a FinFET.

The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments are therefore to be considered in all respects illustrative rather than limiting on the invention described herein. Scope of the invention is thus indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein.

Claims

1. A method for forming a structure, the method comprising the steps of:

forming a dielectric layer over a semiconductor substrate comprising a first semiconductor material;
defining a trench in the dielectric layer, the trench (i) extending to a surface of the substrate, and (ii) having a height h and a width w, the ratio of h to w being ≧0.5;
forming, in the trench, a crystalline material including a first layer comprising a second semiconductor material and a second layer comprising a third semiconductor material, a majority of dislocation defects in the crystalline material terminating within the trench;
removing a portion of the dielectric layer to expose a side portion of the crystalline material; and
defining a gate over the crystalline material.

2. The method of claim 1, wherein the second and third semiconductor materials have different lattice constants.

3. The method of claim 2, wherein the second semiconductor material is relaxed and the third semiconductor material is strained.

4. The method of claim 1, wherein removing a portion of the dielectric layer comprises exposing at least a portion of a sidewall of the second layer.

5. The method of claim 1, wherein the second semiconductor material comprises SiGe.

6. The method of claim 5, wherein the third semiconductor material comprises at least one of Si and Ge.

7. The method of claim 1, wherein the second semiconductor material has a bandgap of at least 0.5 eV.

8. The method of claim 7, wherein the second semiconductor material includes at least one of a III-V compound or a II-VI compound.

9. The method of claim 8, wherein the second semiconductor material comprises at least one of AlSb, InAlSb, GaSb, CdSe, ZnTe, or CdTe.

10. The method of claim 1, wherein the third semiconductor material has a bulk electron mobility greater than 2000 cm2/V·s.

11. The method of claim 10, wherein the third semiconductor material comprises at least one of InSb, InAs, or InGaAs.

12. The method of claim 1, wherein a difference between a lattice constant of the second semiconductor material and a lattice constant of the third semiconductor material is less than 1%.

13. A method for forming a structure, the method comprising the steps of:

forming a dielectric layer over a semiconductor substrate comprising a first semiconductor material;
defining a trench in the dielectric layer, the trench (i) extending to a surface of the substrate, and (ii) having a height h and a width w, the ratio of h to w being ≧0.5;
forming, in the trench, at least one crystalline material layer comprising a second semiconductor material having a lattice mismatch with the first semiconductor material, a majority of dislocation defects in the second semiconductor material terminating within the trench;
removing a portion of the dielectric layer to expose a side portion of the crystalline material; and
defining a gate over the crystalline material.

14. The method of claim 13, wherein the second semiconductor material includes at least one of a III-V compound or a II-VI compound.

15. The method of claim 13, wherein the second semiconductor material has a bandgap of at least 0.5 eV.

16. The method of claim 13, wherein the second semiconductor material has a bulk electron mobility greater than 2000 cm2/V·s.

17. The method of claim 13, wherein the at least one crystalline material layer includes a first layer comprising the second semiconductor material and a second layer comprising a third semiconductor material.

18. The method of claim 17, wherein the third semiconductor material comprises at least one of a III-V compound or a II-VI compound, and the third semiconductor material is different from the second semiconductor material.

19. The method of claim 17, wherein the second and third semiconductor materials have different lattice constants.

20. The method of claim 17, wherein the second semiconductor material is relaxed and the third semiconductor material is strained.

21. The method of claim 17, wherein the third semiconductor material includes at least one element contained in the second semiconductor material.

22. The method of claim 13, wherein defining the dielectric layer comprises at least one of thermal oxidation or PECVD.

23. A method for forming a structure, the method comprising:

removing a portion of a semiconductor substrate comprising a first semiconductor material to define a fin;
depositing a dielectric layer over the substrate and the fin;
planarizing the dielectric layer such that a top surface thereof is substantially co-planar with a top surface of the fin;
defining a trench by removing at least a portion of the fin, the trench having a height h and a width w, the ratio of h to w being ≧0.5;
forming, in the trench, a crystalline material comprising a second semiconductor material lattice-mismatched to the first semiconductor material, a majority of dislocation defects in the crystalline material terminating within the trench;
removing a portion of the dielectric layer to expose a side portion of the crystalline material; and
defining a gate over the second semiconductor material.

Referenced Cited

U.S. Patent Documents

4545109 October 8, 1985 Reichert
4551394 November 5, 1985 Betsch et al.
4651179 March 17, 1987 Reichert
4727047 February 23, 1988 Bozler et al.
4774205 September 27, 1988 Choi et al.
4789643 December 6, 1988 Kajikawa
4826784 May 2, 1989 Salerno et al.
4860081 August 22, 1989 Cogan
4876210 October 24, 1989 Barnett et al.
4948456 August 14, 1990 Schubert
5032893 July 16, 1991 Fitzgerald, Jr. et al.
5034337 July 23, 1991 Mosher et al.
5061644 October 29, 1991 Yue et al.
5091333 February 25, 1992 Fan et al.
5091767 February 25, 1992 Bean et al.
5093699 March 3, 1992 Weichold et al.
5098850 March 24, 1992 Nishida et al.
5105247 April 14, 1992 Cavanaugh
5156995 October 20, 1992 Fitzgerald, Jr. et al.
5166767 November 24, 1992 Kapoor et al.
5236546 August 17, 1993 Mizutani et al.
5238869 August 24, 1993 Shichijo et al.
5256594 October 26, 1993 Wu et al.
5269852 December 14, 1993 Nishida et al.
5269876 December 14, 1993 Mizutani et al.
5281283 January 25, 1994 Tokunaga et al.
5285086 February 8, 1994 Fitzgerald, Jr.
5295150 March 15, 1994 Vangieson et al.
5403751 April 4, 1995 Nishida et al.
5417180 May 23, 1995 Nakamura et al.
5427976 June 27, 1995 Koh et al.
5432120 July 11, 1995 Meister et al.
5438018 August 1, 1995 Mori et al.
5518953 May 21, 1996 Takasu et al.
5589696 December 31, 1996 Baba et al.
5621227 April 15, 1997 Joshi
5640022 June 17, 1997 Inai et al.
5710436 January 20, 1998 Tanamoto et al.
5717709 February 10, 1998 Sasaki et al.
5792679 August 11, 1998 Nakato
5825049 October 20, 1998 Simmons et al.
5849077 December 15, 1998 Kenney
5886385 March 23, 1999 Arisumi et al.
5953361 September 14, 1999 Borchert et al.
5966620 October 12, 1999 Sakaguchi et al.
6011271 January 4, 2000 Sakuma et al.
6015979 January 18, 2000 Sugiura et al.
6049098 April 11, 2000 Sato et al.
6100106 August 8, 2000 Yamaguchi et al.
6111288 August 29, 2000 Watanabe et al.
6191432 February 20, 2001 Sugiyama et al.
6228691 May 8, 2001 Doyle
6235547 May 22, 2001 Sakuma et al.
6252261 June 26, 2001 Usui et al.
6271551 August 7, 2001 Schmitz et al.
6320220 November 20, 2001 Watanabe et al.
6342404 January 29, 2002 Shibata et al.
6348096 February 19, 2002 Sunakawa et al.
6362071 March 26, 2002 Nguyen et al.
6407425 June 18, 2002 Babcock et al.
6475869 November 5, 2002 Yu
6492216 December 10, 2002 Yeo et al.
6512252 January 28, 2003 Takagi et al.
6521514 February 18, 2003 Gehrke et al.
6576532 June 10, 2003 Jones et al.
6579463 June 17, 2003 Winningham et al.
6603172 August 5, 2003 Segawa et al.
6617643 September 9, 2003 Goodwin-Johansson
6635110 October 21, 2003 Luan et al.
6686245 February 3, 2004 Mathew et al.
6710368 March 23, 2004 Fisher et al.
6720196 April 13, 2004 Kunisato et al.
6727523 April 27, 2004 Morita et al.
6753555 June 22, 2004 Takagi et al.
6762483 July 13, 2004 Krivokapic et al.
6767793 July 27, 2004 Clark et al.
6784074 August 31, 2004 Shchukin et al.
6787864 September 7, 2004 Paton et al.
6794718 September 21, 2004 Nowak et al.
7061065 June 13, 2006 Horng
6800910 October 5, 2004 Lin et al.
6803598 October 12, 2004 Berger et al.
6809351 October 26, 2004 Kuramoto et al.
6812495 November 2, 2004 Wada et al.
6815241 November 9, 2004 Wang
6815738 November 9, 2004 Rim
6825534 November 30, 2004 Chen et al.
6835246 December 28, 2004 Zaidi
6835618 December 28, 2004 Dakshina-Murthy et al.
6838322 January 4, 2005 Pham et al.
6841410 January 11, 2005 Sasaoka et al.
6841808 January 11, 2005 Shibata et al.
6849487 February 1, 2005 Taylor, Jr. et al.
6849884 February 1, 2005 Clark et al.
6855583 February 15, 2005 Krivokapic et al.
6855982 February 15, 2005 Xiang et al.
6855990 February 15, 2005 Yeo et al.
6867433 March 15, 2005 Yeo et al.
6873009 March 29, 2005 Hisamoto et al.
6887773 May 3, 2005 Gunn, III et al.
6888181 May 3, 2005 Liao et al.
6900070 May 31, 2005 Craven et al.
6900502 May 31, 2005 Ge et al.
6902965 June 7, 2005 Ge et al.
6902991 June 7, 2005 Xiang et al.
6909186 June 21, 2005 Chu
6917068 July 12, 2005 Krivokapic
6919258 July 19, 2005 Grant et al.
6920159 July 19, 2005 Sidorin et al.
6921673 July 26, 2005 Kobayashi et al.
6921963 July 26, 2005 Krivokapic et al.
6921982 July 26, 2005 Joshi et al.
6936875 August 30, 2005 Sugii et al.
6943407 September 13, 2005 Ouyang et al.
6946683 September 20, 2005 Sano et al.
6949769 September 27, 2005 Hu et al.
6955969 October 18, 2005 Djomehri et al.
6955977 October 18, 2005 Kong et al.
6958254 October 25, 2005 Seifert et al.
6960781 November 1, 2005 Currie et al.
6974733 December 13, 2005 Boyanov et al.
6977194 December 20, 2005 Belyansky et al.
6982204 January 3, 2006 Saxler et al.
6984571 January 10, 2006 Enquist
6991998 January 31, 2006 Bedell et al.
6994751 February 7, 2006 Hata et al.
6995430 February 7, 2006 Langdo et al.
6995456 February 7, 2006 Nowak
6998684 February 14, 2006 Anderson et al.
7001804 February 21, 2006 Dietz et al.
7012298 March 14, 2006 Krivokapic
7012314 March 14, 2006 Bude et al.
7015497 March 21, 2006 Berger
7015517 March 21, 2006 Grant et al.
7033436 April 25, 2006 Biwa et al.
7033936 April 25, 2006 Green et al.
7041178 May 9, 2006 Tong et al.
7045401 May 16, 2006 Lee et al.
7049627 May 23, 2006 Vineis et al.
7074623 July 11, 2006 Lochtefeld et al.
7078299 July 18, 2006 Maszara et al.
7078731 July 18, 2006 D'Evelyn et al.
7084051 August 1, 2006 Ueda et al.
7084441 August 1, 2006 Saxler
7087965 August 8, 2006 Chan et al.
7091561 August 15, 2006 Matsushita et al.
7095043 August 22, 2006 Oda et al.
7098508 August 29, 2006 Ieong et al.
7101444 September 5, 2006 Shchukin et al.
7109516 September 19, 2006 Langdo et al.
7118987 October 10, 2006 Fu et al.
7119402 October 10, 2006 Kinoshita et al.
7125785 October 24, 2006 Cohen et al.
7128846 October 31, 2006 Nishijima et al.
7132691 November 7, 2006 Tanabe et al.
7138292 November 21, 2006 Mirabedini et al.
7138302 November 21, 2006 Xiang et al.
7160753 January 9, 2007 Williams, Jr.
7164183 January 16, 2007 Sakaguchi et al.
7176522 February 13, 2007 Cheng et al.
7180134 February 20, 2007 Yang et al.
7195993 March 27, 2007 Zheleva et al.
7198995 April 3, 2007 Chidambarrao et al.
7205586 April 17, 2007 Takagi et al.
7205604 April 17, 2007 Ouyang et al.
7211864 May 1, 2007 Seliskar
7224033 May 29, 2007 Zhu et al.
7244958 July 17, 2007 Shang et al.
7247534 July 24, 2007 Chidambarrao et al.
7247912 July 24, 2007 Zhu et al.
7250359 July 31, 2007 Fitzgerald
7262117 August 28, 2007 Gunn, III et al.
7268058 September 11, 2007 Chau et al.
7344942 March 18, 2008 Korber
20010006249 July 5, 2001 Fitzgerald
20010045604 November 29, 2001 Oda et al.
20020030246 March 14, 2002 Eisenbeiser et al.
20020066403 June 6, 2002 Sunakawa et al.
20020070383 June 13, 2002 Shibata et al.
20020084000 July 4, 2002 Fitzgerald
20030030117 February 13, 2003 Iwasaki et al.
20030045017 March 6, 2003 Hiramatsu et al.
20030064535 April 3, 2003 Kub et al.
20030087462 May 8, 2003 Koide et al.
20030089899 May 15, 2003 Lieber et al.
20030155586 August 21, 2003 Koide et al.
20030178677 September 25, 2003 Clark et al.
20030207518 November 6, 2003 Kong et al.
20040012037 January 22, 2004 Venkatesan et al.
20040072410 April 15, 2004 Motoki et al.
20040075105 April 22, 2004 Leitz et al.
20040195624 October 7, 2004 Liu et al.
20040227187 November 18, 2004 Cheng et al.
20050003572 January 6, 2005 Hahn et al.
20050017351 January 27, 2005 Ravi
20050040444 February 24, 2005 Cohen
20050045983 March 3, 2005 Noda et al.
20050054164 March 10, 2005 Xiang
20050054180 March 10, 2005 Han
20050073028 April 7, 2005 Grant et al.
20050093021 May 5, 2005 Ouyang et al.
20050093154 May 5, 2005 Kottantharayil et al.
20050104152 May 19, 2005 Snyder et al.
20050104156 May 19, 2005 Wasshuber
20050118793 June 2, 2005 Snyder et al.
20050118825 June 2, 2005 Nishijima et al.
20050127451 June 16, 2005 Tsuchiya et al.
20050139860 June 30, 2005 Snyder et al.
20050145941 July 7, 2005 Bedell et al.
20050145954 July 7, 2005 Zhu et al.
20050156169 July 21, 2005 Chu
20050156202 July 21, 2005 Rhee et al.
20050161711 July 28, 2005 Chu
20050164475 July 28, 2005 Peckerar et al.
20050181549 August 18, 2005 Barr et al.
20050184302 August 25, 2005 Kobayashi et al.
20050205859 September 22, 2005 Currie et al.
20050205932 September 22, 2005 Cohen
20050212051 September 29, 2005 Jozwiak et al.
20050217565 October 6, 2005 Lahreche et al.
20050250285 November 10, 2005 Yoon et al.
20060009012 January 12, 2006 Leitz et al.
20060019462 January 26, 2006 Cheng et al.
20060049409 March 9, 2006 Rafferty et al.
20060105533 May 18, 2006 Chong et al.
20060113603 June 1, 2006 Currie
20060128124 June 15, 2006 Haskell et al.
20060131606 June 22, 2006 Cheng
20060145264 July 6, 2006 Chidambarrao et al.
20060160291 July 20, 2006 Lee et al.
20060175601 August 10, 2006 Lieber et al.
20060186510 August 24, 2006 Lochtefeld et al.
20060189056 August 24, 2006 Ko et al.
20060197123 September 7, 2006 Lochtefeld et al.
20060197124 September 7, 2006 Lochtefeld et al.
20060197126 September 7, 2006 Lochtefeld et al.
20060202276 September 14, 2006 Kato
20060205197 September 14, 2006 Yi et al.
20060211210 September 21, 2006 Bhat et al.
20060267047 November 30, 2006 Murayama
20060292719 December 28, 2006 Lochtefeld et al.
20070029643 February 8, 2007 Johnson et al.
20070054465 March 8, 2007 Currie et al.
20070054467 March 8, 2007 Currie et al.
20070105256 May 10, 2007 Fitzgerald
20070105274 May 10, 2007 Fitzgerald
20070105335 May 10, 2007 Fitzgerald
20070181977 August 9, 2007 Lochtefeld et al.
20070187668 August 16, 2007 Noguchi et al.
20070196987 August 23, 2007 Chidambarrao et al.
20070267722 November 22, 2007 Lochtefeld et al.
20080001169 January 3, 2008 Lochtefeld
20080070355 March 20, 2008 Lochtefeld et al.
20080073641 March 27, 2008 Cheng et al.
20080093622 April 24, 2008 Li et al.
20080099785 May 1, 2008 Bai et al.
20080187018 August 7, 2008 Li
20090039361 February 12, 2009 Li et al.
20090065047 March 12, 2009 Fiorenza et al.

Foreign Patent Documents

1 551 063 July 2005 EP
1796180 June 2007 EP
2-62090 March 1990 JP
02062090 March 1990 JP
2000-286449 October 2000 JP
2004-200375 July 2004 JP
WO-02/086952 October 2002 WO
WO 2004/023536 March 2004 WO
WO-2005/013375 February 2005 WO
WO-2005/048330 May 2005 WO
WO-2005/098963 October 2005 WO
WO-2005/122267 December 2005 WO
WO-2006/125040 November 2006 WO

Other references

  • 68 Applied Physics Letters 7, pp. 774-779 (1999). (trans. of relevant portions attached).
  • Asano, T. et al., “AIGaInN laser diodes grown on an ELO-GaN substrate vs. on a sapphire substrate,” 2000 IEEE 17th International Semiconductor Laser Conference, Conference Digest., pp. 109-110.
  • Ashby, C.I.H. et al., “Low-dislocation-density GaN from a single growth on a textured substrate.” Applied Physics Letters, v 77, n 20, Nov. 13, 2000, p. 3233-35.
  • Ashley et al., “Heternogeneous InSb Quantum Well Transistors on Silicon for ultra-high speed, low power logic applications,” 43 Electronics Letters 14 (Jul. 2007).
  • Bai et al, “Study of the defect elimination mechanisms in aspect ratio trapping Ge growth,” Appl. Phys. Letters, vol. 90 (2007).
  • Bakkers et al., “Epitaxial Growth on InP Nanowires on Germanium,” Nature Materials, vol. 3 (Nov. 2004), pp. 769-773.
  • Baron et al., “Chemical Vapor Deposition of Ge Nanocrystals on SiO2,” Applied Physics Letters, vol. 83, No. 7 (Aug. 18, 2003), pp. 1444-1446.
  • Beckett et al., “Towards a reconfigurable nanocomputer platform,” ACM Int'l. Conf. Proceeding Series, vol. 19, pp. 141-150 (2002).
  • Beltz et al., “A Theoretical Model for Threading Dislocation Reduction During Selective Area Growth,” Materials Science and Engineering, A234-236 (1997), pp. 794-797.
  • Borland, J.O., “Novel device structures by selective epitaxial growth (SEG),” 1987 International Electron Devices Meeting, pp. 12-15.
  • Bryskiewicz, T., “Dislocation filtering in SiGe and InGaAs buffer layers grown by selective lateral overgrowth method,” Applied Physics Letters, v 66, n 10, Mar. 6, 1995, p. 1237-39.
  • Bushroa, A.R. et al., “Lateral epitaxial overgrowth and reduction in defect density of 3C-SiC on patterned Si substrates,” Journal of Crystal Growth, v 271, Oct. 15, 2004, pp. 200-206.
  • Cannon et al., “Monolithic Si-based Technology for Optical Receiver Circuits,” Proceedings of SPIE, vol. 4999 (2003), pp. 145-155.
  • Chan et al., “Influence of metalorganic Sources on the Composition Uniformity of Selectively Grown GaxIn1-xP,” Jpn J. Appl. Phys., vol. 33 (1994) pp. 4812-4819.
  • Chang et al., “Epitaxial Lateral Overgrowth of Wide Dislocation-Free GaAs on Si Substrates,” Electrochemical Soc'y Proceedings, vol. 97-21, pp. 196-200.
  • Chang, Y.S. et al., “Effect of growth temperature on epitaxial lateral overgrowth of GaAs on Si substrate,” Journal of Crystal Growth, 174, Apr. 1997, pp. 630-634.
  • Chau et al., “Opportunities and Challenges of III-V Nanoelectronics for Future High-Speed, Low Power Logic Applications,” IEEE CSIC Digest, pp. 17-20 (2005).
  • Chen, Y. et al., “Dislocation reduction in GaN thin films via lateral overgrowth from trenches,” Applied Physics Letters, v 75, n 14, Oct. 4, 1999, p. 2062-63.
  • Dadgar et al., “MOVPE Growth of GaN on Si (111) Substrates,” Journal of Crystal Growth, 248 (2003) pp. 556-562.
  • Datta et al., “Silicon and III-V Nanoelectronics,” IEEE Int'l. Conf. on Indium Phosphide & Related Mat., pp. 7-8 (2005).
  • Datta et al., “Ultrahigh-Speed 0.5 V Supply Voltage In0.7Ga0.3As Quantum-Well Transistors on Silicon Substrate,” 28 Electron Device Letters 8, pp. 685-687 (2007).
  • Davis, R.F. et al., “Lateral epitaxial overgrowth of and defect reduction in GaN thin films,” IEEE Lasers and Electro-Optics Society Annual Meeting, 1998, vol. 1, pp. 360-361.
  • de Boeck et al., “The fabrication on a novel composite GaAs/SiO2 nucleation layer on silicon for heteroepitaxial overgrowth by molecular beam epitaxy,” Mat. Sci. and Engineering, B9 (1991), pp. 137-141.
  • Dong et al., “Selective area growth of InP through narrow openings by MOCVD and its application to InP HBT,” 2003 International Conference on Indium Phosphide and Related Materials, pp. 389-392, May 12-16, 2003.
  • Dong-Ho Kim et al., “GaN nano epitaxial lateral overgrowth on holographically patterned substrates,” International Symposium on Compound Semiconductors, pp. 27-28, Aug. 2003.
  • Epitaxial Lateral Overgrowth of GaAs on a Si Substrate, 28 Jap. J. App. Physics 3, pp. L337-L339 (Mar. 1989).
  • Fang et al., “Electrically pumped hybrid AIGaInAs-silicon evanescent laser,” 14 Optics Express 20, pp. 9203-9210 (2006).
  • Feltin, E. et al., “Epitaxial lateral overgrowth of GaN on Si (111),” Journal of Applied Physics, v 93, n 1, Jan. 1, 2003, pp. 182-185.
  • Fitzgerald et al., “Elimination of Dislocations in Heteroepitaxial MBE and RTCVD GexSi1-x Grown on Patterned Si Substrates,” Journal of Electronic Materials, vol. 19, No. 9 (1990), pp. 949-955.
  • Fitzgerald et al., “Epitaxial Necking in GaAs Grown on Pre-patterned Si Substrates,” Journal of Electronic Materials, vol. 20, No. 10 (1991), pp. 839-853.
  • Fitzgerald et al., “Nucleation Mechanisms and the Elimination of Misfit Dislocations at Mismatched Interfaces by Reduction in Growth Area,” J. Applied Phys., vol. 65, No. 6, (Mar. 15, 1989), pp. 2220-2237.
  • Fitzgerald, “The Effect of Substrate Growth Area on Misfit and Threading Dislocation Densities in Mismatched Heterostructures,” J. Vac. Sci. Technol., vol. 7, No. 4 (Jul./Aug. 1989), pp. 782-788.
  • Gallagher et al., “Development of the magnetic tunnel junction MRAM at IBM: From first junctions to a 16-Mb MRAM demonstrator chip,” 50 IBM J. Research & Dev. 1 (2006).
  • Gallas et al, “Influence of Doping on Facet Formation at the SiO2/Si Interface,” Surface Sci. 440, pp. 41-48 (1999).
  • Geppert, L., “Quantum transistors: toward nanoelectronics,” IEEE Spectrum, pp. 46-51 (Sep. 2000).
  • Glew et al., “New DFB grating structure using dopant-induced refractive index step,” J. Crystal Growth 261 (2004) pp. 349-354.
  • Gould et al., “Magnetic resonant tunneling diodes as voltage-controlled spin selectors,” 241 Phys. Stat. Sol. (B) 3, pp. 700-703 (2004).
  • Groenert et al., “Monolithic integration of room-temperature cw GaAs/AIGaAs lasers on Si substrates via relaxed graded GeSi buffer layers,” 93 J. Appl. Phys. 362 (2003).
  • Gustafsson et al., “Cathodoluminescence from relaxed GexSi1-x grown by heteroepitaxial lateral overgrowth,” J. Crystal Growth 141 (1994), pp. 363-370.
  • Gustafsson et al., “Investigations of high quality GexSi1-x grown by heteroepitaxial lateral overgrowth using cathodoluminescence,” Inst. Phys. Conf. Ser. No. 134: Section 11, pp. 675-678 (1993).
  • Hayafuji et al., Jap. J. Appl. Phys. 29, pp. 2371 (1990).
  • Hersee, et al., “The Controlled Growth of GaN Nanowires,” Nano Letters, vol. 6, No. 8 (2006), pp. 1808-1811.
  • Hiramatsu, K. et al., “Fabrication and characterization of low defect density GaN using facet-controlled epitaxial lateral overgrowth (FACELO),” Journal of Crystal Growth, v 221, Dec. 2000, pp. 316-326.
  • Hollander et al., “Strain and Misfit Dislocation Density in Finite Lateral Size Si1-xGex Films Grown by Sective Epitaxy,” Thin Solid Films, vol. 292, (1997) pp. 213-217.
  • Huang et al., “Electron and Hole Mobility Enhancement in Strained SOI by Wafer Bonding,” 49 IEEE Trans. on Electron Devices 9, pp. 1566-1571 (2002).
  • International Search Report and Written Opinion for Patent Application No. PCT/US2006/019152, dated Oct. 19, 2006.
  • International Search Report and Written Opinion for Patent Application No. PCT/US2006/029247, dated May 7, 2007.
  • International Search Report and Written Opinion for Patent Application No. PCT/US2006/033859, dated Sep. 12, 2007.
  • Ipri, A.C. et al., “Mono/Poly technology for fabricating low-capacitance CMOS integrated circuits,” IEEE Trans. on Electron Devices, vol. 35, No. 8, pp. 1382-1383, Aug. 1988.
  • Ishitani et al., “Facet Formation in Selective Silicon Epitaxial Growth,” 24 Jap. J. Appl. Phys. 10, pp. 1267-1269 (1985).
  • Jing Wang et al., “Fabrication of patterned sapphire substrate by wet chemical etching for maskless lateral overgrowth of GaN,” J. Electrochemical Soc'y, v. 153, n. 3, Mar. 2006, pp. C182-C185.
  • Ju, W. et al. , “Epitaxial lateral overgrowth of gallium nitride on silicon substrate,” J. Crystal Growth, v. 263, Mar. 1, 2004, p. 30-4.
  • Kamiyama, S. et al., “UV laser diode with 350.9-nm-lasing wavelength grown by hetero-epitaxial-lateral overgrowth technology,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 11, No. 5, pp. 1069-1073, Sep.-Oct. 2005.
  • Kamiyama, S. et al., “UV light-emitting diode fabricated on hetero-ELO-grown Al0.22Ga0.78N with low dislocation density,” Physica Status Solidi A, v 192, n 2, Aug. 2002, pp. 296-300.
  • Kazi et al., “Realization of GaAs/AIGaAs Lasers on Si Substrates Using Epitaxial Lateral Overgrowth by Metalorganic Chemical Vapor Deposition,” Jpn. J. Appl. Physics, vol. 40 (2001), pp. 4903-4906.
  • Kidoguchi, I. et al., “Air-bridged lateral epitaxial overgrowth of GaN thin films,” Applied Physics Letters, v 76, n 25, Jun. 19, 2000, pp. 3768-3770.
  • Kimura et al., “Vibronic Fine Structure Found in the Blue Luminescence from Silicon Nanocolloids,” Jpn. J. Appl. Physics, vol. 38 (1999), pp. 609-612.
  • Klapper, “Generation and Propagation of Dislocations During Crystal Growth,” Mat. Chem. and Phys. 66, pp. 101-109 (2000).
  • Knall et al., Threading Dislocations in GaAs Grown with Free Sidewalls on Si mesas, J Vac. Sci. Technol. B, vol. 12, No. 6, (Nov./Dec. 1994) pp. 3069-3074.
  • Krost et al., “GaN-based Optoelectronics on Silicon Substrates,” Mat. Sci. & Engineering, B93 (2002) pp. 77-84.
  • Kushida, K. et al., “Epitaxial growth of PbTiO3 films on SrTiO3 by RF magnetron sputtering,” Ultrasonics, IEEE Transactions on Ferroelectrics and Frequency Control, vol. 38, No. 6, pp. 656-662, Nov. 1991.
  • Kwok K Ng, Complete Guide to Semiconductor Devices, 2nd ed., Chapter 18 (2002).
  • Langdo et al., “High Quality Ge on Si by Epitaxial Necking,” Applied Physics Letters, vol. 76, No. 25 (Jun. 19, 2000), pp. 3700-3702.
  • Langdo, “Selective SiGe Nanostructures,” Ph.D. Thesis, Massachusetts Institute of Technology (2001).
  • Lee et al., “Strained-relieved, Dislocation-free InxGa1-xAs/GaAs(001) Heterostructure by Nanoscale-patterned Growth,” Applied Physics Letters, vol. 85, No. 18 (Nov. 1, 2004), pp. 4181-4183.
  • Lee, S.C. et al., “Growth of GaN on a nanoscale periodic faceted Si substrate by metal organic vapor phase epitaxy,” 2003 International Symposium on Compound Semiconductors: Post-Conference Proceedings, pp. 15-21.
  • Li et al, “Heteropitaxy of High-quality Ge on Si by Nanoscale Ge seeds Grown through a Thin Layer of SiO2,” Applied Physics Letters, vol. 85, No. 11 (Sep. 13, 2004), pp. 1928-1930.
  • Li et al., “Defect Reduction of GaAs Epitaxy on Si (001) Using Selective Aspect Ratio Trapping,” 91 Applied Physics Letters 021114-1-021114-3 (2007).
  • Li et al., “Morphological Evolution and Strain Relaxation of Ge Islands Grown on Chemically Oxidized Si(100) by Molecular-beam Epitaxy,” J. Applied Physics, vol. 98, (2005), pp. 073504-1-073504-8.
  • Li et al., “Selective Growth of Ge on Si(100) through vias of SiO2 Nanotemplate Using Solid Source Molecular Beam Epitaxy,” Applied Physics Letters, vol. 83, No. 24 (Dec. 15, 2003), pp. 5032-5034.
  • Liang et al., “Critical Thickness Enhancement of Epitaxial SiGe films Grown on Small Structures,” Journal of Applied Physics, vol. 97, (2005) pp. 043519-1-043519-7.
  • Lim et al., “Facet Evolution in Selective Epitaxial Growth of Si by cold-wall ultrahigh vacuum chemical vapor deposition,” J. Vac. Sci. Tech. B 22(2), p. 682 (2004).
  • Liu et al., “High Quality Single-crystal Ge on Insulator by Liquid-phase Epitaxy on Si Substrates,” Applied Physics Letters, vol. 84, No. 14, (Apr. 4, 2004) pp. 2563-2565.
  • Liu et al., “Rapid Melt Growth of Germanium Crystals with Self-Aligned Microcrucibles on Si Substrates,” J. Electrochemical Soc'y, vol. 152, No. 8, (2005) pp. G688-G693.
  • Loo et al., “Successful Selective Epitaxial Si1-x Gex Deposition Process for HBT-BiCMOS and high Mobility Heterojunction pMOS Applications,” 150 J. Electrochemical Soc'y 10, pp. G638-G647 (2003).
  • Lourdudoss, S. et al., “Semi-insulating epitaxial layers for optoelectronic devices,” 2000 IEEE International Semiconducting and Insulating Materials Conference, pp. 171-178.
  • Luan et al., “High-quality Ge Epilayers on Si with Low Threading-dislocation Densities,” Applied Phsics Letters, vol. 75, No. 19, (Nov. 8, 1999) pp. 2909-2911.
  • Luan, “Ge Photodectors for Si Microphotonics,” Ph.D. Thesis, Massachusetts Institute of Technology, Feb. 2001.
  • Lubnow et al., “Effect of III/V-Compound Epitaxy on Si Metal-Oxide-Semiconductor Circuits,” Jpn. J. Applied Phys., vol. 33 (1994) pp. 3628-3634.
  • Luryi et al., “New Approach to the High Quality Epitaxial Growth of Latticed-mismatch Materials,” Appl. Phys. Lett., vol. 49, No. 3, (Jul. 21, 1986) pp. 140-142.
  • Martinez et al., “Characterization of GaAs Conformal Layers Grown by Hydride Vapour Phase Epitaxy on Si Substrates by Microphotoluminescence Cathodoluminescence and microRaman,” J. Crystal Growth, vol. 210 (2000) pp. 198-202.
  • Matsunaga et al., “A New Way to Achieve Dislocation-free Heteroepitaxial Growth by Molecular Beam Epitaxy: Vertical Microchannel Epitaxy,” J. Crystal Growth, 237-239 (2002) pp. 1460-1465.
  • Monroy et al., “High UV/visible contrast photodiodes based on epitaxial lateral overgrown GaN layers,” Electronics Letters , vol. 35, No. 17, pp. 1488-1489, Aug. 19, 1999.
  • Nakano, K. et al., “Epitaxial lateral overgrowth of AIN layers on patterned sapphire substrates,” Source: Physica Status Solidi A, v 203, n 7, May 2006, p. 1632-35.
  • Nam et al., “Lateral Epitaxy of Low Defect Density GaN Layers via Organometallic Vapor Phase Epitaxy,” Appl. Phys. Letters, vol. 71, No. 18, (Nov. 3, 1997) pp. 2638-2640.
  • Naoi et al, “Epitaxial Lateral Overgrowth of GaN on Selected-area Si(111) Substrate with Nitrided Si Mask,” Journal of Crystal Growth, vol. 248, (2003) pp. 573-577.
  • Naritsuka et al., “InP Layer Grown on (001) Silicon Substrate by Epitaxial Lateral Overgrowth,” Jpn. J. Appl. Physics, vol. 34 (1995), pp. L1432-L1435.
  • Naritsuka et al., “Vertical Cavity Surface Emitting Laser Fabricated on GaAs Laterally Grown on Si Substrate,” Electrochemical Soc'y Proc. vol. 97-21, pp. 86-90.
  • Neudeck et al., “Novel silicon epitaxy for advanced MOSFET devices,” Electron Devices Meeting, 2000 IEDM Technical Digest, pp. 169-172.
  • Norman, A.G. et al., “Characterization of MOCVD lateral epitaxial overgrown III-V semiconductor layers on GaAs substrates,” Int'l Symposium on Compound Semiconductors, pp. 45-46, Aug. 25-27, 2003.
  • Parillaud et al, “High Quality InP on Si by Conformal Growth,” Appl. Phys. Lett., vol. 68, No. 19 (May 6, 1996) pp. 2654-2656.
  • Park et al., “Defect Reduction and Its Mechanism of Selective Ge Epitaxy in Trenches on Si(001) Substrates Using Aspect Ratio Trapping,” Mat. Res. Soc'y Symp. Proc., vol. 994 (2007).
  • Park et al., “Defect Reduction of Selective Ge Epitaxy in Trenches on Si(001) Substrates using Aspect Ratio Trapping,” 90 Appl. Physics Letters (2007).
  • Park et al., “Growth of Ge Thick Layers on Si(001) Substrates Using Reduced Pressure Chemical Vapor Deposition,” 45 Japanese J. Applied Physics 11, pp. 8581-8585 (2006).
  • Partial International Search for International Application No. PCT/US2006/033859, 7 pages.
  • Piffault, N. et al., “Assessment of the strain of InP films on Si obtained by HVPE conformal growth,” Sixth Int'l Conference on Indium Phosphide and Related Materials, Conf. Proc., pp. 155-158, Mar. 27-31, 1994.
  • Pribat et al., “High Quality GaAs on Si by Conformal Growth,” Appl. Phys. Lett., vol. 60, No. 17 (Apr. 27, 1992) pp. 2144-2146.
  • Reed et al., “Realization of a three-terminal resonant tunneling device: the bipolar quantum resonant tunneling transistor,” 54 Appl. Phys. Letters 11, p. 1034 (1989).
  • Ren, D. et al., “Low-dislocation-density, nonplanar GaN templates for buried heterostructure lasers grown by lateral epitaxial overgrowth,” Applied Physics Letters, v 86, Mar. 14, 2005, 111901-1-111901-3.
  • Rim et al., “Fabrication and mobility characteristics of ultra-thin strained Si Directly on Insulator (SSDOI) MOSFETs,” 2003 IEDM Tech. Dig., pp. 49-52.
  • Ringel et al., “Single-junction InGaP/GaAs Solar Cells Grown on Si Substrates with SiGe Buffer Layers,” Prog. Photovolt.: Res. & Appl. 2002; 10:417-426.
  • Sakai, “Defect Structure in Selectively Grown GaN films with low threading dislocation density,” Appl. Physics Letters 71(16), pp. 2259-2261 (1997).
  • Sakai, “Transmission electron microscopy of defects in GaN films formed by epitaxial lateral overgrowth,” 73 App. Physics Letters 4, pp. 481-483 (1998).
  • Sakawa et al., “Effect of Si Doping on Epitaxial Lateral Overgrowth of GaAs on GaAs-Coated Si Substrate,” Jpn. J. Appl. Physics, vol. 31 (1992), pp. L359-L361.
  • Sangwoo Pae et al., “Multiple layers of silicon-on-insulator islands fabrication by selective epitaxial growth,” Electron Device Letters, vol. 20, No. 5, pp. 194-196, May 1999.
  • Schaub, J.D. et al., “Resonant-cavity-enhanced high-speed Si photodiode grown by epitaxial lateral overgrowth,” Photonics Technology Letters, vol. 11, No. 12, pp. 1647-1649, Dec. 1999.
  • Seabaugh et al., “Promise of Tunnel Diode Integrated Circuits,” Tunnel Diode and CMOS/HBT Integration Workshop, Dec. 9, 1999, Naval Research Laboratory.
  • Shahidi, G. et al., “Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing,” 1990 IEDM Tech. Dig., pp. 587-590.
  • Siekkinen, J.W. et al., “Selective epitaxial growth silicon bipolar transistors for material characterization,” IEEE Transactions on Electron Devices, vol. 35, No. 10, pp. 1640-1644, Oct. 1988.
  • Su et al., “Catalytic Growth of Group III-nitride Nanowires and Nanostructures by Metalorganic Chemical Vapor Deposition,” Applied Physics Letters, vol. 86 (2005) pp. 013105-1-013105-3.
  • Su et al., “New planar self-aligned double-gate fully-depleted P-MOSFETs using epitaxial lateral overgrowth (ELO) and selectively grown source/drain (S/D),” IEEE International SOI Conference, 2000, pp. 110-111.
  • Sun, Y. et al., “Temporally resolved growth of InP in the openings off-oriented from [110] direction,” 2000 Int'l Conference on Indium Phosphide and Related Materials, Conf. Proc., pp. 227-230.
  • Sun, Y.T. et al., “InGaAsP multi-quantum wells at 1.5 μm wavelength grown on indium phosphide templates on silicon,” 2003 Int'l Conference on Indium Phosphide and Related Materials, pp. 277-280.
  • Sun, Y.T.; Lourdudoss, S., “Sulfur doped indium phosphide on silicon substrate grown by epitaxial lateral overgrowth,” 2004 Int'l Conference on Indium Phosphide and Related Materials, pp. 334-337.
  • Sun, Y.T.; Napierala, J.; Lourdudoss, S., “Selective area growth of InP on InP precoated silicon substrate by hydride vapor phase epitaxy,” 2002 Int'l Conference on Indium Phosphide and Related Materials, pp. 339-342.
  • Suryanarayanan, G. et al., “Microstructure of lateral epitaxial overgrown InAs on (100) GaAs substrates,” Applied Physics Letters, v 83, n 10, Sep. 8, 2003, pp. 1977-1979.
  • Takasuka et al., “AlGaAs/InGaAs DFB Laser by One-Time Selective MOCVD Growth on a Grating Substrate,” 43 Jap. J. App. Phys. 4B (2004) pp. 2019-2022.
  • Takasuka et al., “InGaAs/AIGaAs Quantum Wire DFB Buried HeteroStructure Laser Diode by One-Time Selective MOCVD on Ridge Substrate,” 44 Jap. J. App. Phys. 4B (2005) pp. 2546-2548.
  • Tamura et al., “Threading Dislocations in GaAs on Pre-patterned Si and in Post-patterned GaAs on Si,” J. Crystal Growth, vol. 147, (1995) pp. 264-273.
  • Tanaka et al., “Structural Characterization of GaN Laterally Overgrown on a (111) Si Substrate,” Applied Physics Letters, vol. 79, No, 7 (Aug. 13, 2001) pp. 955-957.
  • Tomiya, S. et al.., “Dislocation related issues in the degradation of GaN-based laser diodes,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 10, No. 6, pp. 1277-1286, Nov.-Dec. 2004.
  • Tran et al., “Growth and Characterization of InP on Silicon by MOCVD,” J. Crystal Growth, vol. 121, (1992) pp. 365-372.
  • Tsang, W. et al., “The heteroepitaxial ridge-overgrown distributed feedback laser,” IEEE Journal of Quantum Electronics, vol. QE-21, No. 6, pp. 519-526, Jun. 1985.
  • Tsaur, B.-Y. et al., “Low-dislocation-density GaAs epilayers grown on Ge-coated Si substrates by means of lateral epitaxial overgrowth,” Applied Physics Letters, v 41, n 4, Aug. 15, 1982, pp. 347-49.
  • Tseng et al., “Effects of Isolation Materials on Facet Formation for Silicon Selective Epitaxial Growth,” 71 Appl. Phys. Letters 16, p. 2328 (1997).
  • Tsuji et al., “Selective Epitaxial Growth of GaAs on Si with Strained Sort-period Superlattices by Molecular Beam Epitaxy under Atomic Hydrogen Irradiation,” J. Vac. Sci. Technol. B., vol. 22, No. 3, (May/Jun. 2004) pp. 1428-1431.
  • Vanamu et al., “Epitaxial Growth of High-quality Ge Films on Nanostructured Silicon Substrates,” Applied Physics Letters, vol. 88, (2006) pp. 204104-1-204104-3.
  • Vanamu et al., “Growth of High Quality Ge/Si1-xGex on Nano-scale Patterned Si Structures,” J. Vac. Sci. Techn. B, vol. 23, No. 4, (Jul./Aug. 2005) pp. 1622-1629.
  • Vanamu et al., “Heteroepitaxial Growth on Microscale Patterned Silicon Structures,” J. Crystal Growth, vol. 280, (2005) pp. 66-74.
  • Vanamu et al., “Improving Ge/SixGe1-x Film Quality through Growth onto Patterned Silicon Substrates,” Advances in Electronics Manufacturing Technology, V-EMT 1:25 (Nov. 8, 2004), pp. 1-4.
  • Vetury et al., “First Demonstration of AIGaN/GaN Heterostructure Field Effect Transistor on GaN grown by lateral epitaxial overgrowth (ELO),” Inst. Phys. Conf. Ser. No. 162: Ch. 5, pp. 177-183.
  • Wemersson et al., “InAs Epitaxial Lateral growth of W Marks,” J. Crystal Growth, vol. 280 (2005) pp. 81-86.
  • Wuu, D.S. et al., “Defect reduction and efficiency improvement of near-ultraviolet emitters via laterally overgrown GaN on a GaN/patterned sapphire template,” Applied Physics Letters, v 89, n 16, Oct. 16, 2006, pp. 161105-1-161105-3.
  • Xie et al., “From Porous Si to Patterned Si Substrate: Can Misfit Strain Energy in a Continuous Heteroepitaxial Film Be Reduced?” J Va. Sci. Technol. B, vol. 8, No. 2, (Mar./Apr. 1990) pp. 227-231.
  • Xu et al., “Spin-filter devices based on resonant tunneling antisymmetrical magnetic semiconductor hybrid structures,” 84 App. Phys. Letters 11, pp. 1955-1957 (2004).
  • Yamaguchi et al., “Analysis for Dislocation Density Reduction in Selective Area Grown GaAs Films on Si Substrates,” Appl. Phys. Lett. vol. 56, No. 1, (Jan. 1, 1990) pp. 27-29.
  • Yamaguchi et al., “GaAs Solar Cells Grown on Si Substrates for Space Use,” Prog. Photovolt.: Res. Appl. 2001; 9:191-201.
  • Yamaguchi et al., “Super-high-efficiency Multi-junction Solar Cells,” Prog. Photovolt.: Res. Appl. 2005; 13:125-132.
  • Yamaguchi et al., “Defect Reduction Effects in GaAs on Si Substrates by Thermal Annealing,” Appl. Phys. Letters 53(23), p. 2293 (1998).
  • Yamamoto et al., “Optimization of InP/Si Heteroepitaxial Growth Conditions Using Organometallic Vapor Phase Epitaxy,” J. Crystal Growth, vol. 96, (1989) pp. 369-377.
  • Yang et al., “High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations,” 2003 IEDM Tech. Dig., pp. 453-456.
  • Yang et al., “Selective Area Deposited Blue GaN-InGaN Multiple-quantum Well Light Emitting Diodes over Silicon Substrates,” Applied Physics Letter, vol. 76, No. 3, (Jan. 17, 2000) pp. 273-275.
  • Yoon et al., “Selective Growth of Ge Islands on Noanometer-scale Patterned SiO2/Si Substrate by Molecular Beam Epitaxy,” Applied Physics Letters, vol. 89 (2006) pp. 063107-1-063107-3.
  • Zamir et al., “Thermal Microcrack Distribution Control in GaN Layers on Si Substrates by Lateral Confined Epitaxy,” Applied Physics Letters, vol. 78, No. 3, (Jan. 15, 2001) pp. 288-290.
  • Zang, K.Y. et al., “Nanoheteroepitaxial lateral overgrowth of GaN on nanoporous Si(111),” Applied Physics Letters, v 88, n 14, Apr. 3, 2006, p. 141925.
  • Zang, K.Y. et al., “Nanoscale lateral epitaxial overgrowth of GaN on Si (111),” Applied Physics Letters, v 87, Nov. 7, 2005, p. 193106-1-193106-3.
  • Zela et al., “Single-crystalline Ge Grown Epitaxially on Oxidized and Reduced Ge/Si (100) Islands,” J. Crystal Growth, vol. 263 (2004) pp. 90-93.
  • Zhang et al., “Removal of Threading Dislocations from Patterned Heteroepitaxial Semiconductors by Glide to Sidewalls,” J. Electronic Materials, vol. 27, No. 11, (1998) pp. 1248-1253.
  • Zhang et al., “Strain Status of Self-assembled InAs Quantum Dots,” Applied Physics Letters, vol. 77, No. 9, (Aug. 28, 2000) pp. 1295-1297.
  • Zheleva, T.S.; Ok-Hyun Nam; Ashmawi, W.M.; Griffin, J.D.; Davis, R.F., “Lateral epitaxy and dislocation density reduction in selectively grown GaN structures,” J. Crystal Growth, v 222, n 4, Feb. 2001, pp. 706-718.
  • Zubia et al., “Initial Nanoheteroepitaxial Growth of GaAs on Si(100) by OMVPE.” J. Electronic Materials, vol. 30, No. 7, (2001) pp. 812-816.
  • Intel Press Release, “Intel's Tri-Gate Transistor to Enable Next Era in Energy-Efficient Performance,” Intel Corporation (Jun. 12, 2006).
  • Hammerschmidt, “Intel to Use Trigate Transistors from 2009 on,” EETIMES Online, available at: http://www.eetimes.com/showArticle.jhtml?articleID=189400035 (Jun. 12, 2006).
  • Lammers, “Trigate and High-kstack up vs. planar,” EETIMES Online, available at: http://www.eetimes.com/showArticle.jhtml?articleID=188703323&pgno=2&printable=true (Jun. 12, 2006).
  • Intel to Develop Tri-Gate Transistors Based Processors, available at: http://news.techwhack.com/3822/tri-gate-transistors/ (Jun. 13, 2006).
  • Ames, “Intel Says More Efficient Chips are Coming,” PC World, available at: http://www.pcworld.com/printable/article/id,126044/printable.html (Jun. 12, 2006).
  • Bergman et al., “RTD/CMOS Nanoelectronic Circuits: Thin-Film InP-based Resonant Tunneling Diodes Integrated with CMOS circuits,” 20 Electron Device Letters 3, pp. 119-122 (1999).
  • Cloutier et al., “Optical gain and stimulated emission in periodic nanopatterned crystalline silicon,” Nature Materials, Nov. 2005.
  • Feng et al., “Integration of Germanium-on-Insulator and Silicon MOSFETs on a Silicon Substrate,” 27 Electron Device Letters 11, pp. 911-913 (2006).
  • Fischer et al., “Elastic stress relaxation in SiGe epilayers on patterned Si substrates,” 75 Journal of Applied Physics 1, pp. 657-659 (1994).
  • Fischer et al., “State of stress and critical thickness of Strained small-area SiGe layers,” Phys. Stat. Sol. (a) 171, pp. 475-485 (1999).
  • Fitzgerald et al., “Structure and recombination in InGaAs/GaAs heterostructures,” 63 Journal of Applied Physics 3, pp. 693-703 (1988).
  • Fitzgerald et al., “Totally relaxed GexSi1-x layers with low threading dislocation densities grown on Si Substrates,” 59 Applied Physics Letters 7, pp. 811-813 (1991).
  • Gibbon et al., “Selective-area low-pressure MOCVD of GaInAsP and related materials on planar InP substrates” Semicond Sci Tech. 8, pp. 998-1010 (1993).
  • International Preliminary Report on Patentability for International Application No. PCT/US2006/019152, dated Nov. 20, 2007.
  • International Search Report and Written Opinion for International Application PCT/US2007/007373, dated Oct. 5, 2007.
  • Ismail et al., “High-quality GaAs on sawtooth-patterned Si substrates,” 59 Applied Physics Letters 19, pp. 2418-2420 (1991).
  • Jain et al., “Stresses in strained GeSi stripes and quantum structures: calculation using the finite element method and determination using micro-Raman and other measurements,” Thin Solid Films 292 (1997) pp. 218-226.
  • Neumann et a., “Growth of III V resonant tunneling diode,” J. of Crystal Growth (2003).
  • Prost, W., ed. QUDOS Technical Report 2002-2004.
  • Sun et al., “Thermal strain in Indium Phosphide on silicon obtained by Epitaxial Lateral Overgrowth,” 94 J. of Applied Physics 4, pp. 2746-2748 (2003).
  • Usuda et al., “Strain relaxation of strained-Si layers on SiGe-on-insulator (SGOI) structures after mesa isolation,” Applied Surface Sci. 224, pp. 113-116 (2004).
  • Usui et al., “Thick GaN Epitaxial Growth with Low Dislocation Density by Hydride Vapor Phase Epitazy,” 36 Jap. J. of Applied Physics, pp. L899-L902 (1997).
  • Vescan et al., “Lateral confinement by low pressure chemical vapor deposition-based selective epitaxial growth of Si1-xGex/Si nanostructures,” 81 J. of Applied Physics 10, pp. 6709-6715 (1997).
  • Choi et al., “Monolithic Integration of Si MOSFET's and GaAs MESFET's,” Electron Device Letters, v. EDL-7, No. 4 (1986).
  • Choi et al., “Monolithic Integration of GaAs/AIGaAs Double-Heterostructure LED's and Si MOSFET's,” Electon Device Letters, v. EDL-7, No. 9 (1986).
  • Choi et al., “Monolithic Integration of GaAs/AIGaAs LED and Si Driver Circuit,” 9 Electron Device Letters 10 (1988).
  • Fiorenza et al., “Film Thickness Constraints for Manufacturable Strained Silicon CMOS,” 19 Semiconductor Sci. Technol., pp. L4 (2004).
  • Hu et al., “Growth of Well-Aligned Carbon Nanotube arrays on Silicon Substrates using Porous Alumina Film as a Nanotemplate,” 79 App. Physics Letters 19 (2001).
  • International Search Report and Written Opinion for International Application No. PCT/US2007/020181, dated Jan. 25, 2008.
  • International Search Report and Written Opinion for International Application No. PCT/US07/020777, mailed Feb. 8, 2008.
  • International Search Report and Written Opinion for International Application No. PCT/US2007/019568, mailed Feb. 6, 2008.
  • Rosenblad et al., “A Plasma Process for Ultrafast Deposition of SiGe Graded Buffer Layers,” 76 Applied Physics Letters 4, pp. 427-429 (2000).
  • Shichijo et al., “Co-Integration of GaAs MESFET & Si CMOS Circuits,” 9 Elec. Device. Letters 9 (1988).
  • Tamura et al., “Heteroepitaxy on high-quality GaAs on Si for Optical Interconnections on Si Chip,” Proceedings of the SPIE, vol. 2400, pp. 128-139 (1995).
  • IPRP for International Application No. PCT/US2006/029247, mailed Feb. 7, 2008.
  • Bean et al., “GexSi1-x/Si strained-later superlattice grown by molecular beam epitaxy,” J. Vac. Sci. Tech. A (2)2, pp. 436-440 (1984).
  • Blakeslee, “The Use of Superlattices to Block the Propogation of Dislocations in Semiconductors,” Mat. Res. Soc. Symp. Proc. 148, pp. 217-227.
  • Currie et al., “Carrier Mobilities and Process Stability of Strained Si n- and p-MOSFETs on SiGe Virtual Substrates,” J. Vac. Sci. Tech. B 19(6), pp. 2268-2279 (2001).
  • Donaton et al., “Design and Fabrication of MOSFETs with a Reverse Embedded SiGe (Rev. e-SiGe) Structure,” 2006 IEDM, pp. 465-468.
  • International Technology Roadmap for Semiconductors- Front End Processes, pp. 1-62 (2005).
  • IPRP for International Application No. PCT/US2006/033859, mailed Mar. 20, 2008.
  • Matthews et al., “Defects in Epitaxial Multilayers- Misfit Dislocations,” J. Crystal Growth 27, pp. 118-125(1974).
  • Pidin et al., “MOSFET Current Drive Optimization Using Silicon Nitride Capping Layer for 65-nm Technology Node,” 2004 Symp. On VLSI Technology, Dig. Tech. Papers, pp. 54-55.
  • Rim et al., “Enhanced Hole Mobilities in Surface-channel Strained-Si p-MOSFETs,” 1995 IEDM, pp. 517-520.
  • Thean et al., “Uniaxial-Biaxial Hybridization for Super-Critical Strained-Si Directly on Insulator (SC-SSSOI) PMOS with Different Channel Orientations,” IEEE, pp. 1-4 (2005).
  • Thompson et al., “A Logic Nanotechnology Featuring Strained-Silicon,” 25 IEEE Electron Device Letters 4, pp. 191-193 (2004).
  • Yin et al., “Ultrathin Strained-SOI by Stress Balance on Compliant Substrates and FET Performance,” 52 IEEE Trans. on Electron Devices 10, pp. 2207-2214 (2005).
  • International Preliminary Report on Patentability for International Application No. PCT/US2007/019568, mailed Mar. 19, 2009 (7 pages).
  • International Preliminary Report on Patentability for International Application No. PCT/US07/021023, mailed Apr. 9, 2009 (8 pages).
  • International Preliminary Report on Patentability for International Application No. PCT/US2007/020181, mailed Apr. 2, 2009 (9 pages).
  • International Preliminary Report on Patentability for International Application No. PCT/US07/020777, mailed Apr. 9, 2009 (12 pages).
  • International Search Report and Written Opinion for International Application No. PCT/US07/022392, mailed Apr. 11, 2008 (20 pages).
  • Examination Report in European Patent Application No. 06800414.2, mailed Mar. 5, 2009 (3 pages).
  • Partial International Search Report for International Application No. PCT/US2008/068377, mailed Apr. 7, 2009 (7 pages).
  • Bogumilowicz et al., “Chemical vapour etching of Si, SiGe and Ge with HCI; applications to the formation of thin relaxed SiGe buffers and to the revelation of threading dislocations,” Semicond. Sci. & Tech. 20, pp. 127-134 (2005).
  • Campo et al., “Comparison of etching processes of silicon and germanium in SF6 -O2 radio-frequency plasma, ” 13 J. Vac. Sci. Tech. B 2, pp. 235-241 (1995).
  • International Preliminary Report on Patentability for International Application No. PCT/US07/022392, mailed Apr. 30, 2009 (14 pages).
  • International Search Report and Written Opinion for International Application No. PCT/US2008/068377, mailed Jul. 6, 2009 (19 pages).
  • Oehrlein et al., “Studies of the reactive ion etching of SiGe alloys, ” 9 J. Vac. Sci. Tech. A 3, pp. 768-774 (1991).
  • Partial International Search Report for International Application No. PCT/US2008/004564, mailed Jul. 30, 2009 (9 pages).
  • Williams et al., “Etch rates for micromachining processing, ” 5 J. Microelectromechanical Sys, 4, pp. 256-269 (1996).
  • Williams et al., “Etch rates for micromachining processing—Part II, ” 12 J. Microelectromechanical Sys. 6, pp. 761-777 (2003).

Patent History

Patent number: 7799592
Type: Grant
Filed: Sep 26, 2007
Date of Patent: Sep 21, 2010
Patent Publication Number: 20080073667
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. (Hsin-Chu)
Inventor: Anthony J. Lochtefeld (Somerville, MA)
Primary Examiner: Charles D Garber
Assistant Examiner: Yasser A Abdelaziez
Attorney: Slater & Matsil, L.L.P.
Application Number: 11/861,931