Layer Is A Group Iii-v Semiconductor Compound Patents (Class 257/189)
  • Patent number: 10804101
    Abstract: A semiconductor structure including a substrate and a nucleation layer over the substrate. The semiconductor structure further includes a first III-V layer over the nucleation layer, wherein the first III-V layer includes a first dopant type. The semiconductor structure further includes one or more sets of III-V layers over the first III-V layer. Each set of the one or more sets of III-V layers includes a lower III-V layer, wherein the lower III-V layer has a second dopant type opposite the first dopant type, and an upper III-V layer on the lower III-V layer, wherein the upper III-V layer has the first dopant type. The semiconductor structure further includes a second III-V layer over the one or more sets of III-V layers, the second III-V layer having the second dopant type.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai
  • Patent number: 10770500
    Abstract: A solid state imaging device having a light sensing section that performs photoelectric conversion of incident light includes: an insulating layer formed on a light receiving surface of the light sensing section; a layer having negative electric charges formed on the insulating layer; and a hole accumulation layer formed on the light receiving surface of the light sensing section.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 8, 2020
    Assignee: Sony Corporation
    Inventors: Itaru Oshiyama, Takashi Ando, Susumu Hiyama, Tetsuji Yamaguchi, Yuko Ohgishi, Harumi Ikeda
  • Patent number: 10749021
    Abstract: A GaN-based enhancement-mode power electronic device and a method for manufacturing the same. The GaN-based enhancement-mode power electronic device comprises: a substrate; a thin barrier Al(In,Ga)N/GaN heterostructure formed on the substrate; a gate, a source, and a drain formed on the thin barrier Al(In,Ga)N/GaN heterostructure. An AlN or SiNx passivation layer is formed on access regions between the gate and the source and between the gate and the drain, respectively, such that two dimensional electron gas is recovered in channels of the thin barrier Al(In,Ga)N/GaN heterostructure below the MN passivation layer by utilizing the MN passivation layer having polarization characteristics, or by using the SiNx passivation layer with positive fixed bulk/interface charges, so as to reduce on-resistance of the device and inhibit high-voltage current collapse in the device.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: August 18, 2020
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Sen Huang, Xinyu Liu, Xinhua Wang, Ke Wei
  • Patent number: 10746592
    Abstract: According to the present invention, a method for manufacturing a rear surface incident type light receiving device including a substrate, a light receiving unit formed on a surface of the substrate and an electrode formed on the light receiving unit and electrically connected to the light receiving unit includes a first step of performing, after formation of a part of the electrode, a characteristic inspection of the rear surface incident type light receiving device by applying a probe to a part of the electrode and a second step of reducing an area of the electrode in a plan view.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 18, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yasuo Nakajima
  • Patent number: 10644128
    Abstract: A semiconductor device includes a channel layer, a first barrier layer, a second barrier layer, a source electrode, a drain electrode and a gate structure. The channel layer, the first barrier layer, and the second barrier layer are sequentially stacked over a substrate. The source electrode, a drain electrode and the gate structure extend through at least portions of the second barrier layer. The source electrode, the drain electrode and the gate structure have respective bottom surfaces located at substantially the same level as and adjacent to the first barrier layer.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: May 5, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventor: Chih-Yen Chen
  • Patent number: 10580815
    Abstract: A solid state imaging device including: a pixel region that is formed on a light incidence side of a substrate and to which a plurality of pixels that include photoelectric conversion units is arranged; a peripheral circuit unit that is formed in a lower portion in the substrate depth direction of the pixel region and that includes an active element; and a light shielding member that is formed between the pixel region and the peripheral circuit unit and that shields the incidence of light, emitted from an active element, to the photoelectric conversion unit.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: March 3, 2020
    Assignee: SONY CORPORATION
    Inventors: Shoji Kobayashi, Yoshiharu Kudoh, Takuya Sano
  • Patent number: 10566429
    Abstract: A semiconductor device is disclosed, comprising: a substrate; a semiconductor layer disposed on the substrate; a source electrode and a drain electrode disposed on the semiconductor layer, and a gate electrode disposed between the source electrode and the drain electrode; a dielectric layer disposed on at least a part of the surface of the semiconductor layer which is between the gate electrode and the drain electrode, the dielectric layer having at least a recess therein; and a source field plate disposed on the dielectric layer and at least partially covering the recess, the source field plate being electrically connected to the source electrode through at least a conductive path, wherein a part of the source field plate above the gate electrode has a varying distance from an upper surface of the semiconductor layer. A method of manufacturing such a semiconductor device is also disclosed.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: February 18, 2020
    Assignee: DYNAX SEMICONDUCTOR, INC.
    Inventors: Naiqian Zhang, Fengli Pei, Xinchuan Zhang
  • Patent number: 10460937
    Abstract: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: October 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Cheng-Wei Cheng, Kunal Mukherjee, John A. Ott, Devendra K. Sadana, Brent A. Wacaser
  • Patent number: 10439082
    Abstract: The photodetector includes a photon absorbing region formed by a first semiconductor material having a first bandgap energy value. It also includes a blocking region formed by at least second and third semiconductor materials configured to prevent the majority charge carriers from passing between the photon absorbing region and a contact region, the second semiconductor material presenting a second bandgap energy value higher than the first bandgap energy value to form a quantum well with the third semiconductor material. The blocking region is doped.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: October 8, 2019
    Assignee: SOCIETE FRANCAISE DE DETECTEURS INFRAROUGES—SOFRADIR
    Inventors: Laurent Rubaldo, Nicolas Pere Laperne, Alexandre Kerlain, Alexandru Nedelcu
  • Patent number: 10374392
    Abstract: Optical devices having a structured active region configured for selected wavelengths of light emissions are disclosed.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: August 6, 2019
    Assignee: Soraa Laser Diode, Inc.
    Inventor: James W. Raring
  • Patent number: 10269565
    Abstract: The present document discloses a semiconductor device structure (1) comprising a SiC substrate (11), an Inx1Aly1Ga1-x1-y1N buffer layer (13), wherein x1=0-1, y1=0-1 and x1+y1=1, and an Inx2Aly2Ga1-x2-y2N nucleation layer (12), wherein x2=0-1, y2=0-1 and x2+y2=1, sandwiched between the SiC substrate (11) and the buffer layer (13). The buffer layer (13) presents a rocking curve with a (102) peak having a FWHM below 250 arcsec, and the nucleation layer (12) presents a rocking curve with a (105) peak having a FWHM below 200 arcsec, as determined by X-ray Diffraction (XRD). Methods of making such a semiconductor device structure are disclosed.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: April 23, 2019
    Assignee: SWEGAN AB
    Inventors: Erik Janzén, Jr-Tai Chen
  • Patent number: 10230018
    Abstract: A substrate used for III-V-nitride growth and a manufacturing method thereof, the manufacturing method including the following steps: 1) providing a growth substrate, and forming on the surface of the growth substrate a buffer layer used for subsequent growth of a luminescent epitaxial structure; 2) forming a semiconductor dielectric layer on the surface of the buffer layer; 3) by a photolithography process, etching a plurality of semiconductor dielectric protrusions arranged at intervals on the semiconductor dielectric layer, and exposing the buffer layer between the semiconductor dielectric protrusions. This method ensures the crystal quality of the grown luminescent epitaxial structure and also raises the luminescent efficiency of a light-emitting diode. The process is simple, advantageous for reducing cost of manufacture, and suitable for use in industrial production.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: March 12, 2019
    Assignee: CHIP FOUNDATION TECHNOLOGY LTD.
    Inventors: Maosheng Hao, Genru Yuan, Ming Xi, Yue Ma
  • Patent number: 10217900
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to light emitting diode (LED) structures and methods of manufacture. The method includes: forming a buffer layer on a substrate, the buffer layer having at least a lattice mismatch with the substrate; and relaxing the buffer layer by pixelating the buffer layer into discrete islands, prior to formation of a quantum well.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: February 26, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Deepak K. Nayak, Srinivasa R. Banna, Ajey P. Jacob
  • Patent number: 10199222
    Abstract: The present document discloses a semiconductor device structure (1) comprising a SiC substrate (11), an Inx1Aly1Ga1-x1-y1N buffer layer (13), wherein x1=0-1, y1=0-1 and x1+y1=1, and an Inx2Aly2Ga1-x2-y2N nucleation layer (12), wherein x2=0-1, y2=0-1 and x2+y2=1, sandwiched between the SiC substrate (11) and the buffer layer (13). The buffer layer (13) presents a rocking curve with a (102) peak having a FWHM below 250 arcsec, and the nucleation layer (12) presents a rocking curve with a (105) peak having a FWHM below 200 arcsec, as determined by X-ray Diffraction (XRD). Methods of making such a semiconductor device structure are disclosed.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: February 5, 2019
    Assignee: SWEGAN AB
    Inventors: Erik Janzén, Jr-Tai Chen
  • Patent number: 10153362
    Abstract: In an embodiment, a semiconductor device includes an enhancement mode Group III-nitride-based High Electron Mobility Transistor (HEMT) including a drain, a gate, a barrier layer, a channel layer, a barrier layer arranged on the channel layer, and a heterojunction formed between the barrier layer and the channel layer and capable of supporting a two-dimensional electron gas (2DEG). At least one of a thickness and a composition of the barrier layer is configured to decrease a 2DEG density in a channel region compared with a 2DEG density outside of the channel region, wherein the channel region is arranged under the gate and extends a distance d beyond a drain-sided gate edge.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: December 11, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Oliver Haeberlen
  • Patent number: 10134937
    Abstract: A semiconductor photodiode, including a light-absorbing layer; an optical waveguide via which light can evanescently be coupled into the light-absorbing layer, and a doped contact layer arranged between the light-absorbing layer and the optical waveguide. The optical waveguide at least sectionally has a doping which produces a diffusion barrier counteracting a diffusion of dopant of the contact layer into the optical waveguide.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: November 20, 2018
    Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
    Inventors: Patrick Runge, Tobias Beckerwerth, Sten Seifert
  • Patent number: 10026804
    Abstract: A semiconductor device according to an embodiment includes: a first GaN based semiconductor layer; a second GaN based semiconductor layer disposed on the first GaN based semiconductor layer and having a bandgap larger than that of the first GaN based semiconductor layer; a source electrode disposed on the second GaN based semiconductor layer; a drain electrode disposed on the second GaN based semiconductor layer; a p-type third GaN based semiconductor layer disposed between the source electrode and the drain electrode on the second GaN based semiconductor layer; a gate electrode disposed on the third GaN based semiconductor layer; and a p-type fourth GaN based semiconductor layer disposed between the gate electrode and the drain electrode on the second GaN based semiconductor layer and disposed separated from the third GaN based semiconductor layer.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: July 17, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Kuraguchi, Hisashi Saito
  • Patent number: 10026817
    Abstract: A microelectronic device contains a high performance silicon nitride layer which is stoichiometric within 2 atomic percent, has a low stress of 600 MPa to 1000 MPa, and has a low hydrogen content, less than 5 atomic percent, formed by an LPCVD process. The LPCVD process uses ammonia and dichlorosilane gases in a ratio of 4 to 6, at a pressure of 150 millitorr to 250 millitorr, and at a temperature of 800° C. to 820° C.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: July 17, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Nicholas Stephen Dellas
  • Patent number: 9954087
    Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: April 24, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
  • Patent number: 9932688
    Abstract: The present techniques provide a method for producing a Group III nitride semiconductor single crystal that is designed to grow a semiconductor single crystal with high reproducibility. The method for producing a Group III nitride semiconductor single crystal comprises adding a seed crystal substrate, Ga, and Na into a crucible, and growing a Group III nitride semiconductor single crystal. In the growth of the Group III nitride semiconductor single crystal, a measuring device is used to detect the reaction of Ga with Na. Ga is reacted with Na with the temperature of the crucible adjusted within a first temperature range of 80° C. to 200° C. After the measuring device detected the reaction of Ga with Na, the temperature of the crucible is elevated up to a growth temperature of the Group III nitride semiconductor single crystal.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: April 3, 2018
    Assignee: TOYODA GOSEI CO., LTD.
    Inventor: Miki Moriyama
  • Patent number: 9893227
    Abstract: A photodiode for detecting photons comprising a substrate; first semiconducting region suitable for forming a contact thereon; a first contact; a second semiconducting region comprising an absorption region for the photons and being formed of a semiconductor having one or more of a high surface recombination velocity or a high interface recombination velocity; a second contact operatively associated with the second region; the first semiconducting region and the second semiconducting region forming a first interface; the second semiconducting region being configured such that reverse biasing the photodiode between the first and second contacts results in the absorption region having a portion depleted of electrical carriers and an undepleted portion at the reverse bias point of operation; the undepleted portion being smaller than the absorption depth for photons; whereby the depletion results in the creation of an electric field and photogenerated carriers are collected by drift; and a method of making.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: February 13, 2018
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Anand Venktesh Sampath, Michael Wraback, Paul Shen
  • Patent number: 9870918
    Abstract: The present invention discloses an InGaAs film grown on a Si substrate, which comprises a Si substrate, a low temperature In0.4Ga0.6As buffer layer, a high temperature In0.4Ga0.6As buffer layer and an In0.53Ga0.47As epitaxial film, arranged sequentially, wherein the low temperature In0.4Ga0.6As buffer layer is an In0.4Ga0.6As buffer layer grown at the temperature of 350˜380° C.; the high temperature In0.4Ga0.6As buffer layer is an In0.4Ga0.6As buffer layer grown at the temperature of 500˜540° C., and the sum of the thickness of the low temperature In0.4Ga0.6As buffer layer and the thickness of the high temperature In0.4Ga0.6As buffer layer is 10˜20 nm. The invention further discloses a method for preparing the InGaAs film. The InGaAs film grown on the Si substrate of the present invention has good crystal quality, is almost completely relaxed, and has a simple preparation process.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: January 16, 2018
    Assignee: SOUTH CHINA UNIVERSITY OF TECHNOLOGY
    Inventors: Guoqiang Li, Fangliang Gao, Yunfang Guan, Lei Wen, Jingling Li, Shuguang Zhang
  • Patent number: 9853107
    Abstract: An embodiment includes a III-V material based device, comprising: a first III-V material based buffer layer on a silicon substrate; a second III-V material based buffer layer on the first III-V material based buffer layer, the second III-V material including aluminum; and a III-V material based device channel layer on the second III-V material based buffer layer. Another embodiment includes the above subject matter and the first and second III-V material based buffer layers each have a lattice parameter equal to the III-V material based device channel layer. Other embodiments are included herein.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: December 26, 2017
    Assignee: Intel Corporation
    Inventors: Matthew V. Metz, Jack T. Kavalieros, Gilbert Dewey, Willy Rachmady, Benjamin Chu-Kung, Marko Radosavljevic, Han Wui Then, Ravi Pillarisetty, Robert S. Chau
  • Patent number: 9818872
    Abstract: A method of semiconductor device fabrication is described that includes forming a fin extending from a substrate and having a source/drain region and a channel region. The fin includes a first epitaxial layer having a first composition and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second composition. The second epitaxial layer is removed from the source/drain region of the fin to form a gap. The gap is filled with a dielectric material. Another epitaxial material is formed on at least two surfaces of the first epitaxial layer to form a source/drain feature.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Carlos H. Diaz, Chih-Hao Wang, Wai-Yi Lien, Ying-Keung Leung
  • Patent number: 9780659
    Abstract: In general, according to one embodiment, a semiconductor device includes a device main body, a semiconductor substrate. The device main body includes a semiconductor substrate mounting part and a first conductor provided around the semiconductor substrate mounting part. The semiconductor substrate includes a DC-to-DC converter control circuit having a detector to detect at least one of a current flowing through the first conductor and a voltage supplied to the first conductor. The semiconductor substrate is disposed on the semiconductor substrate mounting part so that the detector comes close to the first conductor.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: October 3, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Saito, Ryo Wada, Yuichi Goto
  • Patent number: 9761672
    Abstract: There are disclosed herein various implementations of a semiconductor component including one or more aluminum silicon nitride layers. The semiconductor component includes a substrate, a group III-V intermediate body situated over the substrate, a group III-V buffer layer situated over the group III-V intermediate body, and a group III-V device fabricated over the group III-V buffer layer. The group III-V intermediate body includes the one or more aluminum silicon nitride layers.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: September 12, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Scott Nelson, Srinivasan Kannan
  • Patent number: 9721792
    Abstract: Implementations described herein generally relate to methods for relaxing strain in thin semiconductor films grown on another semiconductor substrate that has a different lattice constant. Strain relaxation typically involves forming a strain relaxed buffer layer on the semiconductor substrate for further growth of another semiconductor material on top. Whereas conventionally formed buffer layers are often thick, rough and/or defective, the strain relaxed buffer layers formed using the implementations described herein demonstrate improved surface morphology with minimal defects.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: August 1, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yi-Chiau Huang, Yihwan Kim
  • Patent number: 9677192
    Abstract: A group 13 nitride crystal substrate according to the present invention is produced by growing a group 13 nitride crystal on a seed-crystal substrate by a flux method, wherein a content of inclusions in the group 13 nitride crystal grown in a region of the seed-crystal substrate except for a circumferential portion of the seed-crystal substrate, the region having an area fraction of 70% relative to an entire area of the seed-crystal substrate, is 10% or less, preferably 2% or less.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: June 13, 2017
    Assignee: NGK Insulators, Ltd.
    Inventors: Takanao Shimodaira, Katsuhiro Imai, Makoto Iwai, Takayuki Hirao
  • Patent number: 9660134
    Abstract: A polarization controlled device has a first layer comprising a group III-nitride semiconductor substrate or template; a second group III-nitride semiconductor layer disposed over the group III-nitride semiconductor substrate or template; a third group III-nitride semiconductor layer disposed over the second group III-nitride semiconductor layer; and a fourth group III-nitride semiconductor layer disposed over the third group III-nitride semiconductor layer. A pn junction is formed at an interface between the third and fourth group III-nitride semiconductor layers. A polarization heterojunction is formed between the second group III-nitride semiconductor layer and the third group III-nitride semiconductor layer. The polarization junction has fixed charges of a polarity on one side of the polarization junction and fixed charges of an opposite polarity on an opposite side of the polarization junction.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: May 23, 2017
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: John E. Northrup, Thomas Wunderer, Jeng Ping Lu, Noble M Johnson
  • Patent number: 9601610
    Abstract: A HEMT device comprising a M-plane III-Nitride material substrate, a p-doped epitaxial layer of III-Nitride material grown on said substrate; a recess etched in said p-doped epitaxial layer, the recess having a plane wall parallel to a polar plane of the III-Nitride material; a carrier carrying layer formed on said plane wall of the recess; a carrier supply layer formed on said at least one carrier carrying layer, such that a 2DEG region is formed in the carrier carrying layer at the interface with the carrier supply layer along said plane wall of the recess; a doped source region formed at the surface of said p-doped epitaxial layer such that the doped source region is separated from said 2DEG region by a channel region; a gate insulating layer formed on the channel region; and a gate contact layer formed on the gate insulating layer.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: March 21, 2017
    Assignee: HRL Laboratories, LLC
    Inventor: Sameh G. Khalil
  • Patent number: 9601895
    Abstract: A laser system includes first and second mirrors, a semiconductor laser and a high frequency pulse generator. The semiconductor laser generates optical power within an optical cavity and reflects the optical power between the first mirror and second mirrors. The optical power has a frequency of foriginal-laser. The high frequency pulse generator generates a high frequency pulse with a rise time greater than an optical cycle of the optical power within the optical cavity and directly impinges the high frequency pulse on the optical power within the optical cavity. Impinging the high frequency pulse on the optical power within the optical cavity causes a frequency shift of the optical power to generate a final laser frequency that is greater than foriginal-laser as well as beyond a frequency band of the second mirror to cause a final laser to be emitted past the second mirror and from the semiconductor laser.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: March 21, 2017
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Idan Mandelbaum, Konstantinos Papadopoulos
  • Patent number: 9559161
    Abstract: A compound semiconductor device includes a III-nitride buffer and a III-nitride barrier on the III-nitride buffer. The III-nitride barrier has a different band gap than the III-nitride buffer so that a two-dimensional charge carrier gas channel arises along an interface between the III-nitride buffer and the III-nitride barrier. The compound semiconductor device further includes a source and a drain spaced apart from one another and electrically connected to the two-dimensional charge carrier gas channel, a gate for controlling the two-dimensional charge carrier gas channel between the source and the drain, and a patterned III-nitride back-barrier buried in the III-nitride buffer. The patterned III-nitride back-barrier extends laterally beyond the gate towards the drain and terminates prior to the drain so that the patterned III-nitride back-barrier is laterally spaced apart from the drain by a region of the III-nitride buffer.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: January 31, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Gilberto Curatola
  • Patent number: 9530767
    Abstract: According to one embodiment, a semiconductor light emitting element includes a base body, first to sixth semiconductor layers, a first conductive layer, and a first pad layer. The first semiconductor layer is separated from the base body and includes first and second semiconductor regions arranged with each other. The second semiconductor layer is provided between the second semiconductor region and the base body. The third semiconductor layer is provided between the second semiconductor region and the second semiconductor layer. The fourth semiconductor layer is separated from the base body, arranged with the first semiconductor layer. The fifth semiconductor layer is provided between the base body and one portion of the fourth semiconductor layer. The sixth semiconductor layer is provided between the fifth semiconductor layer and the one portion. The first conductive layer includes first, second, and third conductive regions. The first pad layer includes a first pad region.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: December 27, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jumpei Tajima, Hiroshi Ono, Shunsuke Asaba, Shinya Nunoue
  • Patent number: 9478632
    Abstract: A method of making a semiconductor device includes epitaxially growing a channel layer over a substrate. The method further includes depositing an active layer over the channel layer. Additionally, the method includes forming a gate structure over the active layer, the gate structure configured to deplete a 2DEG under the gate structure, the gate structure including a dopant. Furthermore, the method includes forming a barrier layer between the gate structure and the active layer, the barrier layer configured to block diffusion of the dopant from the gate structure into the active layer.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: October 25, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chun Liu, Chi-Ming Chen, Chen-Hao Chiang, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 9450001
    Abstract: A light detection system which comprises an active region between a back contact layer and a front contact layer is disclosed. The active region comprises a quantum well structure having a quantum well between quantum barriers, wherein the quantum well comprises foreign atoms that induce an excited bound state at an energy level which is above an energy level characterizing the quantum barriers.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: September 20, 2016
    Assignee: Technion Research & Development Foundation Limited
    Inventors: Asaf Albo, Gad Bahir, Dan Fekete
  • Patent number: 9406530
    Abstract: The present invention provides ART techniques with reduced LER. In one aspect, a method of ART with reduced LER is provided which includes the steps of: providing a silicon layer separated from a substrate by a dielectric layer; patterning one or more ART lines in the silicon layer selective to the dielectric layer; contacting the silicon layer with an inert gas at a temperature, pressure and for a duration sufficient to cause re-distribution of silicon along sidewalls of the ART lines patterned in the silicon layer; using the resulting smoothened, patterned silicon layer to pattern ART trenches in the dielectric layer; and epitaxially growing a semiconductor material up from the substrate at the bottom of each of the ART trenches, to form fins in the ART trenches.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: August 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Guy Cohen, Katherine L. Saenger, Kuen-Ting Shiu
  • Patent number: 9397243
    Abstract: Various embodiments of a germanium-on-silicon (Ge—Si) avalanche photodiode are provided. In one aspect, the Ge—Si avalanche photodiode utilizes a silicon carrier-energy-relaxation layer to reduce the energy of holes drifting into absorption layer where the absorption material has lower ionization threshold, thereby suppressing multiplication noise and increasing the gain-bandwidth product of the avalanche photodiode.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: July 19, 2016
    Assignee: SIFOTONICS TECHNOLOGIES CO., LTD.
    Inventors: Tuo Shi, Mengyuan Huang, Pengfei Cai, Su Li, Ching-yin Hong, Wang Chen, Liangbo Wang, Dong Pan
  • Patent number: 9142688
    Abstract: A GaN-based diode may include an intrinsic GaN-based semiconductor layer, GaN-based semiconductor layers configured to have a first conductivity type and bonded to the intrinsic GaN-based semiconductor layer. A first electrode made of metal is placed on a surface opposite a surface bonded to the GaN-based semiconductor layers of the intrinsic GaN-based semiconductor layer; a second electrode is placed on a surface opposite to a surface bonded to the intrinsic GaN-based semiconductor layer of the GaN-based semiconductor layers of the first conductivity type. Voltage-resistant layers configured to have a second conductivity type are formed in regions of the intrinsic GaN-based semiconductor layer that come in contact with edges of the first electrode.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: September 22, 2015
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Motonobu Takeya, Kang Nyung Lee
  • Patent number: 9035351
    Abstract: A semiconductor device having a p base region and an n+ emitter region that come into contact with an emitter electrode and are selectively provided in a surface layer of an n? drift layer. A gate electrode is provided on a portion of the front surface of the n? drift layer which is interposed between the n+ emitter regions, with a gate insulating film interposed therebetween. In some exemplary embodiments, an n+ buffer layer and a p collector layer which have a higher impurity concentration than the n? drift layer are sequentially provided on a surface of the n? drift layer opposite to the front surface on which the n+ emitter region is provided. The impurity concentration of the n+ buffer layer is equal to or greater than 7×1016 cm?3 and equal to or less than 7×1017 cm?3. Accordingly, it is possible to obtain high field decay resistance.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: May 19, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 9029831
    Abstract: An exemplary light emitting diode includes a substrate and a first undoped gallium nitride (GaN) layer formed on the substrate. The first undoped GaN layer defines a groove in an upper surface thereof. A distributed Bragg reflector is formed in the groove of the first undoped GaN layer. The distributed Bragg reflector includes a plurality of second undoped GaN layers and a plurality of air gaps alternately stacked one on the other. An n-type GaN layer, an active layer and a p-type GaN layer are formed on the distributed Bragg reflector and the first undoped GaN layer. A p-type electrode and an n-type electrode are electrically connected with the p-type GaN layer and the n-type GaN layer, respectively. A method for manufacturing plural such light emitting diodes is also provided.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: May 12, 2015
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Ching-Hsueh Chiu, Ya-Wen Lin, Po-Min Tu, Shih-Cheng Huang
  • Patent number: 8981338
    Abstract: A semiconductor photocathode includes an AlXGa1-XN layer (0?X<1) bonded to a glass substrate via an SiO2 layer and an alkali-metal-containing layer formed on the AlXGa1-XN layer. The AlXGa1-XN layer includes a first region, a second region, an intermediate region between the first and second regions. The second region has a semiconductor superlattice structure formed by laminating a barrier layer and a well layer alternately, the intermediate region has a semiconductor superlattice structure formed by laminating a barrier layer and a well layer alternately. When a pair of adjacent barrier and well layers is defined as a unit section, an average value of a composition ratio X of Al in a unit section decreases monotonously with distance from an interface position between the second region and the SiO2 layer at least in the intermediate region.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: March 17, 2015
    Assignees: Sanken Electric Co., Ltd., Hamamatsu Photonics K.K.
    Inventors: Shunro Fuke, Tetsuji Matsuo, Yoshihiro Ishigami, Tokuaki Nihashi
  • Patent number: 8980674
    Abstract: Provided is a semiconductor image sensor device. The image sensor device includes a semiconductor substrate that includes an array region and a black level correction region. The array region contains a plurality of radiation-sensitive pixels. The black level correction region contains one or more reference pixels. The substrate has a front side and a back side. The image sensor device includes a first compressively-stressed layer formed on the back side of the substrate. The first compressively-stressed layer contains silicon nitride. The image sensor device includes a metal shield formed on the compressively-stressed layer. The metal shield is formed over at least a portion of the black level correction region. The image sensor device includes a second compressively-stressed layer formed on the metal shield and the first compressively-stressed layer. The second compressively-stressed layer contains silicon oxide. A sidewall of the metal shield is protected by the second compressively-stressed layer.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Weng, Hsun-Ying Huang, Yung-Cheng Chang, Jin-Hong Cho
  • Patent number: 8969912
    Abstract: A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, a gate region at least partially surrounding the channel region, having a first surface coupled to the drift region and a second surface on a side of the gate region opposing the first surface, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: March 3, 2015
    Assignee: Avogy, Inc.
    Inventors: Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano, David P. Bour, Richard J. Brown, Thomas R. Prunty
  • Patent number: 8963274
    Abstract: A low noise infrared photo detector with a vertically integrated field effect transistor (FET) structure is formed without thermal diffusion. The FET structure includes a high sensitivity photo detector layer, a charge well layer, a transfer well layer, a charge transfer gate, and a drain electrode. In an embodiment, the photo detector layer and charge well are InGaAs and the other layers are InP layers.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 24, 2015
    Assignee: Sensors Unlimited, Inc.
    Inventor: Peter Dixon
  • Patent number: 8963162
    Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. Each of the source feature and the drain feature comprises a corresponding intermetallic compound at least partially embedded in the second III-V compound layer. Each intermetallic compound is free of Au and comprises Al, Ti or Cu. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A depletion region is disposed in the carrier channel and under the gate electrode.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wei Hsu, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chen-Ju Yu, Po-Chih Chen, King-Yuen Wong
  • Patent number: 8952419
    Abstract: A semiconductor device includes a substrate, a buffer layer on the substrate, and a plurality of nitride semiconductor layers on the buffer layer. The semiconductor device further includes at least one masking layer and at least one inter layer between the plurality of nitride semiconductor layers. The at least one inter layer is on the at least one masking layer.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jo Tak, Jae-won Lee, Young-soo Park, Jun-youn Kim
  • Patent number: 8946771
    Abstract: The present disclosure relates to an enhancement mode gallium nitride (GaN) transistor device. The GaN transistor device has an electron supply layer located on top of a GaN layer. An etch stop layer (e.g., AlN) is disposed above the electron supply layer. A gate structure is formed on top of the etch stop layer, such that the bottom surface of the gate structure is located vertically above the etch stop layer. The position of etch stop layer in the GaN transistor device stack allows it to both enhance gate definition during processing (e.g., selective etching of the gate structure located on top of the AlN layer) and to act as a gate insulator that reduces gate leakage of the GaN transistor device.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wen Hsiung, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chun-Wei Hsu, Chen-Ju Yu, Fu-Chih Yang
  • Patent number: 8941145
    Abstract: Systems and methods for dry eteching a photodetector array based on InAsSb are provided. A method for fabricating an array of photodetectors includes receiving a pattern of an array of photodetectors formed from InAsSb, the pattern including at least one trench defined between adjacent photodetectors, and dry etching the at least one trench with a plasma including BrCl3 and Ar.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: January 27, 2015
    Assignee: The Boeing Company
    Inventor: Pierre-Yves Delaunay
  • Patent number: 8941093
    Abstract: A first electrode, an intrinsic first compound semiconductor layer over the first electrode, a second compound semiconductor layer whose band gap is smaller than that of the first compound semiconductor layer on the first compound semiconductor layer, and a second electrode over the second compound semiconductor layer are provided.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: January 27, 2015
    Assignee: Fujitsu Limited
    Inventor: Tadahiro Imada
  • Patent number: 8937336
    Abstract: Passivation of group III-nitride heterojunction devices is described herein. The passivation facilitates simultaneous realization of effective/high current collapse suppression and low leakage current without the use of a sophisticated multiple-field plate technique. The passivation can be achieved by growing a charge-polarized AlN thin film on the surface of a group III-nitride based heterojunction device by plasma-enhanced atomic layer deposition such that positive polarization charges are induced at the interface to compensate for a majority of negative charges at the interface.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: January 20, 2015
    Assignee: The Hong Kong University of Science and Technology
    Inventors: Jing Chen, Sen Huang, Qimeng Jiang, Zhikai Tang