Abstract: A semiconductor arrangement includes: a substrate; fins formed on the substrate and extending in a first direction; gate stacks formed on the substrate and each extending in a second direction crossing the first direction to intersect at least one of the fins, and dummy gates composed of a dielectric and extending in the second direction; spacers formed on sidewalls of the gate stacks and the dummy gates; and dielectric disposed between first and second ones of the gate stacks in the second direction to electrically isolate the first and second gate stacks. The dielectric is disposed in a space surrounded by respective spacers of the first and second gate stacks which extend integrally. At least a portion of an interval between the first and second gate stacks in the second direction is less than a line interval achievable by lithography in a process of manufacturing the semiconductor arrangement.

Abstract: A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.

Abstract: A transistor device is provided. The transistor device includes a substrate, a channel layer on the substrate, the channel layer including a GaN material, a barrier layer that is on the channel layer and that includes an AlGaN material, a drain electrode that is on the barrier layer in a drain region of the device, a source ohmic structure that is at least partially recessed into the barrier layer in a source region of the device, a source electrode that is on the source ohmic structure and a gate contact that is on the barrier layer and that is in a gate region of the device that is between the drain region and the source region.

Abstract: A method of fabricating a semiconductor device includes providing a substrate including a semiconductor material having a first lattice constant and then patterning the substrate to form a first semiconductor pattern extending in a first direction. A second semiconductor pattern is also formed on and in contact with the first semiconductor pattern. The second semiconductor pattern extends in the first direction and has a second lattice constant that is sufficiently greater than the first lattice constant so that lattice stress is present at an interface between the first semiconductor pattern and the second semiconductor pattern. The second semiconductor pattern is further patterned to define a sidewall of the second semiconductor pattern that extends in a second direction intersecting the first direction. A gate electrode is formed, which extends in the first direction on the second semiconductor pattern.

Abstract: A method for preparing an ohmic contact electrode of a GaN-based device. Said method comprises the following steps: growing a first dielectric layer (203) on an upper surface of a device (S1); implanting silicon ions and/or indium ions in a region of the first dielectric layer (203) corresponding to an ohmic contact electrode region, and in the ohmic contact electrode region of the device (S2); growing a second dielectric layer (206) on an upper surface of the first dielectric layer (203) (S3); activating the silicon ions and/or the indium ions by means of a high temperature annealing process, so as to form an N-type heavy doping (S4); respectively removing portions, corresponding to the ohmic contact electrode region, of the first dielectric layer (203) and the second dielectric layer (206) (S5); growing a metal layer (208) on the upper surface of the ohmic contact electrode region of the device, so as to form an ohmic contact electrode (S6).

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed directly on the shallow recess.

Abstract: A semiconductor device includes a substrate; a first semiconductor layer and a second semiconductor layer, both including a nitride semiconductor; a gate electrode; a source electrode; a drain electrode formed on the second semiconductor layer; and a first insulating film and a second insulating film formed on the second semiconductor layer. The first insulating film is formed on a gate-electrode side and the second insulating film is formed on a drain-electrode side between the gate electrode and the drain electrode. A part of the gate electrode is formed on the first insulating film. The first insulating film and the second insulating film are formed of silicon nitride. The Si—H bond density in the first insulating film is higher than that in the second insulating film. The N—H bond density in the second insulating film is higher than that in the first insulating film.

Abstract: A thin-film transistor is disclosed. The thin-film transistor includes a gate electrode disposed on a substrate, an oxide semiconductor layer disposed so as to overlap at least a portion of the gate electrode in the state of being isolated from the gate electrode, a gate insulation film disposed between the gate electrode and the oxide semiconductor layer, a source electrode connected to the oxide semiconductor layer, and a drain electrode connected to the oxide semiconductor layer in the state of being spaced apart from the source electrode, wherein the oxide semiconductor layer includes indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O), the content of indium (In) in the oxide semiconductor layer is greater than the content of gallium (Ga), the content of indium (In) is substantially equal to the content of zinc (Zn), and the content ratio (Sn/In) of tin (Sn) to indium (In) is 0.1 to 0.25.

Abstract: The present disclosure describes a method for forming ultra-thin fins with a tapered bottom profile for improved structural rigidity and gate control characteristics. The method includes forming a fin structure that includes an epitaxial layer portion and a doped region portion surrounded by an isolation region so that a top section of the epitaxial layer portion is above the isolation region. The method also includes depositing a silicon-based layer on the top portion of the epitaxial layer above the isolation region and annealing the silicon-based layer to reflow the silicon-based layer. The method further includes etching the silicon-based layer and the fin structure above the isolation region to form a first bottom tapered profile in the fin structure above the isolation region and annealing the fin structure to form a second bottom tapered profile below the first bottom tapered profile and above the isolation region.

Abstract: A normally-off heterojunction field-effect transistor is provided, including a superposition of a first layer, of III-N type, and of a second layer, of III-N type, so as to form a two-dimensional electron gas; a stack of an n-doped third layer making electrical contact with the second layer, and of a p-doped fourth layer placed in contact with and on the third layer, a first conductive electrode and a second conductive electrode making electrical contact with the two-dimensional electron gas; a dielectric layer disposed against a lateral face of the fourth layer; and a control electrode separated from the lateral face of the fourth layer by the dielectric layer.

Abstract: A semiconductor module 1 according to one embodiment includes a first circuit board, circuit units and a first plate member; the circuit units include a second plate member, a vertical type transistor and a second circuit board; n first circuit unit of N circuit units electrically connect a back surface side conductive region to the first input interconnection pattern of the first circuit board; (N?n) second circuit unit of the N circuit units electrically connect the third conductive pattern and the fourth conductive pattern of the second circuit board to the first control interconnection pattern and the second input interconnection pattern of the first circuit board; the first plate member electrically connects the fourth conductive pattern of the first circuit units to the second plate member of the second circuit units; and the gate electrode pad of the vertical type transistor contained in the first circuit unit is electrically connected to the first control interconnection pattern of the first circuit b

Abstract: A gate structure includes a gate dielectric layer over a semiconductor workpiece. The gate structure further includes a work function layer over the gate dielectric layer, wherein the work function layer has a U-shape profile. The gate structure further includes an adhesion layer over the work function layer, wherein a surface of the adhesion layer farthest from the work function layer is substantially free of oxygen atoms. The gate structure further includes a conductive layer over the adhesion layer, wherein the conductive layer has an I-shape profile.

Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a gate structure over a substrate, forming an interlayer dielectric structure surrounding the gate structures, and forming a first opening in the gate structure and the interlayer dielectric structure. The first opening has a first portion in the gate structure and a second portion in the interlayer dielectric structure, in which the first portion has a width larger than the second portion. The method further includes depositing a dielectric layer in the first opening and forming a second opening over the first opening. The first portion of the opening remains open and the second portion of the opening is filled after depositing the dielectric layer. The second opening in the gate structure has a depth larger than the first opening in the gate structure.

Abstract: A semiconductor device including an active fin that protrudes from a substrate and forms a plurality of recess regions spaced apart from each other, a gate pattern between the plurality of recess regions that covers a lateral surface and a top surface of the active fin, a plurality of source/drain patterns in the plurality of recess regions, and a diffusion reduction region adjacent to each of a plurality of bottoms of the plurality of recess regions and each of a plurality of sidewalls of the plurality of recess regions, the diffusion reduction region including a dopant having a lower diffusion coefficient than phosphorus (P).

Abstract: A method and structure for mitigating strain loss (e.g., in a FinFET channel) includes providing a semiconductor device having a substrate having a substrate fin portion, an active fin region formed over a first part of the substrate fin portion, a pickup region formed over a second part of the substrate fin portion, and an anchor formed over a third part of the substrate fin portion. In some embodiments, the substrate fin portion includes a first material, and the active fin region includes a second material different than the first material. In various examples, the anchor is disposed between and adjacent to each of the active fin region and the pickup region.

Abstract: A gate-sinking pseudomorphic high electron mobility transistor comprises a compound semiconductor substrate overlaid with an epitaxial structure which includes sequentially a buffer layer, a channel layer, a Schottky layer, and a first cap layer. The Schottky layer comprises from bottom to top at least two stacked regions of semiconductor material. Each of the two adjacent stacked regions differs in material from the other and provides a stacked region contact interface therebetween. In any two adjacent stacked regions of the Schottky layer, one stacked region composed of AlGaAs-based semiconductor material alternates with the other stacked region composed of InGaP-based semiconductor material. A gate-sinking region is beneath the first gate metal layer of the gate electrode, and the bottom boundary of the gate-sinking region is located at the one of the at least one stacked region contact interface of the Schottky layer.

Abstract: A semiconductor memory device including an access transistor configured as a vertical transistor comprises a channel portion and a pair of source/drain regions; a storage capacitor connected to one of the pair of source/drain regions; a bit line connected to the other of the pair of source/drain regions, a first semiconductor layer provided in the source/drain region to which the bit line is connected. Preferably, the first semiconductor layer comprises SiGe.

Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer disposed above the substrate; a second nitride semiconductor layer disposed above the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; a third nitride semiconductor layer selectively disposed above the second nitride semiconductor layer and containing a p-type first impurity element; a high resistance region disposed in the third nitride semiconductor layer, the high resistance region containing a second impurity element and having a specific resistance higher than a specific resistance of the third nitride semiconductor layer; and a gate electrode disposed above the high resistance region, wherein an end of the high resistance region is inside a surface end of the third nitride semiconductor layer.

Abstract: Group III-V semiconductor devices having asymmetric source and drain structures and their methods of fabrication are described. In an example, an integrated circuit structure includes a gallium arsenide layer on a substrate. A channel structure is on the gallium arsenide layer. The channel structure includes indium, gallium and arsenic. A source structure is at a first end of the channel structure and a drain structure is at a second end of the channel structure. The drain structure has a wider band gap than the source structure. A gate structure is over the channel structure.

Abstract: Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a first device region and a second device region; forming a first doped layer on the semiconductor substrate; forming a first fin layer on the first doped layer in the first device region; forming a second fin layer on the first doped layer in the second device region; forming a first isolation layer on the first doped layer in the first device region and covering sidewall surfaces of the first fin layer; forming a second isolation layer on the second doped layer in the second device region and covering portions of sidewall surfaces of the second fin layer and with a thickness smaller than a thickness of the first isolation layer; and forming a first gate structure on the first isolation layer and a second gate structure on the second isolation layer.

Abstract: According to some embodiments, a method for stabilizing electrical properties of a diamond semiconductor comprises terminating a surface of a diamond with hydrogen (H) or deuterium (D) atoms and over-coating the surface of the diamond with an encapsulating material comprising metal oxide salt doped with one or more elements capable of generating negative charge in the metal oxide salt.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a fin structure extending above a substrate, and the fin structure has a first portion and a second portion below the first portion, and the first portion and the second portion are made of different materials. The FinFET device structure includes an isolation structure formed on the substrate, and an interface between the first portion and the second portion of the fin structure is above a top surface of the isolation structure. The FinFET device structure includes a liner layer formed on sidewalls of the second portion of the fin structure.

Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer having a greater band gap than the first nitride semiconductor layer; a source electrode and a drain electrode on the second nitride semiconductor layer apart from each other; a third nitride semiconductor layer, between the source electrode and the drain electrode, containing a p-type first impurity and serving as a gate; and a fourth nitride semiconductor layer, between the third nitride semiconductor layer and the drain electrode, containing a p-type second impurity, wherein the average carrier concentration of the fourth nitride semiconductor layer is lower than the average carrier concentration of the third nitride semiconductor layer.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. First and second gate structures extend over the semiconductor body, a second gate structure that extends over the semiconductor body. A source/drain region is positioned laterally between the first gate structure and the second gate structure. The source/drain region includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer has a first section and a second section. The second semiconductor layer is positioned laterally between the first section of the first semiconductor layer and the second section of the first semiconductor layer.

Abstract: A semiconductor device includes a compound semiconductor layer disposed over a substrate, a protection layer disposed over the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode which penetrate through the protection layer and are disposed on the compound semiconductor layer. The semiconductor device also includes a gate field plate connecting the gate electrode and disposed over a portion of the protection layer between the gate electrode and the drain electrode. The gate field plate has an extension portion extending into the protection layer.

Abstract: A semiconductor device includes: a drift layer; a mesa region that is interposed between adjacent trenches on the drift layer; a gate electrode buried in each trench through a gate insulating film; a base region of buried in the mesa region; a plurality of emitter regions that are periodically buried in a surface layer portion of the base region along a longer direction of the trench; and contact regions that are alternately buried in the longer direction together with the emitter regions such that each emitter region is interposed between the contact regions, are deeper than the emitter region, and extend immediately below the emitter region so as to be separated from each other, a contact-region contact-width in the longer direction defined in a surface of the contact region being less than an emitter-region contact-width in the longer direction defined in a surface of the emitter region.

Abstract: Structures and methods for controlling dopant diffusion and activation are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a channel layer; a barrier layer over the channel layer; a gate electrode over the barrier layer; and a doped layer formed between the barrier layer and the gate electrode. The doped layer includes (a) an interface layer in contact with the barrier layer and (b) a main layer between the interface layer and the gate electrode. The doped layer comprises a dopant whose doping concentration in the interface layer is lower than that in the main layer.

Abstract: A method includes forming a bottom layer of a multi-layer mask over a first gate structure extending across a fin; performing a chemical treatment to treat an upper portion of the bottom layer of the multi-layer mask, while leaving a lower portion of the bottom layer of the multi-layer mask untreated; forming a sacrificial layer over the bottom layer of the multi-layer mask; performing a polish process on the sacrificial layer, in which the treated upper portion of the bottom layer of the multi-layer mask has a slower removal rate in the polish process than that of the untreated lower portion of the bottom layer of the multi-layer mask; forming middle and top layers of the multi-layer mask; patterning the multi-layer mask; and etching an exposed portion of the first gate structure to break the first gate structure into a plurality of second gate structures.

Abstract: A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.

Abstract: A method for fabricating a field-effect transistor includes: providing a structure including a first layer of semiconductor material, a doped second layer of semiconductor material arranged on top of the first layer of semiconductor material, the composition of which is different from that of the first layer, two spacers made of dielectric material arranged on top of the second layer of semiconductor material and separated by a groove, the second layer of semiconductor material being accessible at the bottom of the groove; etching the second layer of semiconductor material at the bottom of the groove until reaching the first layer of semiconductor material in such a way as to retain the second layer of semiconductor material beneath the spacers on either side of the groove; and then forming a gate stack in the groove.

Abstract: A gate stack structure is disclosed for inhibiting charge leakage in III-V transistor devices. The techniques are particularly well-suited for use in enhancement-mode MOSHEMTs but can also be used in other transistor designs susceptible to charge spillover and unintended channel formation in the gate stack. In an example embodiment, the techniques are realized in a transistor having a III-N gate stack over a gallium nitride (GaN) channel layer. The gate stack is configured with a relatively thick barrier structure and wide bandgap III-N materials to prevent or otherwise reduce channel charge spillover resulting from tunneling or thermionic processes at high gate voltages. The barrier structure is configured to manage lattice mismatch conditions, so as to provide a robust high-performance transistor design. In some cases, the gate stack is used in conjunction with an access region polarization layer to induce two-dimensional electron gas (2DEG) in the channel layer.

Abstract: An integrated circuit includes a plurality of low-voltage FinFET transistors each having a channel length l and a channel width w, the low-voltage FinFET transistors having a first threshold voltage channel implant and a first gate dielectric thickness. The integrated circuit also includes a plurality of high-voltage FinFET transistors each having the channel length l and the channel width w, the high-voltage FinFET transistors having a second threshold voltage channel implant greater than the first threshold voltage channel implant and second gate dielectric thickness greater than the first gate dielectric thickness.

Abstract: A high-electron-mobility semiconductor device includes: a buffer region having first, second and third cross-sections forming a stepped lateral profile, the first cross-section being thicker than the third cross-section and comprising a first buried field plate disposed therein, the second cross-section interposed between the first and third cross-sections and forming oblique angles with the first and third cross-sections; and a barrier region of substantially uniform thickness extending along the stepped lateral profile of the buffer region, the barrier region being separated from the first buried field plate by a portion of the buffer region. The buffer region is formed by a first semiconductor material and the barrier region is formed by a second semiconductor material.

Abstract: A semiconductor structure is provided. The semiconductor structure includes: a substrate; a source structure and a drain structure disposed on the substrate; a gate structure disposed on the substrate and between the source structure and the drain structure; a first field plate disposed on the substrate; a first oxide layer disposed between the substrate and the first field plate; a second field plate disposed on the first field plate, wherein the second field plate is closer to the drain structure than the first field plate; a planarized second oxide layer disposed between the first oxide layer and the second field plate; and a third field plate disposed on the second field plate, wherein the third field plate is closer to the drain structure than the second field plate.

Abstract: Embodiments of the present invention are directed to techniques for integrating a split gate metal-oxide-nitride-oxide-semiconductor (SG-MONOS) memory with a vertical field effect transistor (VFET). In a non-limiting embodiment of the invention, a vertical SG-MONOS memory device is formed on a first region of a substrate. The SG-MONOS memory device can include a charge storage stack, a memory gate on the charge storage stack, and a control gate vertically stacked over the charge storage stack and the memory gate. A VFET is formed on a second region of the substrate. The VFET can include a logic gate.

Abstract: A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.

Abstract: One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure.

Abstract: A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.

Abstract: Provided is a semiconductor device including a first n-type fin field effect transistor (FinFET) and a second n-type FinFET. The first FinFET includes a first work function layer. The first work function layer includes a first portion of a first layer. The second n-type FinFET includes a second work function layer. The second work function layer includes a second portion of the first layer and a first portion of a second layer underlying the second portion of the first layer. A thickness of the first work function layer is less than a thickness of the second work function layer. A method of manufacturing the semiconductor device is also provided.

Abstract: A method for making a semiconductor device may include forming an isolation region adjacent an active region in a semiconductor substrate, and selectively etching the active region so that an upper surface of the active region is below an adjacent surface of the isolation region and defining a stepped edge therewith. The method may further include forming a superlattice overlying the active region. The superlattice may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: The present invention provides a GaN-based microwave power device with a large gate width and manufacturing method thereof. The device includes an AlGaN/GaN heterojunction epitaxial layer, a first dielectric layer overlying the AlGaN/GaN heterojunction epitaxial layer, a strip-like source electrode, a drain electrode distributed in a shape of a fishbone, an annular gate electrode, a second dielectric layer separating upper and lower electrodes, and an interconnect metal electrode pad. The GaN-based microwave power device with the large gate width prepared according to the present invention, has a small phase shift of the signals, a small parasitic capacitance of the device, a high signal gain, high power added efficiency and a high output power. At the same time, the manufacturing process of the device is simple, the chip area is saved, and the device has a good repeatability.

Abstract: Provided is a field effect transistor (FET) including a gradually varying composition channel. The FET includes: a drain region; a drift region on the drain region; a channel region on the drift region; a source region on the channel region; a gate penetrating the channel region and the source region in a vertical direction; and a gate oxide surrounding the gate. The channel region has a gradually varying composition along the vertical direction such that an intensity of a polarization in the channel region gradually varies.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a stack comprising a plurality of conductive layers stacked one over the other in a first direction, and an insulating layer interposed between adjacent conductive layers located over the substrate, a first semiconductor layer extending inwardly of the stack and through the plurality of conductive layers in the first direction, a memory layer located between the first semiconductor layer and the plurality of conductive layers, and a second semiconductor layer located over, and in contact with, the first semiconductor layer, wherein the second semiconductor layer includes a third semiconductor layer containing phosphorous, and a fourth semiconductor layer containing carbon provided between the first semiconductor layer and the third semiconductor layer.

Abstract: A semiconductor film, a sheet like object, and a semiconductor device are provided that have inhibited semiconductor properties, particularly leakage current, and excellent withstand voltage and heat dissipation. A crystalline semiconductor film or a sheet like object includes a corundum structured oxide semiconductor as a major component, wherein the film has a film thickness of 1 ?m or more. Particularly, the semiconductor film or the object includes a semiconductor component of oxide of one or more selected from gallium, indium, and aluminum as a major component. A semiconductor device has a semiconductor structure including the semiconductor film or the object.

Abstract: A method for forming source/drain regions in a semiconductor device and a semiconductor device including source/drain regions formed by the method are disclosed. In an embodiment, a method includes etching a semiconductor fin to form a first recess, the semiconductor fin defining sidewalls and a bottom surface of the first recess, the semiconductor fin extending in a first direction; forming a source/drain region in the first recess, the source/drain region including a single continuous material extending from a bottom surface of the first recess to above a top surface of the semiconductor fin, a precursor gas for forming the source/drain region including phosphine (PH3) and at least one of arsine (AsH3) or monomethylsilane (CH6Si); and forming a gate over the semiconductor fin adjacent the source/drain region, the gate extending in a second direction perpendicular the first direction.

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second direction perpendicular to the first direction.

Abstract: Techniques are disclosed for forming semiconductor integrated circuits including one or more of source and drain contacts and gate electrodes comprising crystalline alloys including a transition metal. The crystalline alloys help to reduce contact resistance to the semiconductor devices. In some embodiments of the present disclosure, this reduction in contact resistance is accomplished by aligning the work function of the crystalline alloy with the work function of the source and drain regions such that a Schottky barrier height associated with an interface between the crystalline alloys and the source and drain regions is in a range of 0.3 eV or less.

Abstract: A metal-oxide-semiconductor (MOS) device comprising a heavily doped substrate, an epitaxial layer, an open, a plurality of MOS units, and a metal pattern layer is provided. The epitaxial layer is formed on the heavily doped substrate. The open is defined in the epitaxial layer to expose the heavily doped substrate. The MOS units are formed on the epitaxial layer. The metal pattern layer comprises a source metal pattern, a gate metal pattern, and a drain metal pattern. The source metal pattern and the gate metal pattern are formed on the epitaxial layer. The drain metal pattern fills in the open and is extended from the heavily doped substrate upward to above the epitaxial layer.

Abstract: III-nitride materials are described herein, including material structures comprising III-nitride material regions (e.g., gallium nitride material regions). In certain cases, the material structures also comprise substrates having relatively high electrical conductivities. Certain embodiments include one or more features that reduce the degree to which thermal runaway occurs, which can enhance device performance including at elevated flange temperatures. Some embodiments include one or more features that reduce the degree of capacitive coupling exhibited during operation. For example, in some embodiments, relatively thick III-nitride material regions and/or relatively small ohmic contacts are employed.

Abstract: A semiconductor structure having epitaxial structures and a method for forming the same are provided. The method includes forming a gate structure over first and second fins on a semiconductor substrate. The method also includes forming a first dielectric material over the first and second fins and the gate structure. The method further includes forming a second dielectric material over the first dielectric material and above an interspace between the first and the second fins. The method includes partially removing the first dielectric material and the second dielectric material to form an inner spacer structure between the first fin and the second fin and outer spacers on two opposite sides of the inner spacer structure, wherein a top surface of the inner spacer structure is below top surfaces of the outer spacers. The method also includes forming an epitaxial structure on the first fin and the second fin.