Abstract: A p-type nitride compound semiconductor layer is formed on a buffer formed on a substrate. An n-type contact region is formed by ion implantation under a source electrode and a drain electrode. An electric-field reducing layer made of an n-type nitride compound semiconductor is formed on the p-type nitride compound semiconductor layer. A carrier density of the electric-field reducing layer is lower than that of the n-type contact region. A first end portion of the electric-field reducing layer contacts with the n-type contact region, and a second end portion of the electric-field reducing layer overlaps with a gate electrode.

Abstract: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.

Abstract: An AlN layer (2), a GaN buffer layer (3), a non-doped AlGaN layer (4a), an n-type AlGaN layer (4b), an n-type GaN layer (5), a non-doped AlN layer (6) and an SiN layer (7) are sequentially formed on an SiC substrate (1). At least three openings are formed in the non-doped AlN layer (6) and the SiN layer (7), and a source electrode (8a), a drain electrode (8b) and a gate electrode (19) are evaporated in these openings.

Abstract: An epilayer structure includes a field-effect transistor structure and a heterojunction bipolar transistor structure. The heterojunction bipolar transistor structure contains an n-doped subcollector and a collector formed in combination with the field-effect transistor structure, wherein at least a portion of the subcollector or collector contains Sn, Te, or Se. In one embodiment, a base is formed over the collector; and an emitter is formed over the base. The bipolar transistor and the field-effect transistor each independently contain a III-V semiconductor material.

Abstract: A GaN-based field effect transistor (MOSFET) is comprised of a channel layer comprised of p-type GaN, an electron supply layer, a surface layer having band gap energy smaller than that of the electron supply layer, sequentially laminated on a substrate, and recess section is formed by removing a part of the drift layer, the electron supply layer, and the surface layer down to a depth that reaches to the channel layer. A source electrode and a drain electrode are formed so that the recess section positions between them, a gate insulation film is formed on the surface layer and on inner-surface of the recess section including the channel layer, and a gate electrode is formed on the gate insulating film in the recess section.

Abstract: A motor driving circuit includes a three-phase inverter circuit 8, including three upper-arm switching elements 56a to 56c for driving upper arms of different phases of a three-phase motor 3, and three lower-arm switching elements 56d to 56f for driving lower arms of different phases. At least one of the upper-arm switching elements 56a to 56c and the lower-arm switching elements 56d to 56f is a semiconductor element that performs a diode operation. The diode operation is an operation in which a voltage less than or equal to a threshold voltage of a gate electrode G is applied to the gate electrode G with reference to a potential of a first ohmic electrode S, thereby conducting a current flow from the first ohmic electrode S to a second ohmic electrode D and blocking a current flow from the second ohmic electrode D to the first ohmic electrode S.

Abstract: An integrated electrostatic discharge (ESD) shunting circuit includes a III-V semiconductor layer, and a first drain-less high electron mobility transistor (HEMT) or a metal-semiconductor FET (MESFET) transistor having a first gate and at least a second drain-less HEMT or MESFET having a second gate formed in the substrate. The HEMTs or MESFETs include a donor layer on the semiconductor layer, no drains, and a source including an ohmic contact layer on the donor layer.

Abstract: A transistor comprising an active region, with source and drain electrodes formed in contact with the active region and a gate formed between the source and drain electrodes and in contact with the active region. A first spacer layer is on at least part of the surface of the active region between the gate and the drain electrode and between the gate and the source electrode. The gate comprises a generally t-shaped top portion that extends toward the source and drain electrodes. A field plate is on the spacer layer and under the overhand of at least one section of the gate top portion. The field plate is at least partially covered by a second spacer layer, with the second spacer layer on at least part of the surface of the first active layer and between the gate and the drain and between the gate and the source. At least one conductive path electrically connects the field plate to the source electrode or the gate.

Abstract: There are disclosed herein various implementations of composite semiconductor devices including a voltage protected device. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor having a first output capacitance, and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device, the LV device having a second output capacitance. A ratio of the first output capacitance to the second output capacitance is set based on a ratio of a drain voltage of the normally ON III-nitride power transistor to a breakdown voltage of the LV device so as to provide voltage protection for the LV device.

Abstract: There are disclosed herein various implementations of composite III-nitride semiconductor devices having turn-on prevention control. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device. The LV device is configured to have a noise-resistant threshold voltage to provide the turn-on prevention control for the normally OFF composite semiconductor device by preventing noise current from flowing through a channel of the normally ON III-nitride power transistor in a noisy system.

Abstract: There are disclosed herein various implementations of semiconductor devices having passive oscillation control. In one exemplary implementation, such a device is implemented to include a III-nitride transistor having a source electrode, a gate electrode and a drain electrode. A damping resistor is configured to provide the passive oscillation control for the III-nitride transistor. In one implementation, the damping resistor includes at least one lumped resistor.

Abstract: Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.

Abstract: A light-emitting diode including: a structure in a semiconductor material of first conductivity type, wherein the structure has a first face of which a first region is in contact with a pad of semiconductor material having a second conductivity type opposite the first conductivity type, and the diode further includes a first electric contact on the pad, a second electric contact-on the first face or on a second face of the structure, and a gate in electrically conductive material arranged on a second region of the first face and separated from the first face by an electrically insulating layer.

Abstract: A semiconductor device includes an etch-stop layer between a first layer of a field-effect transistor and a second layer of a bipolar transistor, each of which includes at least one arsenic-based semiconductor layer. A p-type layer is between the second layer and the etch-stop layer, and the device can include an n-type layer deposited between the etch-stop layer and p-type layer. The p-type layer provides an electric field that inhibits intermixing of the InGaP layer with layers in the first and second layers.

Abstract: A transistor device capable of high performance at high temperatures. The transistor comprises a gate having a contact layer that contacts the active region. The gate contact layer is made of a material that has a high Schottky barrier when used in conjunction with a particular semiconductor system (e.g., Group-III nitrides) and exhibits decreased degradation when operating at high temperatures. The device may also incorporate a field plate to further increase the operating lifetime of the device.

Abstract: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.

Abstract: An optically active material is used to create power devices and circuits having significant performance advantages over conventional methods for affecting optical control of power electronics devices and circuits. A silicon-carbide optically active material is formed by compensating shallow donors with the boron related D-center. The resulting material can be n-type or p-type but it is distinguished from other materials by the ability to induce persistent photoconductivity in it when illuminated by electromagnetic radiation with a photon energy in excess of the threshold energy required to photoexcite electrons from the D-center to allowed states close to the conduction band edge, which varies from polytype to polytype.

Abstract: A semiconductor device including at least a p-channel field-effect transistor region formed above a compound semiconductor substrate. The p-channel field-effect transistor region includes an undoped buffer layer; a p-type channel layer formed in contact with the buffer layer; a p-type source region and a p-type drain region formed in the channel layer, being separated with each other; and an n-type gate region formed above the channel layer and between the source region and the drain region. The buffer layer is formed having either a multilayer structure including a hole diffusion control layer with a band gap larger than the channel layer, or a single layer structure including only the hole diffusion control layer.

Abstract: An enhancement mode (E-mode) HEMT is provided that can be used for analog and digital applications. In a specific embodiment, the HEMT can be an AlN/GaN HEMT. The subject E-mode device can be applied to high power, high voltage, high temperature applications, including but not limited to telecommunications, switches, hybrid electric vehicles, power flow control and remote sensing. According to an embodiment of the present invention, E-mode devices can be fabricated by performing an oxygen plasma treatment with respect to the gate area of the HEMT. The oxygen plasma treatment can be, for example, an O2 plasma treatment. In addition, the threshold voltage of the E-mode HEMT can be controlled by adjusting the oxygen plasma exposure time. By using a masking layer protecting regions for depletion mode (D-mode) devices, D-mode and E-mode devices can be fabricated on a same chip.

Abstract: A semiconductor device includes a high-side field-effect transistor including a high-side drain electrode, a high-side gate electrode, and a high-side source electrode; and a first low-side field-effect transistor including a first low-side drain electrode, a first low-side gate electrode and a first low-side source electrode, wherein the high-side source electrode and the first low-side drain electrode are shared as a single source and drain electrode, and the high-side drain electrode, the high-side gate electrode, the source and drain electrode, the first low-side gate electrode and the first low-side source electrode are arranged in this order while being interposed by gaps, respectively.

Abstract: A field-effect transistor includes a semi-insulating substrate, a source electrode, a drain electrode, a gate electrode, the electrodes being provided on the semi-insulating substrate, and a buried gate region which is provided under the gate electrode and in which an impurity is doped, wherein a concave slit is provided in the semi-insulating substrate, the slit being located between the gate electrode and the drain electrode and being adjacent to the buried gate region at the side of the drain electrode.

Abstract: Provided is a display device capable of suppressing generation of optical leakage current as well as increase in capacitance in a case where a plurality of thin film transistors (TFTs) including a gate electrode film on a light source side are formed in series. Relative areas of opposing regions between a semiconductor film and the gate electrode film with respect to channel regions are different in at least a part of the plurality of TFTs, to thereby provide a flat panel display having a structure for suppressing increase in capacitance while suppressing generation of optical leakage current.

Abstract: An array substrate is disclosed. The array substrate comprises a substrate, a gate metal layer, a gate insulation layer, a semiconductor layer, a patterned metal layer, a flat layer, and a pixel electrode. The patterned metal layer is disposed on the surface of the semiconductor layer comprising a source and a drain, and on the surface of the gate insulation layer comprising a storage capacitor line and a data line. The storage capacitor line has an extending portion parallel to a scan line. The pixel electrode overlaps parts of the scan line, parts of the data line, parts of the storage capacitor line, and parts of the extending portion. A method for manufacturing the array substrate is also provided.

Abstract: In a method of forming a gate recess, on a surface of an epitaxial wafer including an epitaxial substrate, having a semiconductor layer having the band gap energy varying therein in the depth-wise direction, and a SiN surface protective layer, having a sidewall forming a gate opening and coating the surface of the epitaxial substrate, ultraviolet light having its energy equivalent to the band gap energy of the specific semiconductor layer is irradiated, while the specific semiconductor layer is photoelectrochemically etched from the gate opening with the SiN surface protective layer used as a mask. The gate recess free from plasma ion-induced damage is thus obtained.

Abstract: The present invention provides a nitride-based semiconductor device. The nitride-based semiconductor device includes: a base substrate having a diode structure; an epi-growth film disposed on the base substrate; and an electrode part disposed on the epi-growth film, wherein the diode structure includes: first-type semiconductor layers; and a second-type semiconductor layer which is disposed within the first-type semiconductor layers and has both sides covered by the first-type semiconductor layers.

Abstract: This invention provides a light-emitting element and the manufacture method thereof. The light-emitting element is suitable for flip-chip bonding and comprises an electrode having a plurality of micro-bumps for direct bonding to a submount. Bonding within a relatively short distance between the light-emitting device and the submount can be formed so as to improve the heat dissipation efficiency of the light-emitting device.

Abstract: A semiconductor device includes a substrate common to a first field effect transistor and a second field effect transistor, a channel layer of a first conductivity type formed on the substrate and common to the first and second field effect transistors, a an upper compound semiconductor layer formed on the channel layer and common to the first and second field effect transistors, a compound semiconductor region of a second conductivity type formed in the same layer as the upper compound semiconductor layer, a gate electrode of the first field effect transistor in ohmic contact with the compound semiconductor region, and a gate electrode of the second field effect transistor in Schottky contact with the upper compound semiconductor layer.

Abstract: A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority charge carrier conductivity type, formed over the second silicon body. The second silicon body has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate including a <100> silicon layer, an insulator layer over the <100> silicon layer, and a P type conductivity <111> silicon layer over the insulator layer.

Abstract: A semiconductor device includes a semiconductor layer stack formed on a substrate, a first ohmic electrode and a second ohmic electrode which are formed on the semiconductor layer stack, and are spaced from each other, a first control layer formed between the first ohmic electrode and the second ohmic electrode, and a first gate electrode formed on the first control layer. The first control layer includes a lower layer, an intermediate layer which is formed on the lower layer, and has lower impurity concentration than the lower layer, and an upper layer which is formed on the intermediate layer, and has higher impurity concentration than the intermediate layer.

Abstract: A monolithic semiconductor structure includes a stack of layers. The stack includes a substrate; a first layer made from a first semiconductor material; and a second layer made from a second semiconductor material. The first layer is situated between the substrate and the second layer and at least one of the first semiconductor material and the second semiconductor material contains a III-nitride material. The structure includes a power transistor, including a body formed in the stack of layers; a first power terminal at a side of the first layer facing the second layer; a second power terminal at least partly formed in the substrate; and a gate structure for controlling the propagation through the body of electric signals between the first power terminal and the second power terminal.

Abstract: Exemplary embodiments provide structures and methods for power devices with integrated clamp structures. The integration of clamp structures can protect the power device, e.g., from electrical overstress (EOS). In one embodiment, active devices can be formed over a substrate, while a clamp structure can be integrated outside the active regions of the power device, for example, under the active regions and/or inside the substrate. Integrating clamp structure outside active regions of power devices can maximize the active area for a given die size and improve robustness of the clamped device since the current will spread in the substrate by this integration.

Abstract: A semiconductor device having a transistor and a rectifier includes: a current path; a first main electrode having a rectifying function and arranged on one end of the current path; a second main electrode arranged on the other end of the current path; an auxiliary electrode arranged in a region of the current path between the first main electrode and the second main electrode; a third main electrode arranged on the one end of the current path apart from the first main electrode along a direction intersecting the current path; and a control electrode arranged in a region of the current path between the second main electrode and the third main electrode. The transistor includes the current path, the second main electrode, the third main electrode, and the control electrode. The rectifier includes the current path, the first main electrode, the second main electrode, and the auxiliary electrode.

Abstract: An image sensor includes a semiconductor substrate, a photodiode formed in the semiconductor substrate, a first impurity region formed in the semiconductor substrate spaced from the photodiode, a second impurity region formed in the semiconductor substrate spaced from the first impurity region, a first gate formed over the semiconductor substrate between the photodiode and the first impurity region, a second gate formed over the semiconductor substrate between the first impurity region and the second impurity region, a spacer formed over the fourth impurity region and a first sidewall of the second gate, and an insulating film formed over the photodiode, the first gate, the first impurity region and a second sidewall and a portion of the uppermost surface of the second gate.

Abstract: A semiconductor device includes: a compound semiconductor substrate; a buffer layer, a channel layer, and a Schottky junction forming layer sequentially formed on the compound semiconductor substrate, the buffer layer, the channel layer, and the Schottky junction forming layer each being a compound semiconductor; a source electrode and a drain electrode located on the Schottky junction forming layer; and a gate electrode disposed between the source and drain electrodes and forming a Schottky junction with the Schottky junction forming layer. The dopant impurity concentration profile in the channel layer is inversely proportional to the third power of depth into the channel layer from a top surface of the channel layer. The channel layer has fixed sheet dopant impurity concentration, and the top surface of the channel layer has a dopant concentration in a range from 5.0×1017 cm?3 to 2.0×1018 cm?3.

Abstract: A method for fabricating a semiconductor device which protects the ohmic metal contacts and the channel of the device during subsequent high temperature processing steps is explained. An encapsulation layer is used to cover the channel and ohmic metal contacts. The present invention provides a substrate on which a plurality of semiconductor layers are deposited. The semiconductor layers act as the channel of the device. The semiconductor layers are covered with an encapsulation layer. A portion of the encapsulation layer and the plurality of semiconductor layers are removed, wherein ohmic metal contacts are deposited. The ohmic metal contacts are then annealed to help reduce their resistance. The encapsulation layer ensures that the ohmic metal contacts do not migrate during the annealing step and that the channel is not harmed by the high temperatures needed during the annealing step.

Abstract: To provide a semiconductor device in which a rectifying element capable of reducing a leak current in reverse bias when a high voltage is applied and reducing a forward voltage drop Vf and a transistor element are integrally formed on a single substrate. A semiconductor device has a transistor element and a rectifying element on a single substrate. The transistor element has an active layer formed on the substrate and three electrodes (source electrode, drain electrode, and gate electrode) disposed on the active layer. The rectifying element has an anode electrode disposed on the active layer, a cathode electrode which is the drain electrode, and a first auxiliary electrode between the anode electrode and cathode electrode.

Abstract: A hybrid device including a silicon based MOSFET operatively connected with a GaN based device.

Abstract: Disclosed is a monolithically integrated silicon and group III-V device that includes a group III-V transistor formed in a III-V semiconductor body disposed over a silicon substrate. At least one via extends through the III-V semiconductor body to couple at least one terminal of the group III-V transistor to a silicon device formed in the silicon substrate. The silicon device can be a Schottky diode, and the group III-V transistor can be a GaN HEMT. In one embodiment an anode of the Schottky diode is formed in the silicon substrate. In another embodiment, the anode of the Schottky diode is formed in a lightly doped epitaxial silicon layer atop the silicon substrate. In one embodiment a parallel combination of the Schottky diode and the group III-V transistor is formed, while in another embodiment is series combination is formed.

Abstract: A field-effect semiconductor device such as a HEMT or MESFET is monolithically integrated with a Schottky diode for feedback, regeneration, or protection purposes. The field-effect semiconductor device includes a main semiconductor region having formed thereon a source, a drain, and a gate between the source and the drain. Also formed on the main semiconductor region, preferably between gate and drain, is a Schottky electrode electrically coupled to the source. The Schottky electrode provides a Schottky diode in combination with the main semiconductor region. A current flow is assured from Schottky electrode to drain without interruption by a depletion region expanding from the gate.

Abstract: The object of the present invention is to provide a semiconductor device and the manufacturing method thereof which are capable of preventing decrease in the collector breakdown voltage and reducing the collector resistance. The semiconductor device according to the present invention includes: a HBT formed on a first region of a semiconductor substrate; and an HFET formed on a second region of the semiconductor substrate, wherein the HBT includes: an emitter layer of a first conductivity; a base layer of a second conductivity that has a band gap smaller than that of the emitter layer; a collector layer of the first conductivity or a non-doped collector layer; and a sub-collector layer of the first conductivity which are formed sequentially on the first region, and the HFET includes an electron donor layer including a part of the emitter layer, and a channel layer formed under the electron donor layer.

Abstract: A co-integrated HBT/FET apparatus and system, and methods for making the same, are disclosed. A co-integrated HBT/FET apparatus may include a first epitaxial structure formed over a substrate, the first epitaxial structure forming, at least in part, a FET device, a separation layer formed over the first epitaxial structure, and a second epitaxial structure formed over the separation layer, the second epitaxial structure forming, at least in part, a heterojunction bipolar transistor (HBT) device.

Abstract: According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group III-V semiconductor device may be a III-nitride high electron mobility transistor (HEMT).

Abstract: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.

Abstract: A method for manufacturing a semiconductor apparatus includes forming a step layer in a first region on a substrate; forming a first semiconductor thin film on the top surface and sidewalls of the step layer; removing part of the first semiconductor thin film from the top surface while leaving part of the first semiconductor thin film on the sidewalls; removing the step layer; and forming a fin-type transistor that includes the first semiconductor thin film disposed on the sidewalls as a channel.

Abstract: A semiconductor device includes: a compound semiconductor substrate; an n-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a first channel layer; an n-type first barrier layer that forms a heterojunction with the first channel layer, and supplies an n-type charge to the first channel layer; and a p-type gate region that has a pn junction-type potential barrier against the n-type first barrier layer; and a p-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a p-type second channel layer, and an n-type gate region that has a pn junction-type potential barrier against the p-type second channel layer.

Abstract: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged.

Abstract: According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group III-V semiconductor device may be a III-nitride high electron mobility transistor (HEMT).

Abstract: In a semiconductor device in which a diode and a high electron mobility transistor are incorporated in the same semiconductor chip, a compound semiconductor layer of the high electron mobility transistor is formed on a main surface (first main surface) of a semiconductor substrate of the diode, and an anode electrode of the diode is electrically connected to an anode region via a conductive material embedded in a via hole (hole) reaching a p+ region which is the anode region of the main surface of the semiconductor substrate from a main surface of the compound semiconductor layer.

Abstract: A silicon-made low-forward-voltage Schottky barrier diode is serially combined with a high-antivoltage-strength high-electron-mobility transistor made from a nitride semiconductor that is wider in bandgap than silicon. The Schottky barrier diode has its anode connected to the gate, and its cathode to the source, of the HEMT. This HEMT is normally on. The reverse voltage withstanding capability of the complete device depends upon that between the drain and gate of the HEMT.

Abstract: A nitride semiconductor device includes: a first semiconductor layer made of first nitride semiconductor; a second semiconductor layer formed on a principal surface of the first semiconductor layer and made of second nitride semiconductor having a bandgap wider than that of the first nitride semiconductor; a control layer selectively formed on, or above, an upper portion of the second semiconductor layer and made of third nitride semiconductor having a p-type conductivity; source and drain electrodes formed on the second semiconductor layer at respective sides of the control layer; a gate electrode formed on the control layer; and a fourth semiconductor layer formed on a surface of the first semiconductor layer opposite to the principal surface, having a potential barrier in a valence band with respect to the first nitride semiconductor and made of fourth nitride semiconductor containing aluminum.