Abstract: A device includes a source and a drain for transmitting and receiving an electronic charge. The device also includes a first stack and a second stack for providing at least part of a conduction path between the source and the drain, wherein the first stack includes a first gallium nitride (GaN) layer of a first polarity, and the second stack includes a second gallium nitride (GaN) layer of the second polarity, and wherein the first polarity is different from the second polarity. At least one gate operatively connected to at least the first stack for controlling a conduction of the electronic charge, such that, during an operation of the device, the conduction path includes a first two-dimensional electron gas (2DEG) channel formed in the first GaN layer and a second 2DEG channel formed in the second GaN layer.

Abstract: A higher electron mobility transistor (HEMT) and a method of manufacturing the same are disclosed. According to example embodiments, the HEMT may include a channel supply layer on a channel layer, a source electrode and a drain electrode that are on at least one of the channel layer and the channel supply layer, a gate electrode between the source electrode and the drain electrode, and a source pad and a drain pad. The source pad and a drain pad electrically contact the source electrode and the drain electrode, respectively. At least a portion of at least one of the source pad and the drain pad extends into a corresponding one of the source electrode and drain electrode that the at least one of the source pad and the drain pad is in electrical contact therewith.

Abstract: A semiconductor device includes: a semiconductor substrate having an upper surface and a lower surface; a field effect transistor having a semiconductor layer on the upper surface of the semiconductor substrate, a gate electrode, a drain electrode, and a source electrode; a P-type diffusion region in the semiconductor substrate and extending to the upper surface of the semiconductor substrate; a first N-type diffusion region in the semiconductor substrate and extending t the upper surface of the semiconductor substrate; a first connection electrode connecting the P-type diffusion region to a grounding point; and a second connection electrode connecting the first N-type diffusion region to the gate electrode or the drain electrode. The P-type diffusion region and the first N-type diffusion region constitute a bidirectional lateral diode.

Abstract: A semiconductor device having high breakdown withstand voltage includes a first element which is a normally-on type transistor made of nitride compound semiconductor, a second element which is connected to the first element in series and is a transistor having withstand voltage between a source and a drain lower than withstand voltage of the first element, a first diode which is connected between a gate of the first element or a gate of the second element and a drain of the first element so that a cathode of the first diode is connected at the drain's side and has predetermined avalanche withstand voltage, and a first resistance connected to the gate to which the first diode is connected. The avalanche withstand voltage of the first diode is lower than breakdown voltage of the first element.

Abstract: A semiconductor die includes a III-nitride semiconductor substrate, a power HEMT (high-electron-mobility transistor) disposed in the III-nitride semiconductor substrate, and a first gate driver HEMT monolithically integrated with the power HEMT in the III-nitride semiconductor substrate. The power HEMT and the first gate driver HEMT each have a gate, a source and a drain. The first gate driver HEMT logically forms part of a driver, and is electrically connected to the gate of the power HEMT. The first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device. Additional embodiments of semiconductor dies and methods of manufacturing are also described.

Abstract: Provided is a nitride semiconductor device including: a nitride semiconductor layer over a substrate wherein the nitride semiconductor has a two-dimensional electron gas (2DEG) channel inside; a drain electrode in ohmic contact with the nitride semiconductor layer; a source electrode in Schottky contact with the nitride semiconductor layer wherein the source electrode is spaced apart from the drain electrode; a dielectric layer formed on the nitride semiconductor layer between the drain electrode and the source electrode and on at least a portion of the source electrode; and a gate electrode disposed on the dielectric layer to be spaced apart from the drain electrode, wherein a portion of the gate electrode is formed over a drain-side edge portion of the source electrode with the dielectric layer interposed therebetween, and a manufacturing method thereof.

Abstract: A semiconductor device includes: an epitaxial substrate formed by stacking a plurality of kinds of semiconductors over one semiconductor substrate by epitaxial growth; a field effect transistor of a first conductivity type formed in a first region; a field effect transistor of a second conductivity type formed in a second region; and a protective element formed in a third region. The protective element includes: a first stacking structure formed by etching the epitaxial substrate by vertical etching that proceeds in a stacking thickness direction; and a second stacking structure formed by etching the epitaxial substrate by vertical etching that proceeds in a stacking thickness direction. The protective element has two PN junctions on a current path formed between an upper end of the first stacking structure and an upper end of the second stacking structure via a base part of the first stacking structure and the second stacking structure.

Abstract: Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heterostructure field effect transistor (HFET) or a Schottky diode, arranged on a heat dissipation substrate. The HFET device may include a GaN-based multi-layer having a recess region; a gate arranged in the recess region; and a source and a drain that are arranged on portions of the GaN-based multi-layer at two opposite sides of the gate (or the recess region). The gate, the source, and the drain may be attached to the heat dissipation substrate. The recess region may have a double recess structure. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used.

Abstract: A multi-gate Schottky depletion-mode field effect transistor (FET), at least one diode and two resistors comprise a compact electrostatic discharge (ESD) protection structure. This ESD protection structure can be laid out in a smaller area than typical multiple diode ESD devices. The multi-gate FET may comprise various types of high-electron-mobility transistor (HEMT) devices, e.g., (pseudomorphic) pHEMT, (metamorphic) mHEMT, induced HEMT. The multiple gates of the Schottky field effect device are used to form an ESD trigger and charge draining paths for protection of circuits following the ESD protection device. Both single and dual polarity ESD protection devices may be provided on an integrated circuit die for protection of input-output circuits thereof.

Abstract: An embodiment of a transistor device includes a compound semiconductor material on a semiconductor carrier and a source region and a drain region spaced apart from each other in the compound semiconductor material with a channel region interposed between the source and drain regions. A Schottky diode is integrated with the semiconductor carrier, and contacts extend from the source and drain regions through the compound semiconductor material. The contacts are in electrical contact with the Schottky diode so that the Schottky diode is connected in parallel between the source and drain regions. In another embodiment, the integrated Schottky diode is formed by a region of doped amorphous silicon or doped polycrystalline silicon disposed in a trench structure on the drain side of the device.

Abstract: A semiconductor wafer includes a first semiconductor, and a second semiconductor formed directly or indirectly on the first semiconductor. The second semiconductor contains a first impurity atom exhibiting p-type or n-type conductivity, and a second impurity atom selected such that the Fermi level of the second semiconductor containing both the first and second impurity atoms is closer to the Fermi level of the second semiconductor containing neither the first impurity atom nor the second impurity atom, than the Fermi level of the second semiconductor containing the first impurity atom is. For example, the majority carrier of the second semiconductor is an electron, and the Fermi level of the second semiconductor containing the first and second impurity atoms is lower than the Fermi level of the second semiconductor containing the first impurity atom.

Abstract: According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group semiconductor device may be a III-nitride high electron mobility transistor (HEMT).

Abstract: A transistor in which the electric field is reduced in critical areas using field plates, permitting the electric field to be more uniformly distributed along the component, is provided, wherein the electric field in the active region is smoothed and field peaks are reduced. The semiconductor component has a substrate with an active layer structure, a source contact and a drain contact located on said active layer structure. The source contact and the drain contact are mutually spaced and at least one part of a gate contact is provided on the active layer structure in the region between the source contact and the drain contact, a gate field plate being electrically connected to the gate contact. In addition, at least two separate field plates are placed directly on the active layer structure or directly on a passivation layer.

Abstract: A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.

Abstract: Consistent with various example embodiments, a field-controlling electrode applies a negative bias, relative to a source/drain electrode, increase voltage breakdown. The field-controlling electrode is located over a channel region and between source and drain electrodes, and adjacent a gate electrode. The field electrode shapes a field in a portion of the channel region laterally between the gate electrode and one of the source/drain electrodes, in response to a negative bias applied thereto.

Abstract: A nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a conductive substrate, a first electrode, a second electrode, and a control electrode. The second semiconductor layer is directly bonded to the first semiconductor layer. The conductive substrate is provided on and electrically connected to the first semiconductor layer. The first electrode and the second electrode are provided on and electrically connected to a surface of the second semiconductor layer on a side opposite to the first semiconductor layer. The control electrode is provided on the surface of the second semiconductor layer between the first electrode and the second electrode. The first electrode is electrically connected to a drain electrode of a MOSFET formed of Si. The control electrode is electrically connected to a source electrode of the MOSFET. The conductive substrate is electrically connected to a gate electrode of the MOSFET.

Abstract: Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package with a stamped leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked atop a source of the III-nitride transistor, and a stamped leadframe comprising a first bent lead coupled to a gate of the III-nitride transistor and the anode of the diode, and a second bent lead coupled to a drain of the III-nitride transistor. The bent leads expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts.

Abstract: An optically active material is used to create power devices and circuits having significant performance advantages over conventional methods for affecting optical control of power electronics devices and circuits. A silicon-carbide optically active material is formed by compensating shallow donors with the boron related D-center. The resulting material can be n-type or p-type but it is distinguished from other materials by the ability to induce persistent photoconductivity in it when illuminated by electromagnetic radiation with a photon energy in excess of the threshold energy required to photoexcite electrons from the D-center to allowed states close to the conduction band edge, which varies from polytype to polytype.

Abstract: A semiconductor device of an embodiment includes a normally-off transistor having a first source electrically connected to a source terminal, a first drain, and a first gate electrically connected to a gate terminal, a normally-on transistor having a second source electrically connected to the first drain, a second drain electrically connected to a drain terminal, and a second gate, a capacitor having one end electrically connected to the gate terminal and the other end electrically connected to the second gate; and a first diode having a first anode electrically connected to the capacitor and the second gate and a first cathode electrically connected to the first source.

Abstract: According to an embodiment, a semiconductor device includes a conductive substrate, a Schottky barrier diode, and a field-effect transistor. The Schottky barrier diode is mounted on the conductive substrate and includes an anode electrode and a cathode electrode. The anode electrode is electrically connected to the conductive substrate. The field-effect transistor is mounted on the conductive substrate and includes a source electrode, a drain electrode, and a gate electrode. The source electrode of the field-effect transistor is electrically connected to the cathode electrode of the Schottky barrier diode. The gate electrode of the field-effect transistor is electrically connected to the anode electrode of the Schottky barrier diode.

Abstract: A semiconductor device including a first GaN layer, an AlGaN layer, a second GaN layer, a gate electrode, a source electrode, and a drain electrode sequentially stacked on a substrate, capable of improving a leakage current and a breakdown voltage characteristics generated in the gate electrode by locally forming a p type GaN layer on the AlGaN layer, and a manufacturing method thereof, and a manufacturing method thereof are provided. The semiconductor device includes: a substrate, a first GaN layer formed on the substrate, an AlGaN layer formed on the first GaN layer, a second GaN layer formed on the AlGaN layer and including a p type GaN layer, and a gate electrode formed on the second GaN layer, wherein the p type GaN layer may be in contact with a portion of the gate electrode.

Abstract: An AlN layer (2), a GaN buffer layer (3), a non-doped AlGaN layer (4a), an n-type AlGaN layer (4b), an n-type GaN layer (5), a non-doped AlN layer (6) and an SiN layer (7) are sequentially formed on an SiC substrate (1). At least three openings are formed in the non-doped AlN layer (6) and the SiN layer (7), and a source electrode (8a), a drain electrode (8b) and a gate electrode (19) are evaporated in these openings.

Abstract: A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.

Abstract: A Schottky contact is disposed atop the surface of the semiconductor. A first Schottky contact metal layer is disposed atop a first portion of the semiconductor surface. A second Schottky contact metal is disposed atop a second portion of the surface layer and joins the first Schottky contact metal layer. A first. Schottky contact metal layer has a lower work function than the second Schottky contact metal layer.

Abstract: A method of forming a template on a silicon substrate includes providing a single crystal silicon substrate. The method further includes epitaxially depositing a layer of rare earth oxide on the surface of the silicon substrate. The rare earth oxide being substantially crystal lattice matched to the surface of the silicon substrate. The method further includes forming an aluminum oxide layer on the rare earth oxide, the aluminum oxide being substantially crystal lattice matched to the surface of the rare earth oxide and epitaxially depositing a layer of aluminum nitride (AlN) on the aluminum oxide layer substantially crystal lattice matched to the surface of the aluminum oxide.

Abstract: A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.

Abstract: A semiconductor device has a shield plate electrode connected to a source terminal electrode near a drain electrode. The source terminal electrode is arranged between an active region AA and a drain terminal electrode, and a shield plate electrode is connected to the source terminal electrode.

Abstract: Disclosed is a semiconductor device including: a semiconductor substrate; a field effect transistor formed on the semiconductor substrate; and a diode forming area adjacent to a forming area of the field effect transistor, wherein the diode forming area is insulated from the forming area of the field effect transistor on the semiconductor substrate, the diode forming area includes an anode electrode and a cathode electrode arranged side by side in a multi-finger shape, and the anode electrode and the cathode electrode are formed in a direction different from directions of a gate electrode, a source electrode, and a drain electrode of the field effect transistor arranged side by side in a multi-finger shape.

Abstract: An integrated circuit with ESD protection comprises at least one ESD protection circuit block, which comprises a DC blocking capacitor connected in parallel with at least one compound semiconductor enhancement mode FET as an ESD protection device. The ESD protection circuit block that is built in an integrated circuit provides ESD protection while minimizing the generation of unwanted nonlinear signals resulting from the ESD protection. An integrated circuit comprises a high frequency circuit, a switching element, and two ESD protection circuit blocks, in which the high frequency circuit is connected between a first terminal and a second terminal for inputting or outputting the RF signals, the first ESD protection circuit block is connected from a branch node between the first terminal and the high frequency circuit to the switching element, and the second ESD protection circuit block is connected from the switching element to the ground.

Abstract: An improved pseudomorphic high electron mobility transistor (pHEMT) and heterojunction bipolar transistor (HBT) integrated epitaxial structure, in which the structure comprises a substrate, a pHEMT structure, an etching-stop spacer layer, and an HBT structure. The pHEMT structure comprises a buffer layer, a bottom barrier layer, a first channel spacer layer, a channel layer, a second channel spacer layer, a Schottky spacer layer, a Schottky donor layer, a Schottky barrier layer, an etching-stop layer, and at least one cap layer. By introducing the first channel spacer layer and the second channel spacer layer to reduce the density of the dislocations and to reduce the compressive strain in the pseudomorphic channel layer.

Abstract: The present disclosure relates to a gallium-nitride (GaN) transistor device having a composite gallium nitride layer with alternating layers of GaN and aluminum nitride (AlN). In some embodiments, the GaN transistor device has a first GaN layer disposed above a semiconductor substrate. An AlN inter-layer is disposed on the first GaN layer. A second GaN layer is disposed on the AlN inter-layer. The AlN inter-layer allows for the thickness of the GaN layer to be increased over continuous GaN layers, mitigating bowing and cracking of the GaN substrate, while improving the breakdown voltage of the disclosed GaN device.

Abstract: Various embodiments provide a power transistor arrangement, which may include a carrier including at least a main region, a first terminal region and a second terminal region being electrically isolated from each other; a first power transistor having a control electrode, a first power electrode and a second power electrode, and being arranged on the main region of the carrier such that its first power electrode is facing towards and is electrically coupled to the main region of the carrier; a second power transistor having a control electrode, a first power electrode and a second power electrode, and being arranged on the terminal regions of the carrier such that its control electrode and its first power electrode are facing towards the terminal regions, and having its control electrode being electrically coupled to the first terminal region and its first power electrode being electrically coupled to the second terminal region.

Abstract: There are disclosed herein various implementations of a short circuit protected composite switch and a circuit including such a switch. In one exemplary implementation, such a short circuit protected composite switch includes a III-N field-effect transistor (FET) having a drain, a source, and a gate, and a high current group IV FET coupled in series with the III-N FET and configured to limit a current through the III-N FET. The short circuit protected composite switch also includes another group IV FET coupled between the gate and the source of the III-N FET, and another transistor coupled between the gate of the III-N FET and a source of the high current group IV FET.

Abstract: There are disclosed herein various implementations of an integrated half-bridge circuit with low side and high side composite switches. In one exemplary implementation, such an integrated half-bridge circuit includes a III-N body including first and second III-N field-effect transistors (FETs) monolithically integrated with and situated over a first group IV FET. The integrated half-bridge circuit also includes a second group IV FET stacked over the III-N body. The first group IV FET is cascoded with the first III-N FET to provide one of the low side and the high side composite switches, and the second group IV FET is cascoded with the second III-N FET to provide the other of the low side and the high side composite switches.

Abstract: A magnetic memory cell is formed including a magneto tunnel junction (MTJ) and an access transistor, which is used to access the MTJ in operation. The access transistor, which is formed on a silicon substrate, includes a gate, drain and source with the gate position substantially perpendicular to the plane of the silicon substrate thereby burying the gate and allowing more surface area on the silicon substrate for formation of additional memory cells.

Abstract: Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing.

Abstract: A high electron mobility transistor (HEMT) according to example embodiments includes a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a reverse diode gate structure on the second semiconductor layer. A source and a drain may be on at least one of the first semiconductor layer and the second semiconductor layer. A gate electrode may be on the reverse diode gate structure.

Abstract: To provide a semiconductor device in which a rectifying element capable of reducing a leak current in reverse bias when a high voltage is applied and reducing a forward voltage drop Vf and a transistor element are integrally formed on a single substrate. A semiconductor device has a transistor element and a rectifying element on a single substrate. The transistor element has an active layer formed on the substrate and three electrodes (source electrode, drain electrode, and gate electrode) disposed on the active layer. The rectifying element has an anode electrode disposed on the active layer, a cathode electrode which is the drain electrode, and a first auxiliary electrode between the anode electrode and cathode electrode.

Abstract: The present invention relates to compound semiconductor ESD protection devices of three types. The device comprises a multi-gate enhancement mode FET (E-FET). For the type I compound semiconductor ESD protection device, the source electrode is connected to the plural gate electrodes through at least one first resistor, and the drain electrode is connected to the plural gate electrodes through at least one second resistor. For the type II compound semiconductor ESD protection device, the plural gate electrodes are connected to at least one of the inter-gate regions between two adjacent gate electrodes through at least one fourth resistor. For the type III compound semiconductor ESD protection device, the plural gate electrodes are connected to the source or drain electrodes through at least one seventh resistor. Any two gate electrodes in the three types of compound semiconductor ESD protection devices can be connected by a resistor.

Abstract: A semiconductor device includes an etch-stop layer between a first layer of a field-effect transistor and a second layer of a bipolar transistor, each of which includes at least one arsenic-based semiconductor layer. A p-type layer is between the second layer and the etch-stop layer, and the device can include an n-type layer deposited between the etch-stop layer and p-type layer. The p-type layer provides an electric field that inhibits intermixing of the InGaP layer with layers in the first and second layers.

Abstract: A protection clamp is provided between a first terminal and a second terminal, and includes a multi-gate high electron mobility transistor (HEMT), a current limiting circuit, and a forward trigger control circuit. The multi-gate HEMT includes a drain/source, a source/drain, a first depletion-mode (D-mode) gate, a second D-mode gate, and an enhancement-mode (E-mode) gate disposed between the first and second D-mode gates. The drain/source and the first D-mode gate are connected to the first terminal and the source/drain and the second D-mode gate are connected to the second terminal. The forward trigger control and the current limiting circuits are coupled between the E-mode gate and the first and second terminals, respectively. The forward trigger control circuit provides an activation voltage to the E-mode gate when a voltage of the first terminal exceeds a voltage of the second terminal by a forward trigger voltage.

Abstract: A high electron mobility transistor includes a source, a gate and a drain, a first III-V semiconductor region, and a second III-V semiconductor region below the first III-V semiconductor region. The high electron mobility transistor further includes a compensation structure interposed between the first and second III-V semiconductor regions so that the first and second III-V semiconductor regions are spaced apart from one another by the compensation structure. The compensation structure has a different band gap than the first and second III-V semiconductor regions.

Abstract: A semiconductor device according to the present invention includes a substrate; a nitride semiconductor layer formed above the substrate and having a laminated structure including at least three layers; a heterojunction bipolar transistor formed in a region of the nitride semiconductor layer; and a field-effect transistor formed in a region of the nitride semiconductor layer, the region being different from the region in which the heterojunction bipolar transistor is formed.

Abstract: A monolithic integrated circuit includes: a substrate having a diode region and a transistor region; a first semiconductor layer on the substrate in the diode region and in the transistor region; a second semiconductor layer on the first semiconductor layer in the diode region and in the transistor region; a third semiconductor layer on the second semiconductor layer in the transistor region, but not located in the diode region; a first electrode in the diode region and connected to the first semiconductor layer; a second electrode in the diode region and connected to the second semiconductor layer; and a source electrode, a gate electrode, and a drain electrode which are on the third semiconductor layer.

Abstract: A Schottky contact is disposed atop the surface of the semiconductor. A first Schottky contact metal layer is disposed atop a first portion of the semiconductor surface. A second Schottky contact metal is disposed atop a second portion of the surface layer and joins the first Schottky contact metal layer. A first. Schottky contact metal layer has a lower work function than the second Schottky contact metal layer.

Abstract: Provided is a semiconductor device including: a DC/DC converter circuit, wherein the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected to an input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.

Abstract: A semiconductor device including at least a p-channel field-effect transistor region formed above a compound semiconductor substrate. The p-channel field-effect transistor region includes an undoped buffer layer; a p-type channel layer formed in contact with the buffer layer; a p-type source region and a p-type drain region formed in the channel layer, being separated with each other; and an n-type gate region formed above the channel layer and between the source region and the drain region. The buffer layer is formed having either a multilayer structure including a hole diffusion control layer with a band gap larger than the channel layer, or a single layer structure including only the hole diffusion control layer.

Abstract: According to one embodiment, a rectifying circuit includes a transistor, a rectifying element and a resistor. The transistor includes a control electrode, a first electrode and a second electrode. The rectifying element includes an anode electrode and a cathode electrode. The cathode electrode is electrically connected to the first electrode. The resistor includes one end and one other end. The One end of the resistor is electrically connected to the control electrode. The one other end of the resistor is electrically connected to the anode electrode.

Abstract: Example embodiments relate to semiconductor devices and/or methods of manufacturing the same. According to example embodiments, a semiconductor device may include a first heterojunction field effect transistor (HFET) on a first surface of a substrate, and a second HFET. A second surface of the substrate may be on the second HFET. The second HFET may have different properties (characteristics) than the first HFET. One of the first and second HFETs may be of an n type, while the other thereof may be of a p type. The first and second HFETs may be high-electron-mobility transistors (HEMTs). One of the first and second HFETs may have normally-on properties, while the other thereof may have normally-off properties.

Abstract: A protection circuit including a multi-gate high electron mobility transistor (HEMT), a forward conduction control block, and a reverse conduction control block is provided between a first terminal and a second terminal. The multi-gate HEMT includes an explicit drain/source, a first depletion-mode (D-mode) gate, a first enhancement-mode (E-mode) gate, a second E-mode gate, a second D-mode gate, and an explicit source/drain. The drain/source and the first D-mode gate are connected to the first terminal and the source/drain and the second D-mode gate are connected to the second terminal. The forward conduction control block turns on the second E-mode gate when a voltage difference between the first and second terminals is greater than a forward conduction trigger voltage, and the reverse conduction control block turns on the first E-mode gate when the voltage difference is more negative than a reverse conduction trigger voltage.