Abstract: On two active areas formed in a semiconductor substrate, source electrodes, gate electrodes, and drain electrodes are disposed symmetrically to each other. A gate pad section electrically connected to both gate electrodes is disposed at one side of the active areas, and a drain pad section electrically connected to both drain electrodes is disposed at the other side of the active areas. A source pad section electrically connected to one source electrode is disposed at one side of the gate pad section and the drain pad section, and a source pad section electrically connected to the other source electrode is disposed at the other side of the gate pad section and the drain pad section. An input slot line is formed between the gate pad section and the source pad sections, and an output slot line is formed between the drain pad section and the source pad sections.

Abstract: A low voltage regulator integrated circuit for high speed/high frequency circuits incorporates a field effect transistor switch with a heterojunction bipolar transistor in order to reduce voltage requirements of the circuit and allow lower power voltages to be regulated. A first field effect transistor connects an unregulated power input terminal to a regulated power output terminal with a bias circuit including the heterojunction bipolar transistor provided to maintain conductance of the field effect transistor in regulating a voltage on the output terminal. A second field effect transistor can be included in the circuit to provide a power down or power saving mode of operation. An input voltage range of the voltage regulator is reduced from 3-3.5 V to 2-2.3 V using the integrated field effect transistor/heterojunction bipolar transistor device structure.

Abstract: A semiconductor device comprises a semiconductor substrate, a first semiconductor layer under compressive strain formed on the semiconductor substrate, a p-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed in a predetermined region of the first semiconductor layer, a second semiconductor layer in a lattice-relaxation condition formed on the first semiconductor layer in a region other than the predetermined region with an insulating film lying therebetween, wherein the insulating film has an opening and the first and second semiconductor layers are connected through the opening, a third semiconductor layer under tensile strain formed on the second semiconductor layer, and an n-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed in the third semiconductor layer.

Abstract: A semiconductor functional device includes a semi-insulating semiconductor substrate; a resonant tunneling structure which includes, on the substrate, an n-type collector layer, an epitaxial multilayer structure including a double barrier structure constituted of a plurality of barrier layers holding a well layer therebetween, and an n-type emitter layer; an emitter electrode formed on the emitter layer; and a collector electrode formed on the collector layer. An undoped semiconductor barrier layer is interposed between the semi-insulating semiconductor substrate and the collector layer.

Abstract: A MOSFET device utilizes the gate depletion effect to reduce the oxide field over the junction area. Since the gate depletion effect is present in the non-conducting off state for n.sup.+ gate PMOS devices and p.sup.+ gate NMOS devices, performance degradation is overcome. The level of doping of the gate is critical. In order to prevent gate depletion in the conducting, on state, the NMOS FET must use a highly doped n.sup.+ gate. The PMOS FET n.sup.+ gate must be non-degeneratively doped in order to utilize the advantage of the gate depletion in the non-conducting, off state. This is accomplished by implanting different doses of the same dopant type into the different gates. The MOSFET device can be implemented equally well for n.sup.+ gate PMOS FET devices as well as for p.sup.+ gate NMOS FET devices.

Abstract: A T/R switch/LNA for a radar's active array antenna includes dissimilar semiconductor devices in a monolithic microwave integrated circuit (MMIC). The devices are selected to best meet the functional requirements of the T/R switch/LNA. In particular, the LNA is realized with a HEMT and the T/R switch is realized with HBTs. The dissimilar devices are adapted from first and second heterostructures that are arranged to be coplanar and separated by an isolation layer.

Abstract: An epitaxial structure and method of manufacture for a field-effect transistor capable of high-speed low-noise microwave, submillimeterwave and millimeterwave applications. Preferably, the epitaxial structure includes a donor layer and/or buffer layer made from a semiconductor material having the formula AlP.sub.0.39+y Sb.sub.0.61-y.

Abstract: By forming an isolated semiconductor layer or electrode layer on a semiconductor surface between neighboring field effect transistors and element separating trenches which are deep enough to reach at least the semi-insulating substrate or the hetero junction interface on the buffer layer, low frequency oscillation of a compound semiconductor integrated circuit can be reduced. By controlling the thickness of the buffer layer having a hetero junction to at most 150 nm, the low frequency oscillation can be reduced. By forming materials separating adjacent elements with a width of at most 2 .mu.m which reach from the element region surface to the buffer layer having hetero junction so as to enclose the element regions and etched regions in the neighborhood of the elements or so as to enclose the element regions in the etched regions and by controlling the angle of the sides of the etched regions against the semiconductor layer surface to 10.degree. to 60.degree., wires can be prevented from short-circuiting.

Abstract: A high electron mobility transistor type group III-V compound semiconductor device includes a substrate of a group III-V compound semiconductor, an electron transfer layer of a group III-V compound semiconductor formed on the substrate, an impurity doped electron supply layer of a group III-V compound semiconductor having a wider band gap and smaller electron affinity than the electron transfer layer, and a spacer layer of a group III-V compound semiconductor having a lattice mismatch with the electron supply layer, the spacer layer being formed between the electron transfer layer and the electron supply layer. A HEMT type group III-V compound semiconductor device is provided which uses an Si-doped electron supply layer of material such as InGaP other than AlGaAs and has good device properties.

Abstract: This is a vertical field-effect resonant tunneling transistor device comprising: a semi-conducting substrate 46; a drain region 48 above the semi-conducting substrate; a multiple-barrier multi-well resonant tunneling diode 52, 54, 56, 58, 60 above the drain layer; a two dimensional electron gas heterostructure 64 above the multiple-barrier multi-well resonant tunneling diode; a source region 72 extending through the two dimensional electron gas and above the multiple-barrier multi-well resonant tunneling diode; ohmic contacts 70 on the source region, wherein the source region provides an ohmic connection to the two dimensional electron gas; and gate s! 68, 74 besides the source region.

Abstract: The circuit comprises a heterojunction formed between a layer (6) comprising an III-V semiconductor material having a wide forbidden band and a layer (5) comprising an III-V semiconductor material having a narrow forbidden band and whose crystal lattice mismatch with the remainder of the structure is such that the layer comprising the narrow forbidden band material is under uniaxial compression strain in the plane of the layer.According to the invention the thickness of the layer (6) comprising the wide forbidden band material is selected to be smaller for the p-channel transistor than for the n-channel transistor, the ratio of these respective thicknesses being a predetermined ratio that is a function of the relative tunnel transparency for holes compared with that for electrons.

Abstract: An electrically isolated MESFET includes a compound semiconductor substrate; a plurality of compound semiconductor layers disposed on the compound semiconductor substrate; a MESFET structure in a prescribed region of the compound semiconductor layers; an electrically isolating region in the compound semiconductor layers surrounding and electrically isolating the MESFET structure from the compound semiconductor layers outside the electrically isolating region, wherein the compound semiconductor layer most remote from the compound semiconductor substrate has the highest conductivity of the compound semiconductor layers; a recess penetrating the compound semiconductor layer most remote from the compound semiconductor substrate and at least the compound semiconductor layer adjacent the compound semiconductor layer most remote from the compound semiconductor substrate, the recess dividing the compound semiconductor layer most remote from the compound semiconductor substrate into mutually separated first and second

Abstract: There is disclosed a field effect transistor having a channel layer, an electron supply layer, and a spacer layer formed between the channel layer and the electron supply layer. The spacer layer has a thickness for spatially separating a two-dimensional electron gas from donor ions in the electron supply layer, and for forming the two-dimensional electron gas in the channel layer by the Coulomb force of the donor ions. The spacer layer material has better high frequency characteristics than that of the electron supply layer.

Abstract: A HIGFET having a gate pad situated over a non conducting portion of the channel layer of the heterostructure wafer. The method of producing this device involves application of a very thin layer of gate metal on the wafer to protect the wafer surface during further processing. A photoresist coating is formed over the active area of the channel layer of the FET. An ion isolation implantation is applied to the wafer resulting in a non conducting portion of the channel layer that is not covered by the photoresist layer. The photoresist layer is removed and a thick layer of gate metal is applied on the thin layer of gate metal. The gate layers are fashioned into a pad over the non conducting portion of the channel layer and at least one finger over the conducting portion of the channel layer, resulting in the gate having minimized parasitic gate capacitance.

Abstract: A quantum interference device has semiconductor heterojunctions laminated on a semiconductor substrate for forming a two-dimensional electron gas channel. On the semiconductor heterojunctions are formed a first, a second and a third electrode which, upon the application of a negative voltage, form a depletion region within the semiconductor heterojunctions, thereby making the resulting two-dimensional electron gas channel a quantum wire of a stub structure comprising an entrance and an exit for electron waves, and a stub formed between the entrance and the exit. The second and third electrodes each have a first side substantially parallel to a side of the first electrode. The second and third electrodes also have a second side parallel to each other's second side. On a site near the edge of said stub is provided a fourth electrode for defining the effective length of the stub by a voltage applied thereto.

Abstract: A method of producing on a substrate an in-plane-gate transistor includes producing a channel portion in which a quasi-one-dimensional conductive channel electrically connecting a source region and a drain region is generated and producing gate portions, each portion including a gate electrode layer for controlling generation and forfeiture of the quasi-one-dimensional conductive channel so that an upper surface of the gate layer and the quasi-one-dimensional conductive channel are positioned substantially in the same plane, on both sides of the channel portion on the substrate. Gaps between the channel portion and the gate portions are controlled by side walls produced self-aligningly on the side wall surfaces of the channel portion. Thus, gaps of a high aspect ratio can be produced between the channel portion and the gate portions without being limited by the dry etching technique.

Abstract: The present invention encompasses a method for providing the same ohmic material contact (120, 122, 124) to N-type and P-type regions (70, 80) of a III-V semiconductor device. Specifically, an N-type region (70) extending through a semiconductor structure is formed. Additionally, a P-type region (80) extending through the substrate is formed. The P-type region (80) may be heavily doped with P-type impurities (81). A first ohmic region (117) is formed, contacting the N-type region (70). The first ohmic region may comprise an ohmic material including metal and an N-type dopant. A second ohmic region (119) is formed, contacting the P-type region (80, 81). The second ohmic region comprises the same ohmic material as the first ohmic region. One ohmic material that may be used is nickel-germanium-tungsten.

Abstract: Generally, and in one form of the invention, a semi-insulating semiconductor substrate 10 is provided having a first surface. An HBT subcollector region 12 of a first conductivity type is implanted in the substrate 10 at the first surface. Next, an i-layer 16 is grown over the first surface, over which an HFET electron donor layer 18 of the first conductivity type is grown, the electron donor layer 18 having a wider energy bandgap than the i-layer. Subsequently, an HFET contact layer 20 of the first conductivity type is grown over the HFET donor layer 18. Next, the HFET contact 20 and donor 18 layers are etched away over the HBT subcollector region 12, after which an HBT base layer 22 of a second conductivity type is selectively grown on the i-layer 16 over the HBT subcollector region 12. Then, an HBT emitter layer 24/26/28 of the first conductivity type is selectively grown over the HBT base layer 22, the HBT emitter layer 24/26/28 having a wider energy bandgap than the HBT base layer 22.

Abstract: Disclosed is a system with at least two complementary transistors, having n and p channels but comprising a heterostructure of junctions between III-V group materials. In order to balance the threshold voltages in the two channels, namely the n (2DEG) and p (2DHG) channels, at least two p and n delta doped layers are included in two layers of the heterostructure, at levels included between the channels (2DEG, 2DHG) and the gate electrodes. The n delta doped layer is then removed by localized etching right above the p channel transistor. Application to fast logic circuits.

Abstract: A Double Heterojunction Bipolar Transistor (DHBT) and the method of fabrication therefor. First a layered wafer is prepared on a semi-insulating GaAs substrate. The bottom wafer layer is n.sup.+ GaAs, followed by n.sub.- AlGaAs, a thin layer of n AlGaAs (which form the DHBT's collector) and a base layer of p.sup.+ GaAS. A layered plug fills a trench etched in the base layer. The bottom two plug layers are AlGaAs and the top plug layer is GaAs. Next, an emitter is ion-implanted into the plug core and an extrinsic base region is ion-implanted. Finally, base, emitter and collector contacts are formed.

Abstract: An integrated circuit including a wafer having a GaAs substrate, an un-doped GaAs layer, and a GaAs active layer. This active layer may have an HEMT structure to improve its operation speed. Also, the substrate may a multi-layer structure to form a three dimensional capacitor. At least one mesa portion is formed on the substrate by removing a portion of the un-doped GaAs layer and GaAs active layer. A source electrode, for example, is formed on the mesa portion, and a ground electrode is formed on an exposed surface of the substrate. These electrodes are connected to each other by means of a wiring metal layer. As a result, the source electrode is easily grounded without using a long bonding wire.

Abstract: An integrated field-effect initiator useful for the pyrotechnic initiation or detonation of explosives includes a semiconductor channel of a first conductivity type bounded on opposite ends by semiconductor material of an opposite conductivity type to define two PN junctions in the conduction path. The semiconductor channel is doped to define a conduction path of sufficiently high impedance to prevent unintended initiation. A gate electrode is positioned adjacent the channel and separated therefrom by an insulation layer to affect the conductivity of the channel as a function of a potential applied to the gate. In normal operation, an initiation electrical potential is applied to the opposite ends of the conduction path and a gate potential is applied to the gate to effect field-enhanced conduction in the path sufficient to allow vaporization of the path to cause initiation of an explosive material in contact with the path.

Abstract: The present Field Effect Real Space Transistor, or FERST, is a four terminal device with S, G, C, and D representing the source, gate, collector, and drain, respectively. The S, G, and D terminals can be likened to those of the MODFET. The collector name is borrowed from other real space transfer devices. Surrounding the entire device is an oxygen implant isolation. The source and drain ohmic contacts penetrate to the 150 .ANG. GaAs channel while the collector ohmic contact does not penetrate due to its position upon an elevated submesa. AlGaAs layers are used as etch stops during processing of the device and a Schottky barrier gate is placed on an undoped layer. Channel carriers are provided by modulation doping the lower barrier of the channel. An Al.sub.0.35 Ga.sub.0.65 As layer on the upper channel side is used as a real space transfer barrier. In operation and under appropriate bias conditions, real space transfer occurs across this upper barrier and into the collector.

Abstract: A long wavelength transmitter OEIC includes a transverse direction current injection type semiconductor laser and a high electron mobility transistor which are integrated on a semi-insulating substrate. The semiconductor laser includes at least an AlGaInAs lower cladding layer, a quantum well active layer and a high resistivity AlGaInAs upper cladding layer successively grown on the semi-insulating substrate, disordered regions formed in the quantum well active layer by diffusions of p type and n type dopants, and an active region sandwiched by the disordered regions. The transistor includes an operating layer and a carrier supplying layer both including AlGaInAs series material and formed on the high resistivity AlGaInAs upper cladding layer. This transistor uses the upper cladding layer as a leakage current preventing layer. This structure can be formed by only one epitaxial growth, resulting in low cost.

Abstract: A low power heterojunction field effect transistor (10, 30, 50, 60) capable of operating at low drain currents while having a low intermodulation distortion. A channel restriction region (9, 38, 51) is formed between the gate electrodes (24, 41, 69) and the drain electrodes (25, 46, 65). The channel restriction region (9, 38, 51) depletes the channel layer (13, 33) thereby constricting a channel and lowering a drain saturation current. The channel restriction region (9, 38, 51) may be used to set a desired drain saturation current such that a second derivative of the transconductance with respect to the gate-source voltage is approximately zero and a first derivative of the transconductance with respect to the gate-source voltage is, approximately, a relative maximum at the desired operating point.

Abstract: A monolithic integrated circuit device combines integrated heterostructure acoustic charge transport (HACT) devices and heterostructure insulated gate field effect transistor (HIGFET) devices in a single structure in which the HACT and HIGFET layers are grown in as a contiguous composite heterostructure.

Abstract: In a high speed logic circuit using a vertical hetero-junction bipolar transistor, in which two-dimensional carriers formed at a semiconductor hetero-junction interface are used as a base layer, the uppermost layer being a collector layer, the lowest layer being an emitter layer, two base electrodes making contact with the base layer are disposed so as to put a collector electrode, which is electrically in contact with the collector layer, therebetween. The base electrodes are used at the same time as a source electrode and a drain electrode, respectively, of a field effect transistor using the two-dimensional carriers as an active layer. The high speed logic circuit is so constructed that one of the base electrodes of the bipolar transistor is an input terminal; the other is connected with a power supply; the emitter is grounded; and the collector is an output terminal.

Abstract: In a waveguide type photodetector for receiving and detecting a light guided thereinto, a groove is formed in a semiconductor substrate, a waveguide layer is formed on the semiconductor substrate, and a light absorbing layer for absorbing a light propagated through a waveguide in the waveguide layer is formed on the waveguide layer. The waveguide is formed as a three-dimensional waveguide formed in the waveguide layer due to the presense of the groove. The three-dimensional waveguide is maintained also under the light absorbing layer since the refractive index of a portion layered on the groove formed in the substrate is made large than that of portions other than this portion layered above the groove.

Abstract: A quantum semiconductor device comprises a channel region formed with a two-dimensional carrier gas, a Schottky electrode structure provided on the channel region for creating a depletion region in the channel region to extend in a lateral direction such that the two-dimensional carrier gas is divided into a first region and a second region, a quantum point contact formed in the depletion region to connect the first and second regions of the two-dimensional carrier gas in a longitudinal direction, an emitter electrode provided on the channel region in correspondence to the first region of the two-dimensional carrier gas, one or more collector electrodes provided on the channel region in correspondence to the second region of the two-dimensional carrier gas, and another Schottky electrode structure provided in correspondence to the first region for creating a depletion region therein such that a path of the carriers entering into the quantum point contact is controlled asymmetrical with respect to a hypothetic

Abstract: A metal oxide semiconductor field effect transistor with heterostructure has a silicon substrate. Heavily-doped source and drain layers which are different in conductivity type from the substrate are spaced apart from each other in the surface portion of the substrate. A gate electrode of polycrystalline silicon is disposed above the substrate, and is electrically insulated from the substrate by a gate insulation layer made of thermal silicon oxide thin film. A silicon germanium layer is laterally provided in a preselected substrate surface section positioned between the source and drain layers. This layer partially overlaps the source and drain layers at both of its end portions, and is thus electrically in contact with these layers. The silicon germanium layer acts as a channel of the transistor.

Abstract: Complementary heterostructure field effect transistors (30) with complementary devices having complementary gates (40, 50) and threshold adjusting dopings are disclosed. Preferred embodiment devices include a p.sup.+ gate (50) formed by diffusion of dopant to convert n.sup.+ gate material to p.sup.+, and a pulse-doped layer adjacent the two-dimensional carrier gas channels to adjust threshold voltages. Further preferred embodiments have the conductivity-type converted gate (50) containing a residual layer of unconverted n.sup.+ which cooperates with the pulse-doped layer threshold shifting to yield threshold voltages which are small and positive for n-channel and small and negative for p-channel devices.

Abstract: A three-terminal hot-electron device, in particular a two dimensional electron gas base transistor which can be fabricated by molecular beam epitaxy (MBE). The two-dimensional electron gas is induced in an undoped GaAs quantum well by a modulation doping is used as the base of the transistor and permits a common-base current gain .alpha. to be achieved as high as 0.96 under a collector bias of 2.5 V and an emitter current of 3 mA.

Abstract: A semiconductor device includes an InP substrate, an intrinsic InGaAs channel layer formed on the InP substrate and lattice matched to the InP substrate, a doped GaAsSb carrier supply layer formed on the intrinsic InGaAs channel layer and lattice matched to the InP substrate, a gate electrode formed on the doped GaAsSb carrier supply layer, and a source electrode and a drain electrode which are respectively formed on the doped GaAsSb carrier supply layer and located on both sides of the gate electrode.

Abstract: Present invention is to provide a process for producing an opto-electronic integrated circuit comprising a field effect transistor as an electronic device and a photo-diode as an optical device both formed on an InP substrate,the field effect transistor comprising a high electron mobility transistor having:a GaInAs layer epitaxially grown in the InP substrate in a preset region thereof, a n-AlInAs layer epitaxially grown on the GaInAs layer, a gate electrode formed on the AlInAs layer, and a source electrode and a drain electrode formed on the AlInAs layer with the gate electrode therebetween, andthe photo-diode comprising a PIN photo-diode having:the GaInAs layer epitaxially grown on the InP substrate near the region of the field effect transistor simultaneously with the growth of that of the field effect transistor, the n-AlInAs layer epitaxially grown on the GaInAs layer simultaneously with the growth of that of the field effect transistor, a n-InP layer epitaxially grown on the n-AlInAs layer, an undoped

Abstract: Generally, and in one form of the invention, a semi-insulating semiconductor substrate 10 is provided having a first surface. An HBT subcollector region 12 of a first conductivity type is implanted in the substrate 10 at the first surface. Next, an i-layer 16 is grown over the first surface, over which an HFET electron donor layer 18 of the first conductivity type is grown, the electron donor layer 18 having a wider energy bandgap than the i-layer. Subsequently, an HFET contact layer 20 of the first conductivity type is grown over the HFET donor layer 18. Next, the HFET contact 20 and donor 18 layers are etched away over the HBT subcollector region 12, after which an HBT base layer 22 of a second conductivity type is selectively grown on the i-layer 16 over the HBT subcollector region 12. Then, an HBT emitter layer 24/26/28 of the first conductivity type is selectively grown over the HBT base layer 22, the HBT emitter layer 24/26/28 having a wider energy bandgap than the HBT base layer 22.