Combined With Diverse Type Device Patents (Class 257/195)
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Patent number: 7262446Abstract: A semiconductor device which is capable of operating with a single positive power supply and has a low gate resistance, and a process for production thereof. The semiconductor device includes a channel layer (which constitutes a current channel), a first semiconductor layer formed on said channel layer, a second semiconductor layer in an island-like shape doped with a conductive impurity and formed on said first semiconductor layer, and a gate electrode formed on said second semiconductor layer, wherein said first and second semiconductor layers under said gate electrode have a conductive impurity region formed therein to control the threshold value of current flowing through said channel layer, and the conductive impurity region formed in second semiconductor layer is doped with a conductive impurity more heavily than in the conductive impurity region formed in said first semiconductor layer.Type: GrantFiled: April 11, 2005Date of Patent: August 28, 2007Assignee: Sony CorporationInventor: Takayuki Toyama
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Patent number: 7250641Abstract: The nitride semiconductor device according to one embodiment of the present invention comprises: a silicon substrate; a first aluminum gallium nitride (AlxGa1?xN (0?x?1)) layer formed as a channel layer on the silicon substrate in an island shape; and a second aluminum gallium nitride (AlyGa1?yN (0?y?1, x<y)) layer formed as a barrier layer of a first conductive type or i-type on the first aluminum gallium nitride layer.Type: GrantFiled: October 12, 2004Date of Patent: July 31, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Ichiro Omura
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Patent number: 7250643Abstract: A semiconductor device includes: a gate electrode that is provided on a semiconductor layer; a source electrode and a drain electrode that are provided on the semiconductor layer so as to interpose the gate electrode; a source wall that extends from the source electrode to a point between the gate electrode and the drain electrode through the region above the gate electrode, the source wall having a joining portion in the extending region; and an electrode portion that is joined to the joining portion and has a region extending closer to the drain electrode than the joining portion.Type: GrantFiled: March 30, 2006Date of Patent: July 31, 2007Assignee: Eudyna Devices Inc.Inventor: Masahiro Nishi
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Patent number: 7230284Abstract: AlGaN/GaN HEMTs are disclosed having a thin AlGaN layer to reduce trapping and also having additional layers to reduce gate leakage and increase the maximum drive current. One HEMT according to the present invention comprises a high resistivity semiconductor layer with a barrier semiconductor layer on it. The barrier layer has a wider bandgap than the high resistivity layer and a 2DEG forms between the layers. Source and drain contacts contact the barrier layer, with part of the surface of the barrier layer uncovered by the contacts. An insulating layer is included on the uncovered surface of the barrier layer and a gate contact is included on the insulating layer. The insulating layer forms a barrier to gate leakage current and also helps to increase the HEMT's maximum current drive. The invention also includes methods for fabricating HEMTs according to the present invention. In one method, the HEMT and its insulating layer are fabricated using metal-organic chemical vapor deposition (MOCVD).Type: GrantFiled: July 23, 2002Date of Patent: June 12, 2007Assignee: Cree, Inc.Inventors: Primit Parikh, Umesh Mishra, Yifeng Wu
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Patent number: 7196362Abstract: A high-accuracy, threshold-voltage-settable, field-effect transistor and a semiconductor device including the field-effect transistor are provided. The field-effect transistor, having a channel layer through which carriers move between a source and a drain, includes a doped layer for adjusting the threshold voltage of the transistor by changing the carrier concentration in the channel layer. In particular, the doped layer is provided in a semiconductor substrate by implantation of impurities.Type: GrantFiled: May 26, 2004Date of Patent: March 27, 2007Assignee: Sony CorporationInventor: Shinichi Wada
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Patent number: 7183592Abstract: A semiconductor structure a structure with an enhancement mode transistor device disposed in a first region and depletion mode transistor device disposed in a laterally displaced second region. The structure has a channel layer for the depletion mode and enhancement mode transistor devices. An enhancement mode transistor device InGaP etch stop/Schottky contact layer is disposed over the channel layer; a first layer different from InGaP disposed on the InGaP layer; a depletion mode transistor device etch stop layer is disposed on the first layer; and a second layer disposed on the depletion mode transistor device etch stop layer. The depletion mode transistor device has a gate recess passing through the second layer and the depletion mode transistor device etch stop layer and terminating in the first layer. The enhancement mode transistor device has a gate recess passing through the second layer, the depletion mode transistor device etch stop layer, the first layer, and terminating in the InGaP layer.Type: GrantFiled: May 26, 2004Date of Patent: February 27, 2007Assignee: Raytheon CompanyInventor: Kiuchul Hwang
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Patent number: 7183593Abstract: A heterostructure resistor comprises a doped region formed in a portion of a semiconductor substrate, the substrate comprising a first semiconductor material having a first natural lattice constant. The doped region comprises a semiconductor layer overlying the semiconductor substrate. The semiconductor layer comprises a second semiconductor material with a second natural lattice constant.Type: GrantFiled: December 24, 2003Date of Patent: February 27, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yee-Chia Yeo, Wen-Chin Lee, Chih-Hsin Ko, Chung-Hu Ge, Chun-Chieh Lin, Chenming Hu
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Patent number: 7071499Abstract: In a heterojunction field effect type semiconductor device, a channel layer is formed over a GaAs substrate, and a first semiconductor layer including no aluminum is formed over the channel layer. First and second cap layers of a first conductivity type are formed on the first semiconductor layer, to create a recess on the first semiconductor layer. First and second ohmic electrodes are formed on the first and second cap layers, respectively. A second semiconductor layer of a second conductivity type is formed on the first semiconductor layer within the recess, and the semiconductor layer is isolated from the first and second cap layers. A gate electrode is formed on the second semiconductor layer.Type: GrantFiled: November 25, 2003Date of Patent: July 4, 2006Assignee: NEC Electronics CorporationInventor: Yasunori Bito
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Patent number: 7064359Abstract: A switching semiconductor device includes a first compound layer formed on a single crystal substrate which includes silicon carbide or sapphire, and including a general formula InxGa1-xN, where 0?x?1; a second compound layer formed on the first compound layer, and including a general formula InyALzGa1-y-zN, where 0?y?1 and 0<z?1; and a gate electrode formed on the second compound layer. The gate electrode is electrically connected to a resistance element formed on a first interlayer insulating film that covers the gate electrode, through a metal wiring formed on a second interlayer insulating film that covers the first interlayer insulating film.Type: GrantFiled: August 6, 2004Date of Patent: June 20, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hidetoshi Ishida, Tsuyoshi Tanaka, Daisuke Ueda
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Patent number: 7038253Abstract: According to the present invention, there is provided a new GaN-based field effect transistor of a normally-off type, which has an extremely small ON resistance during operation and is capable of a large-current operation.Type: GrantFiled: August 18, 2004Date of Patent: May 2, 2006Assignee: The Furukawa Electric Co., Ltd.Inventors: Seikoh Yoshida, Masayuki Sasaki
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Patent number: 7015519Abstract: Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for fabricating the FET on a semi-insulating GaAs substrate; fabricating a highly doped thick GaAs layer serving as the cap layer for the FET and the subcollector layer for the HBT; and producing a second set of epitaxial layers for fabricating the HBT.Type: GrantFiled: February 20, 2004Date of Patent: March 21, 2006Assignee: Anadigics, Inc.Inventors: Oleh Krutko, Kezhou Xie, Mohsen Shokrani, Aditya Gupta, Boris Gedzberg
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Patent number: 7009209Abstract: A silicon carbide semi-insulating epitaxy layer is used to create power devices and integrated circuits having significant performance advantages over conventional devices. A silicon carbide semi-insulating layer is formed on a substrate, such as a conducting substrate, and one or more semiconducting devices are formed on the silicon carbide semi-insulating layer. The silicon carbide semi-insulating layer, which includes, for example, 4H or 6H silicon carbide, is formed using a compensating material, the compensating material being selected depending on preferred characteristics for the semi-insulating layer. The compensating material includes, for example, boron, vanadium, chromium, or germanium. Use of a silicon carbide semi-insulating layer provides insulating advantages and improved thermal performance for high power and high frequency semiconductor applications.Type: GrantFiled: January 3, 2002Date of Patent: March 7, 2006Assignee: Mississippi State University Research and Technology Corporation (RTC)Inventors: Jeffrey B. Casady, Michael Mazzola
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Patent number: 6995407Abstract: A photonic digital-to-analog converter employing a plurality of heterojunction thyristor devices that are configured to convert a digital word encoded by a parallel digital optical signal (e.g., a plurality of synchronous optical bits) to an output analog electrical signal whose magnitude corresponds to the digital word. Each heterojunction thyristor device is configured to convert an optical bit in the digital word to a corresponding digital electrical signal. The voltage levels (e.g., magnitudes) of the ON state of the digital electrical signals produced by the heterojunction thyristor devices may be supplied by voltage divider networks coupled between the cathode terminal of the devices and ground potential or voltage reference sources coupled to the input terminals of the heterojunction thyristor devices. In this manner, electrical signals whose magnitude corresponds to contribution of each optical bit in the digital word are produced.Type: GrantFiled: December 19, 2002Date of Patent: February 7, 2006Assignees: The University of Connecticut, Opel, Inc.Inventors: Geoff W. Taylor, Jianhong Cai
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Patent number: 6992337Abstract: A heterojunction bipolar transistor (HBT), comprises a collector formed over a substrate, a base formed over the collector, an emitter formed over the base, and a tunneling suppression layer between the collector and the base, the tunneling suppression layer fabricated from a material that is different from a material of the base and that has an electron affinity equal to or greater than an electron affinity of the material of the base.Type: GrantFiled: April 2, 2004Date of Patent: January 31, 2006Assignee: Agilent Technologies, Inc.Inventors: Sandeep Bahl, Nicolas J. Moll
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Patent number: 6972461Abstract: A structure for use as a MOSFET employs an SOI wafer with a SiGe island resting on the SOI layer and extending between two blocks that serve as source and drain; epitaxially grown Si on the vertical surfaces of the SiGe forms the transistor channel. The lattice structure of the SiGe is arranged such that the epitaxial Si has little or no strain in the direction between the S and D and a significant strain perpendicular to that direction.Type: GrantFiled: June 30, 2004Date of Patent: December 6, 2005Assignee: International Business Machines CorporationInventors: Xiangdong Chen, Dureseti Chidambarrao, Geng Wang, Huilong Zhu
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Patent number: 6936839Abstract: A family of optical waveguide structures and high speed optoelectronic/transistor devices are obtained from a multilayer structure that includes a modulation doped quantum well structure formed over a DBR mirror. The optical waveguide structure is realized by implanting n-type ions to form a pair of n-type implant regions that define a waveguide region therebetween. An oxide layer (e.g., SiO2) is deposited over the waveguide region. A thermal annealing operation causes the oxide layer to introduce impurity free vacancy disordering that substantially eliminates absorption in the waveguide region. The waveguide region contributes to lateral confinement of light therein. An etching operation etches through the n-type implant regions to define sidewalls, which are subject to an oxidation operation that produces oxidized sections along the sidewalls. The oxide layer is removed, and a top distributed bragg reflector mirror is formed over the waveguide region. The resulting structure realizes an optical waveguide.Type: GrantFiled: November 12, 2002Date of Patent: August 30, 2005Assignee: The University of ConnecticutInventor: Geoff W. Taylor
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Patent number: 6924516Abstract: A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein: surfaces of the buffer layer are c facets of Ga atoms; a channel layer including GaN or InGaN formed on the buffer layer,wherein: surfaces of the channel layer are c facets of Ga or In atoms; an electron donor layer including AlGaN formed on the channel layer, wherein: surfaces of the electron donor layer are c facets of Al or Ga atoms; a source electrode and a drain electrode formed on the electron donor layer; a cap layer including GaN or InGaAlN formed between the source electrode and the drain electrode, wherein: surfaces of the cap layer are c facets of Ga or In atoms and at least a portion of the cap layer is in contact with the electron donor layer; and a gate electrode formed at least a portion of which is in contact with the cap layer.Type: GrantFiled: August 26, 2004Date of Patent: August 2, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kaoru Inoue, Katsunori Nishii, Hiroyuki Masato
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Patent number: 6908804Abstract: The bipolar transistor comprises a collector region (1) of a semiconductor material having a first doping type, a base region (2) of a semiconductor material having a second doping type, and an emitter region (3) having the first doping type. A junction is present between the emitter region (3) and the base region (2), and, viewed from the junction (4), a depletion region (5) extends into the emitter region (3). The emitter region (3) comprises a layer (6) of a first semiconductor material and a layer (7) of a second semiconductor material. The first semiconductor material has a higher intrinsic carrier concentration than the second semiconductor material. The layer (7) of said second semiconductor material is positioned outside the depletion region (5). The second semiconductor material has such a doping concentration that Auger recombination occurs. The invention also relates to a semiconductor device comprising such a bipolar transistor.Type: GrantFiled: August 27, 2003Date of Patent: June 21, 2005Assignee: Koninklijke Philips Electronics N.V.Inventors: Hendrik Gezienus Albert Huizing, Jan Willem Slotboom, Doede Terpstra, Johan Hendrik Klootwijk, Eyup Aksen
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Patent number: 6876012Abstract: The present invention provides a Hetero-Bipolar Transistor that suppresses a recombination current between electrons in the conduction band of an emitter and holes in the valence band of a base, which results on an enhancement of the current gain of the transistor. The HBT according to the present invention comprises a semi-insulating semiconductor substrate and a series of semiconductor layers on the substrate. The semiconductor layers are a buffer layer, a sub-collector layer a collector layer, a base layer, an emitter layer, an emitter contact layer, and an intermediate layer between the emitter layer and the emitter contact layer. The emitter layer has a carrier concentation of 1.0×1019 cm?3.Type: GrantFiled: February 24, 2003Date of Patent: April 5, 2005Assignee: Sumitomo Electric Industries, Ltd.Inventor: Masaki Yanagisawa
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Patent number: 6872985Abstract: An optoelectronic device and a method of making same. The optoelectronic device comprises a substrate, at least one dielectric waveguide in the substrate, and at least one active semiconductor layer physically bonded to the substrate and optically coupled to the at least one dielectric waveguide in the substrate, the at least one active semiconductor layer being able to generate light, detect light, amplify light or otherwise modulate amplitude or phase of light.Type: GrantFiled: April 5, 2002Date of Patent: March 29, 2005Assignee: HRL Laboratories, LLCInventor: Daniel Yap
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Patent number: 6872966Abstract: There are provided first and second optical waveguides formed on a semiconductor substrate and having upper clad layers and core layers that are separated mutually respectively, first and second phase modulation electrodes formed on the first and second optical waveguides respectively, and first and second slot-line electrodes formed on the semiconductor substrate on both sides of the first and second optical waveguides and connected to the first and second phase modulation electrodes via air-bridge wirings separately respectively.Type: GrantFiled: July 17, 2003Date of Patent: March 29, 2005Assignee: Fujitsu LimitedInventors: Suguru Akiyama, Haruhisa Soda, Shigeaki Sekiguchi
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Patent number: 6867078Abstract: A microwave field effect transistor (10) has a high conductivity gate (44) overlying a double heterojunction structure (14, 18, 22) that has an undoped channel layer (18). The heterojunction structure overlies a substrate (12). A recess layer that is a not intentionally doped (NID) layer (24) overlies the heterojunction structure and is formed with a predetermined thickness that minimizes impact ionization effects at an interface of a drain contact of source/drain ohmic contacts (30) and permits significantly higher voltage operation than previous step gate transistors. Another recess layer (26) is used to define a gate dimension. A Schottky gate opening (42) is formed within a step gate opening (40) to create a step gate structure. A channel layer (18) material of InxGa1?xAs is used to provide a region of electron confinement with improved transport characteristics that result in higher frequency of operation, higher power density and improved power-added efficiency.Type: GrantFiled: November 19, 2003Date of Patent: March 15, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Olin L. Hartin, Lawrence S. Klingbeil, Ellen Y. Lan, Hsin-Hua P. Li, Charles E. Weitzel
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Patent number: 6864533Abstract: A semiconductor substrate includes a first principal plane and a second principal plane opposite this first principal plane. A first semiconductor region is formed on the first principal plane of the semiconductor substrate. Second and third semiconductor regions are formed separately from each other on the first semiconductor region. A gate electrode is formed, via a gate insulator, on the first semiconductor region between the second semiconductor region and the third semiconductor region. An electric conductor is formed up to the semiconductor substrate from the second semiconductor region and electrically connects the second semiconductor region with the semiconductor substrate. A first main electrode is formed on the second principal plane of the semiconductor substrate and is electrically connected to the semiconductor substrate. A second main electrode is formed on the first semiconductor region via insulators and is electrically connected to the third semiconductor region.Type: GrantFiled: September 12, 2001Date of Patent: March 8, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Norio Yasuhara, Akio Nakagawa, Yusuke Kawaguchi, Kazutoshi Nakamura
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Patent number: 6853018Abstract: A semiconductor device which is capable of operating with a single positive power supply and has a low gate resistance, and a process for production thereof. The semiconductor device includes a channel layer (which constitutes a current channel), a first semiconductor layer formed on said channel layer, a second semiconductor layer in an island-like shape doped with a conductive impurity and formed on said first semiconductor layer, and a gate electrode formed on said second semiconductor layer, wherein said first and second semiconductor layers under said gate electrode have a conductive impurity region formed therein to control the threshold value of current flowing through said channel layer, and the conductive impurity region formed in second semiconductor layer is doped with a conductive impurity more heavily than in the conductive impurity region formed in said first semiconductor layer.Type: GrantFiled: July 12, 2002Date of Patent: February 8, 2005Assignee: Sony CorporationInventor: Takayuki Toyama
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Patent number: 6849883Abstract: A MOSFET device including a semiconductor substrate, an SiGe layer provided on top of the semiconductor substrate, an Si layer provided on top of the SiGe layer; and a first isolation region for separating the Si layer into a first region and a second region, wherein the Si layer in the second region is turned into an Si epitaxial layer greater in thickness than the Si layer in the first region. The MOSFET device further includes at least one first MOSFET with the Si layer in the first region serving as a strained Si channel, and at least one second MOSFET with the Si epitaxial layer serving as an Si channel.Type: GrantFiled: March 21, 2003Date of Patent: February 1, 2005Assignee: Oki Electric Industry Co., Ltd.Inventor: Masao Okihara
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Patent number: 6849866Abstract: A family of high speed transistors and optoelectronic devices are obtained on a monolithic substrate by adding two sheets of planar doping together with a wideband cladding layer to the top of a pseudomorphic high electron mobility transistor (PHEMT) structure. The two sheets are of the same polarity which is opposite to the modulation doping of the PHEMT and they are separated by a lightly doped layer of specific thickness. The combination is separated from the PHEMT modulation doping by a specific thickness of undoped material. The charge sheets are thin and highly doped. The top charge sheet achieves low gate contact resistance and the bottom charge sheet defines the capacitance of the field-effect transistor (FET) with respect to the modulation doping layer of the PHEMT. The structure produces a pnp bipolar transistor, enhancement and depletion type FETs, a vertical cavity surface emitting laser, and a resonant cavity detector.Type: GrantFiled: July 23, 2002Date of Patent: February 1, 2005Assignee: The University of ConnecticutInventor: Geoff W. Taylor
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Publication number: 20040262632Abstract: A transistor structure having an gallium arsenide (GaAs) semiconductor substrate; a lattice match layer; an indium aluminum arsenide (InAlAs) barrier layer disposed over the lattice match layer; an InyGa1-yAs lower channel layer disposed on the barrier layer, where y is the mole fraction of In content in the lower channel layer; an InxGa1-xAs upper channel layer disposed on the lower channel layer, where x is the mole fraction of In content in the upper channel layer and where x is different from y; and an InAlAs Schottky layer on the InxGa1-xAs upper channel layer. The lower channel layer has a bandgap greater that the bandgap of the upper channel layer. The lower channel layer has a bulk electron mobility lower than the bulk electron mobility of the upper channel layer where.Type: ApplicationFiled: June 26, 2003Publication date: December 30, 2004Inventors: Philbert F. Marsh, Colin S. Whelan, William E. Hoke
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Patent number: 6809352Abstract: The semiconductor device of the present invention includes: a gallium nitride (GaN) compound semiconductor layer; and a Schottky electrode formed on the GaN compound semiconductor layer, wherein the Schottky electrode contains silicon.Type: GrantFiled: December 27, 2002Date of Patent: October 26, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Katsunori Nishii, Yoshito Ikeda, Hiroyuki Masato, Kaoru Inoue
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Patent number: 6797994Abstract: A transistor structure is provided. This structure has a source electrode and a drain electrode. A doped cap layer of GaxIn1−xAs is disposed below the source electrode and the drain electrode and provides a cap layer opening. An undoped resistive layer of GaxIn1−xAs is disposed below the cap layer and defines a resistive layer opening in registration with the cap layer opening and having a first width. A Schottky layer of AlyIn1−yAs is disposed below the resistive layer. An undoped channel layer is disposed below the Schottky layer. A semi-insulating substrate is disposed below the channel layer. A top surface of the Schottky layer beneath the resistive layer opening provides a recess having a second width smaller than the first width. A gate electrode is in contact with a bottom surface of the recess provided by the Schottky layer.Type: GrantFiled: February 14, 2000Date of Patent: September 28, 2004Assignee: Raytheon CompanyInventors: William E. Hoke, Katerina Y. Hur
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Publication number: 20040173816Abstract: A monolithic electronic device includes a substrate, a semi-insulating, piezoelectric Group III-nitride epitaxial layer formed on the substrate, a pair of input and output interdigital transducers forming a surface acoustic wave device on the epitaxial layer and at least one electronic device (such as a HEMT, MESFET, JFET, MOSFET, photodiode, LED or the like) formed on the substrate. Isolation means are disclosed to electrically and acoustically isolate the electronic device from the SAW device and vice versa. In some embodiments, a trench is formed between the SAW device and the electronic device. Ion implantation is also disclosed to form a semi-insulating Group III-nitride epitaxial layer on which the SAW device may be fabricated. Absorbing and/or reflecting elements adjacent the interdigital transducers reduce unwanted reflections that may interfere with the operation of the SAW device.Type: ApplicationFiled: March 3, 2003Publication date: September 9, 2004Inventor: Adam William Saxler
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Patent number: 6787822Abstract: The heterojunction transistor comprises III-V semiconductor materials with a broad forbidden band material and a narrow forbidden band material. The narrow forbidden band material is an III-V compound containing gallium as one of its III elements and both arsenic and nitrogen as V elements, the nitrogen content being less than about 5%, and the narrow forbidden band material includes at least a fourth III or V element. Adding this fourth element makes it possible to adjust the width of the forbidden band, the conduction band discontinuity &Dgr;Ec, and the valance band discontinuity &Dgr;Ev of the heterojunction. The invention is applicable to making field effect transistors of the HEMT type having a very small forbidden band, and thus having high drain current. It also applies to making heterojunction bipolar transistors of small VBE, and thus capable of operating with power supply voltages that are very low.Type: GrantFiled: November 19, 2001Date of Patent: September 7, 2004Assignee: Picogiga InternationalInventor: Linh T. Nuyen
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Patent number: 6787820Abstract: A semiconductor device includes an AlGaN film formed on a GaN film on a substrate, a gate electrode formed on the AlGaN film, and source and drain electrodes formed on either side of the gate electrode on the AlGaN film. An n-type InxGayAl1-x-yN film is interposed between the source and drain electrodes and the AlGaN film. Alternatively, the semiconductor device includes an n-type InxGayAl1-x-yN film formed on a GaN film on a substrate, a gate electrode formed on the InxGayAl1-x-yN film, and source and drain electrodes formed on either side of the gate electrode on the InxGayAl1-x-yN film.Type: GrantFiled: January 31, 2002Date of Patent: September 7, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kaoru Inoue, Yoshito Ikeda, Hiroyuki Masato
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Publication number: 20040169194Abstract: A semiconductor device comprises: a GaAs substrate; a buffer layer provided on the GaAs substrate; a laminated structure provided on the buffer layer; a Schottky contact layer provided on the laminated structure; a n-type Inx(Ga1−yAly)1−xP layer provided on the Schottky contact layer; a n-type Inu2Ga1−u2As ohmic contact layer provided on the n-type Inx(Ga1−yAly)1−P layer; a gate electrode provided on the Schottky contact layer; and a source electrode and a drain electrode provided on the ohmic contact layer. The buffer layer is made of a semiconductor, and at least a part of the semiconductor has a lattice constant larger than a lattice constant of GaAs. The channel layer is made of Inu1Ga1−u1As, and the electron supply layer is made of n-type Inv1Al1−v1As. At least a part of the Schottky contact layer is made of non-doped Inv2Al1−v2As.Type: ApplicationFiled: December 18, 2003Publication date: September 2, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Takao Noda
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Publication number: 20040155261Abstract: A semiconductor device and its manufacturing method. The semiconductor device has a semi-insulating GaAs substrate 310, a GaAs buffer layer 321 that is formed on the semi-insulating GaAs substrate 310, AlGaAs buffer layer 322, a channel layer 323, a spacer layer 324. a carrier supply layer 325, a spacer layer 326, a Schottky layer 327 that is composed of an undope In0.48Ga0.52P, an n+-type GaAs cap layer 328, a gate electrode 330 that is formed on the Schottky layer 327, is composed of LaB6 and has a Schottky contact with the Schottky layer 327 and ohmic electrodes 340 that are formed on the n+-type GaAs cap layer 328.Type: ApplicationFiled: July 14, 2003Publication date: August 12, 2004Inventors: Yoshiharu Anda, Akiyoshi Tamura
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Publication number: 20040155260Abstract: The present invention is directed to high frequency, high power or low noise devices such as low noise amplifiers, amplifiers operating at frequencies in the range of 1 GHz up to 400 GHz, radars, portable phones, satellite broadcasting or communication systems, or other devices and systems that use high electron mobility transistors, also called hetero-structure field-effect transistors. A high electron mobility transistor (HEMT) includes a substrate, a quantum well structure and electrodes. The high electron mobility transistor has a polarization-induced charge of high density. Preferably, the quantum well structure includes an AlN buffer layer, an un-doped GaN layer, and an un-doped InAlN layer.Type: ApplicationFiled: February 5, 2004Publication date: August 12, 2004Inventor: Jan Kuzmik
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Patent number: 6770902Abstract: An extracting transistor (10)—an FET—includes a conducting channel extending via a p-type InSb quantum well (22) between p-type InAlSb layers (20, 24) of wider band-gap. One of the InAlSb layers (24) incorporates an ultra-thin n-type &dgr;-doping layer (28) of Si, which provides a dominant source of charge carriers for the quantum well (22). It bears n+ source and drain electrodes (30a, 30b) and an insulated gate (30c). The other InAlSb layer (20) adjoins a barrier layer (19) of still wider band-gap upon a substrate layer (14) and substrate (16) with electrode (18). Biasing one or both of the source and drain electrodes (30a, 30b) positive relative to the substrate electrode (18) produces minority carrier extraction in the quantum well (22) reducing its intrinsic contribution to conductivity, taking it into an extrinsic saturated regime and reducing leakage current.Type: GrantFiled: October 29, 2002Date of Patent: August 3, 2004Assignee: QinetiQ LimitedInventor: Timothy J Phillips
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Publication number: 20040129949Abstract: A method for forming a hybrid active electronic and optical circuit using a lithography mask. The hybrid active electronic and optical circuit comprising an active electronic device and at least one optical device on a Silicon-On-Insulator (SOI) wafer. The SOI wafer including an insulator layer and an upper silicon layer. The upper silicon layer including at least one component of the active electronic device and at least one component of the optical device. The method comprising projecting the lithography mask onto the SOI waver in order to simultaneously pattern the component of the active electronic device and the component of the optical device on the SOI wafer.Type: ApplicationFiled: December 16, 2003Publication date: July 8, 2004Inventors: Shrenik Deliwala, Vipulkumar Patel
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Patent number: 6759696Abstract: The bipolar transistor comprises a collector region (1) of a semiconductor material having a first doping type, a base region (2) of a semiconductor material having a second doping type, and an emitter region (3) having the first doping type. A junction is present between the emitter region (3) and the base region (2), and, viewed from the junction (4), a depletion region (5) extends into the emitter region (3). The emitter region (3) comprises a layer (6) of a first semiconductor material and a layer (7) of a second semiconductor material. The first semiconductor material has a higher intrinsic carrier concentration than the second semiconductor material. The layer (7) of said second semiconductor material is positioned outside the depletion region (5). The second semiconductor material has such a doping concentration that Auger recombination occurs. The invention also relates to a semiconductor device comprising such a bipolar transistor.Type: GrantFiled: August 1, 2002Date of Patent: July 6, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Hendrik Gezienus Albert Huizing, Jan Willem Slotboom, Doede Terpstra, Johan Hendrik Klootwijk, Eyup Aksen
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Patent number: 6724019Abstract: A semiconductor device having an MODFET and at least one other device formed on one identical semiconductor substrate, in which an intrinsic region for the MODFET is formed by selective growth in a groove formed on a semiconductor substrate having an insulation film on the side wall of the groove, and single-crystal silicon at the bottom of the groove, is disclosed. The step between the MODFET and the at least one other device mounted together on one identical substrate can be thereby decreased, and each of the devices can be reduced in the size and integrated to a high degree, and the interconnection length can be shortened to reduce power consumption.Type: GrantFiled: April 3, 2001Date of Patent: April 20, 2004Assignee: Renesas Technology CorporationInventors: Katsuya Oda, Katsuyoshi Washio
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Patent number: 6713779Abstract: An object of the invention is to provide a complete depletion-mode SOI field-effect transistor in which transistors having different threshold voltages are integrated. A SiGe film having a high Ge composition and a SiGe film having a low Ge composition are formed on an insulating film, and strain-Si films are respectively formed thereon. Transistors including channel regions in the strain-Si films obtained as a result of this are formed, so that the transistors having different threshold voltages can be integrated.Type: GrantFiled: December 28, 2001Date of Patent: March 30, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Tsutomu Tezuka, Shinichi Takagi
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Patent number: 6661039Abstract: A hot-electron bolometric mixer/detector, which uses the nonlinearities of the heated two-dimensional electron gas medium, is described. Electrons in the illustrative embodiment of the present invention are “velocity-cooled” rather than “diffusion-cooled” or “phonon-cooled” like hot-electron bolometric mixer/detectors in the prior art. The illustrative embodiment is velocity-cooled when the elastic mean-free path of the electrons is greater than the channel length, L, of the mixer/detector. In this case, the motion of the hot electrons is more accurately modeled by their speed rather than in accordance with diffusion models. This leads to a mixer/detector with a wider modulation bandwidth at a lower power than is exhibited by mixer/detectors in the prior art.Type: GrantFiled: May 18, 2001Date of Patent: December 9, 2003Assignee: Lucent Technologies Inc.Inventors: Mark Lee, Loren Neil Pfeiffer, Kenneth William West
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Patent number: 6653668Abstract: It is an object of the present invention to provide a radio frequency module incorporating an MMIC that has a high S/N ratio while ensuring a high output. A radio frequency module according to the present invention incorporates an MMIC having a field effect transistor in which channel layers for traveling of carriers are formed by a heterostructure of two or more different kinds of materials, and height of a potential barrier of an interface between the different kinds of materials is less than 0.22 eV.Type: GrantFiled: August 30, 2002Date of Patent: November 25, 2003Assignee: Hitachi, Ltd.Inventors: Katsuhiko Higuchi, Shinichiro Takatani
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Patent number: 6642552Abstract: A device includes an element (e.g. in the shape of a sleeve) and a core located in an interior volume defined by the element and at least partially surrounded by the element. The element has two portions: one portion overlaps at least a region of the core thereby to form a capacitor, while another portion surrounds the core thereby to form an inductor. The device may further include an additional capacitor formed by another element that is separated from the core but overlaps at least a region of the core when viewed in a direction perpendicular to the core. The two elements substantially surround the core. The core may be used to hold charge in a non-volatile manner, even when no power is supplied to the device.Type: GrantFiled: February 2, 2001Date of Patent: November 4, 2003Assignee: Grail SemiconductorInventor: Donald S. Stern
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Patent number: 6627914Abstract: An MR/FIR light detector is disclosed herein that has extraordinarily high degree of sensitivity and a high speed of response. The detector includes an MR/FIR light introducing section (1) for guiding an incident MR/FIR light (2), a semiconductor substrate (14) formed with a single-electron transistor (14) for controlling electric current passing through a semiconductor quantum dot (12) formed therein, and a BOTAI antenna (6, 6a, 6b, 6c) for concentrating the MW/FIR light (2) into a small special zone of sub-micron size occupied by the semiconductor quantum dot (12) in the single-electron transistor (14). The quantum dot (12) forming a two-dimensional electron system absorbs the electromagnetic wave concentrated efficiently, and retains an excitation state created therein for 10 nanoseconds or more, thus permitting electrons of as many as one millions in number or more to be transferred with respect to a single photon absorbed.Type: GrantFiled: February 26, 2001Date of Patent: September 30, 2003Assignee: Japan Science and Technology CorporationInventors: Susumu Komiyama, Astafiev Oleg, Antonov Vladimir, Hiroshi Hirai, Takeshi Kutsuwa
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Publication number: 20030178639Abstract: A device includes an element (e.g. in the shape of a sleeve) and a core located in an interior volume defined by the element and at least partially surrounded by the element. The element has two portions: one portion overlaps at least a region of the core thereby to form a capacitor, while another portion surrounds the core thereby to form an inductor. The device may further include an additional capacitor formed by another element that is separated from the core but overlaps at least a region of the core when viewed in a direction perpendicular to the core. The two elements substantially surround the core. The core may be used to hold charge in a non-volatile manner, even when no power is supplied to the device.Type: ApplicationFiled: April 14, 2003Publication date: September 25, 2003Inventor: Donald S. Stern
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Patent number: 6605831Abstract: A field-effect semiconductor device includes a channel layer; a barrier structure formed on the channel layer and including a plurality of semiconductor layers; a plurality of ohmic electrodes formed above the barrier structure; and a Schottky electrode formed on the barrier structure between the ohmic electrodes. The barrier structure has an electron-affinity less than that of the channel layer and includes at least two heavily doped layers and a lightly doped layer provided therebetween.Type: GrantFiled: September 11, 2000Date of Patent: August 12, 2003Assignee: Murata Manufacturing Co., Ltd.Inventors: Makoto Inai, Hidehiko Sasaki
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Patent number: 6586781Abstract: New Group III nitride based field effect transistors and high electron mobility transistors are disclosed that provide enhanced high frequency response characteristics. The preferred transistors are made from GaN/AlGaN and have a dielectric layer on the surface of their conductive channels. The dielectric layer has a high percentage of donor electrons that neutralize traps in the conductive channel such that the traps cannot slow the high frequency response of the transistors. A new method of manufacturing the transistors is also disclosed, with the new method using sputtering to deposit the dielectric layer.Type: GrantFiled: January 29, 2001Date of Patent: July 1, 2003Assignees: Cree Lighting Company, The Regents of the University of CaliforniaInventors: Yifeng Wu, Naiqing Zhang, Jian Xu, Lee Mc Carthy
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Patent number: 6570194Abstract: The present invention provides a structure of a semiconductor device, the structure comprising: a compound semiconductor multi-layer structure having at least a channel region; and at least an ohmic contact layer provided adjacent to a first side face of the multi-layer structure, and the ohmic contact layer being in contact with at least a part of the first side face, wherein the ohmic contact layer has a top extending portion which extends in contact with a part of a top surface of the multi-layer structure.Type: GrantFiled: February 27, 2001Date of Patent: May 27, 2003Assignee: NEC CorporationInventors: Takehiko Kato, Naotaka Iwata
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Publication number: 20030080332Abstract: An extracting transistor (10)—an FET—includes a conducting channel extending via a p-type InSb quantum well (22) between p-type InAlSb layers (20, 24) of wider band-gap. One of the InAlSb layers (24) incorporates an ultra-thin n-type &dgr;-doping layer (28) of Si, which provides a dominant source of charge carriers for the quantum well (22). It bears n+ source and drain electrodes (30a, 30b) and an insulated gate (30c). The other InAlSb layer (20) adjoins a barrier layer (19) of still wider band-gap upon a substrate layer (14) and substrate (16) with electrode (18). Biasing one or both of the source and drain electrodes (30a, 30b) positive relative to the substrate electrode (18) produces minority carrier extraction in the quantum well (22) reducing its intrinsic contribution to conductivity, taking it into an extrinsic saturated regime and reducing leakage current.Type: ApplicationFiled: October 29, 2002Publication date: May 1, 2003Inventor: Timothy J Phillips
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Patent number: 6552373Abstract: A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.Type: GrantFiled: March 28, 2001Date of Patent: April 22, 2003Assignee: NEC CorporationInventors: Yuji Ando, Hironobu Miyamoto, Naotaka Iwata, Koji Matsunaga, Masaaki Kuzuhara, Kensuke Kasahara, Kazuaki Kunihiro, Yuji Takahashi, Tatsuo Nakayama, Nobuyuki Hayama, Yasuo Ohno