Abstract: A semiconductor device having a lateral diode includes a semiconductor layer, a first semiconductor region in the semiconductor layer, a contact region having an impurity concentration greater than that of the first semiconductor region, a second semiconductor region located in the semiconductor layer and separated from the contact region, a first electrode electrically connected through the contact region to the first semiconductor region, and a second electrode electrically connected to the second semiconductor region. The second semiconductor region includes a low impurity concentration portion, a high impurity concentration portion, and an extension portion. The second electrode forms an ohmic contact with the high impurity concentration portion. The extension portion has an impurity concentration greater than that of the low impurity concentration portion and extends in a thickness direction of the semiconductor layer.

Abstract: A light emitting diode package includes an electrically insulated base, first and second electrodes, an LED chip, a voltage stabilizing module, and an encapsulative layer. The base has a first surface and an opposite second surface. The first and second electrodes are formed on the first surface of the base. The LED chip is electrically connected to the first and second electrodes. The voltage stabilizing module is formed on the first surface of the base, positioned between and electrically connected to the first and second electrodes. The voltage stabilizing module connects to the LED chip in reverse parallel and has a polarity arranged opposite to that of the LED chip. The voltage stabilizing module has an annular shape and encircles the first electrode. The encapsulative layer is formed on the base and covers the LED chip.

Abstract: Provided is a semiconductor device in which on-resistance is largely reduced. In a region (2a) of an N type epitaxial layer (2) of the semiconductor device 20, each region between neighboring trenches (3) is blocked with a depletion layer (14) formed around a trench (3) so that a current passage (12) is interrupted, while a part of the depletion layer (14) formed around the trench (3) is deleted so that the current passage (12) is opened. In a region (2b), a junction portion (8) between the N type epitaxial layer (2) and a P+ type diffusion region (7) makes a Zener diode (8).

Abstract: Provided is an electrostatic discharge (ESD) protection diode that is formed on an input/output pad of an integrated circuit (IC), the ESD protection diode including: an N-type semiconductor that constitutes a first diode and is connected to a pad for a power supply voltage; a P-type semiconductor that constitutes the first diode and is connected to a signal line; an N-type semiconductor that constitutes a second diode and is connected to the signal line; a P-type semiconductor that constitutes the second diode and is connected to a pad for grounding; and a third diode that is formed by contacting the N-type semiconductor of the first diode and the P-type semiconductor of the second diode.

Abstract: A diode is defined on a die. The diode includes a substrate of P conductivity having an upper surface and a lower surface, the substrate having first and second ends corresponding to first and second edges of the die. An anode contacts the lower surface of the substrate. A layer of N conductivity is provided on the upper surface of the substrate, the layer having an upper surface and a lower surface. A doped region of N conductivity is formed at an upper portion of the layer. A cathode contacts the doped region. A passivation layer is provided on the upper surface of the layer and proximate to the cathode.

Abstract: The present disclosure provides a semiconductor device which includes a semiconductor substrate, a first gate structure disposed over the substrate, the first gate structure including a first gate electrode of a first conductivity type, a second gate structure disposed over the substrate and proximate the first gate structure, the second gate structure including a second gate electrode of a second conductivity type different from the first conductivity type, a first doped region of the first conductivity type disposed in the substrate, the first doped region including a first lightly doped region aligned with a side of the first gate structure, and a second doped region of the second conductivity type disposed in the substrate, the second doped region including a second lightly doped region aligned with a side of the second gate structure.

Abstract: A semiconductor light emitting device (10) comprises a semiconductor structure (12) comprising a first body (14) of a first semiconductor material (in this case Ge) comprising a first region of a first doping kind (in this case n) and a second body (18) of a second semiconductor material (in this case Si) comprising a first region of a second doping kind (in this case p). The structure comprises a junction region (15) comprising a first heterojunction (16) formed between the first body (14) and the second body (18) and a pn junction (17) formed between regions of the structure of the first and second doping kinds respectively. A biasing arrangement (20) is connected to the structure for, in use, reverse biasing the pn junction, thereby to cause emission of light.

Abstract: A semiconductor device includes a semiconductor substrate made of silicon carbide and having a surface, a normal vector for the surface having an off angle with respect to a <0001> direction or a <000-1> direction, a semiconductor layer of a first conductivity type formed on the semiconductor substrate, a first semiconductor region of a second conductivity type formed in a surface region of the semiconductor layer, a source region of a first conductivity type formed in a surface region of the first semiconductor region, a second semiconductor region of a second conductivity type formed in the surface region of the semiconductor layer, contacting the first semiconductor region, and having a bottom surface lower than a bottom surface of the first semiconductor region, wherein at least one end of the bottom surface of the second semiconductor region is perpendicular to an off angle direction.

Abstract: Disclosed herein are a nitride-based semiconductor device and a method for manufacturing the same. The nitride-based semiconductor device includes: a base substrate having a front surface and a rear surface opposite to the front surface; an epitaxial growth film formed on the front surface of the base substrate; a semiconductor layer formed on the rear surface of the base substrate; and an electrode structure body provided on the epitaxial growth film.

Abstract: A method for producing a photosensitive integrated circuit including producing circuit control transistors, producing, above the control transistors, and between at least one upper electrode and at least one lower electrode, at least one photodiode, by amorphous silicon layers into which photons from incident electromagnetic radiation are absorbed, producing at least one passivation layer, between the lower electrode and the control transistors, and producing, between the control transistors and the external surface of the integrated circuit, a reflective layer capable of reflecting photons not absorbed by the amorphous silicon layers.

Abstract: Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.

Abstract: A photodetector with internal gain comprising a semiconductor structure in which impact ionization events are produced mostly by minority charge carriers; a first biasing contact and a second biasing contact located in the semiconductor structure; a means of defining, in the semiconductor structure, a photon collection region close to first biasing contact; a P-N type junction formed in the semiconductor structure between the two biasing contacts and close to the second biasing contact; and a collector contact which is located in the P-N junction and used to collect current in the P-N junction.

Abstract: This invention discloses configurations and methods to manufacture lateral power device including a super-junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance.

Abstract: A food quality examination device using a high-sensitivity light-receiving element. The light-receiving element includes a III-V compound semiconductor stacked structure including an absorption layer having a pn-junction therein, wherein the absorption layer has a multiquanturn well structure composed of group III-V compound semiconductors, the pn-junction is formed by selectively diffusing an impurity element into the absorption layer, a diffusion concentration distribution control layer composed of III-V group semiconductor is disposed in contact with the absorption layer on a side of the absorption layer opposite the side adjacent to the group III-V compound semiconductor substrate, the bandgap energy of the diffusion concentration distribution control layer is smaller than that of the group III-V semiconductor substrate, the concentration of the impurity element selectively diffused in the diffusion concentration distribution control layer is decreased to be 5×1016/cm3 or less toward the absorption layer.

Abstract: Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2 DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2 DEG, forming an ohmic contact with the layer containing the 2 DEG.

Abstract: Avalanche photodiodes and methods for forming them are disclosed. The breakdown voltage of an avalanche photodiode is controlled through the inclusion of a diffusion sink that is formed at the same time as the device region of the photodiode. The device region and diffusion sink are formed by diffusing a dopant into a semiconductor to form a p-n junction in the device region. The dopant is diffused through a first diffusion window to form the device region and a second diffusion window to form the diffusion sink. The depth of the p-n junction is based on an attribute of the second diffusion window.

Abstract: A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant than the buffer layer.

Abstract: A field-effect transistor (FET) in which a gate electrode is located between a source electrode formed on one side of the gate electrode and a drain electrode formed on the other side, a source ohmic contact is formed under the source electrode and a drain ohmic contact is formed under the drain electrode. In the FET, the rise in the channel temperature is suppressed, the parasitic capacitance with a substrate is decreased, and the temperature dependence of drain efficiency is reduced, so that highly efficient operation can be achieved at high temperatures. The drain electrode is divided into a plurality of drain sub-electrodes spaced from each other and an insulating region is formed between the drain ohmic contacts formed under the drain sub-electrodes.

Abstract: Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.

Abstract: An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type and a higher doping level than the body, extending inside the body, and facing the surface laterally to the first cathode region and at a distance therefrom, and an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the first cathode region and the anode region. The insulation region is formed by a mirror region of metal material, a channel-stopper region having the second conductivity type, surrounding the mirror region, and a coating region, of dielectric material, arranged between the mirror region and the channel-stopper region.

Abstract: A complementary metal oxide semiconductor (CMOS) device that may include a substrate having a first active region and a second active region that are separated from one another by an isolation region. An n-type semiconductor device is present on the first active region that includes a first gate structure having a first gate dielectric layer and an n-type work function metal layer, wherein the n-type work function layer does not extend onto the isolation region. A p-type semiconductor device is present on the second active region that includes a second gate structure having a second gate dielectric layer and a p-type work function metal layer, wherein the p-type work function layer does not extend onto the isolation region. A connecting gate structure extends across the isolation region into direct contact with the first gate structure and the second gate structure.

Abstract: A system and method providing for the detection of an input signal, either optical or electrical, by using a single independent discrete amplifier or by distributing the input signal into independent signal components that are independently amplified. The input signal can either be the result of photoabsorption process in the wavelengths greater than 950 nm or a low-level electrical signal. The discrete amplifier is an avalanche amplifier operable in a non-gated mode while biased in or above the breakdown region, and includes a composite dielectric feedback layer monolithically integrated with input signal detection and amplification semiconductor layers.

Abstract: A light emitting device according to the embodiment includes a first electrode; a light emitting structure including a first semiconductor layer over the first electrode, an active layer over the first semiconductor layer, and a second semiconductor layer over the second semiconductor layer; a second electrode over the second semiconductor layer; and a connection member having one end making contact with the first semiconductor layer and the other end making contact with the second semiconductor layer to form a schottky contact with respect to one of the first and second semiconductor layers.

Abstract: A light emitting diode chip includes a device for protection against overvoltages, e.g., an ESD protection device. The ESD protection device is integrated into a carrier, on which the semiconductor layer sequence of the light emitting diode chip is situated, and is based on a specific doping of specific regions of said carrier. By way of example, the ESD protection device is embodied as a Zener diode that is connected to the semiconductor layer sequence by means of an electrical conductor structure.

Abstract: Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.

Abstract: A simulation of a multiplication process includes tracing histories of a plurality of carriers, increasing a weight factor of a carrier to simulate a multiplication of the carrier, and summing the number of the plurality of carriers. Each of the plurality of carriers is multiplied by its respective weight factor.

Abstract: A semiconductor device includes: a first semiconductor layer including AlXGa1-XN (0?X?1); a second semiconductor layer provided on the first semiconductor layer, including AlYGa1-YN (0?Y?1, X<Y), and having a larger bandgap than the first semiconductor layer; a source electrode provided on the second semiconductor layer; a drain electrode provided on the second semiconductor layer; and a gate electrode provided on the second semiconductor layer between the source electrode and the drain electrode. A region of the second semiconductor layer below the gate electrode at a depth short of the first semiconductor layer is doped with atoms to be negatively charged in the second semiconductor layer.

Abstract: Provided is a semiconductor device in which on-resistance is largely reduced. In a region (2a) of an N type epitaxial layer (2) of the semiconductor device 20, each region between neighboring trenches (3) is blocked with a depletion layer (14) formed around a trench (3) so that a current passage (12) is interrupted, while a part of the depletion layer (14) formed around the trench (3) is deleted so that the current passage (12) is opened. In a region (2b), a junction portion (8) between the N type epitaxial layer (2) and a P+ type diffusion region (7) makes a Zener diode (8).

Abstract: The present disclosure provides systems and methods for configuring and constructing a single photo detector or array of photo detectors with all fabrications circuitry on a single side of the device. Both the anode and the cathode contacts of the diode are placed on a single side, while a layer of laser treated semiconductor is placed on the opposite side for enhanced cost-effectiveness, photon detection, and fill factor.

Abstract: A Zener diode is fabricated on a semiconductor substrate having semiconductor material thereon. The Zener diode includes a first well region having a first conductivity type, formed in the semiconductor material. The Zener diode also includes a first region having a second conductivity type, formed in the first well region (the second conductivity type is opposite the first conductivity type). The Zener diode also includes a second region having the first conductivity type, wherein the second region is formed in the first well region and overlying the first region. An electrode is formed in the first region, and the electrode is electrically coupled to the second region.

Abstract: A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner.

Abstract: An element larger than silicon is ion-implanted to a contact liner in an N-channel region to break constituent atoms of the contact liner in the N-channel region. An element larger than silicon is ion-implanted to the contact liner in a P-channel region to break constituent atoms of the contact liner, oxygen or the like is ion-implanted. Thereafter, heat treatment is performed to cause shrinkage of the contact liner in the N-channel region to form an n-channel contact liner, and to cause expansion of the contact liner in the P-channel region to form a p-channel contact liner.

Abstract: A semiconductor device includes: a first semiconductor layer including AlXGa1-XN (0?X?1); a second semiconductor layer provided on the first semiconductor layer, including AlYGa1-YN (0?Y?1, X<Y), and having a larger bandgap than the first semiconductor layer; a source electrode provided on the second semiconductor layer; a drain electrode provided on the second semiconductor layer; and a gate electrode provided on the second semiconductor layer between the source electrode and the drain electrode. A region of the second semiconductor layer below the gate electrode at a depth short of the first semiconductor layer is doped with atoms to be negatively charged in the second semiconductor layer.

Abstract: Avalanche photodiodes and methods for forming them are disclosed. The breakdown voltage of an avalanche photodiode is controlled through the inclusion of a diffusion sink that is formed at the same time as the device region of the photodiode. The device region and diffusion sink are formed by diffusing a dopant into a semiconductor to form a p-n junction in the device region. The dopant is diffused through a first diffusion window to form the device region and a second diffusion window to form the diffusion sink. The depth of the p-n junction is based on an attribute of the second diffusion window.

Abstract: A method of fabricating a hetero-junction bipolar transistor (HBT) is disclosed, where the HBT has a structure incorporating a hetero-junction bipolar structure disposed on a substrate including of silicon crystalline orientation <110>. The hetero-junction bipolar structure may include an emitter, a base and a collector. The substrate may include a shallow-trench-isolation (STI) region and a deep trench region on which the collector is disposed. The substrate may include of a region of silicon crystalline orientation <100> in addition to silicon crystalline orientation <110> to form a composite substrate by using hybrid orientation technology (HOT). The region of crystalline orientation <100> may be disposed on crystalline orientation <110>. Alternatively, the region of silicon crystalline orientation <110> may be disposed on crystalline orientation <100>.

Abstract: In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.

Abstract: A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed.

Abstract: An avalanche photodiode with a nano-scale reach-through structure comprising n-doped and p-doped regions, formed on a silicon island on an insulator, so that the avalanche photodiode may be electrically isolated from other circuitry on other silicon islands on the same silicon chip as the avalanche photodiode. For some embodiments, multiplied holes generated by an avalanche reduces the electric field in the depletion region of the n-doped and p-doped regions to bring about self-quenching of the avalanche photodiode. Other embodiments are described and claimed.

Abstract: A single-photon detector is disclosed that provides reduced afterpulsing without some of the disadvantages for doing so in the prior art. An embodiment of the present invention provides a stimulus pulse to the active area of an avalanche photodetector to stimulate charges that are trapped in energy trap states to detrap. In some embodiments of the present invention, the stimulus pulse is a thermal pulse.

Abstract: A semiconductor device includes a semiconductor substrate, a photon avalanche detector in the semiconductor substrate. The photon avalanche detector includes an anode of a first conductivity type and a cathode of a second conductivity type. A guard ring is in the semiconductor substrate and at least partially surrounds the photon avalanche detector. A passivation layer of the first conductivity type is in contact with the guard ring to reduce an electric field at an edge of the photon avalanche detector.

Abstract: Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.

Abstract: A method of manufacture of an avalanche photodiode involving a step of making a recess in a top window layer of an avalanche photodiode layer stack, such that a wall surrounding the recess runs smoothly and gradually from the level of the recess to the level of the window layer. Further, diffusing a dopant over the entire window layer area so as to form a p-n junction at the bottom of the recess, and providing a first electrical isolation region around the recess by buried ion implantation or wet oxidation in order to limit the flow of electrical current to the p-n junction. Forming an isolation trench around the photodiode and a second electrical isolation region by ion implantation into the trench such that the second electrical isolation region runs through the absorption layer of the photodiode.

Abstract: A semiconductor apparatus includes, a first silicon layer of a first conductivity type; a second silicon layer provided on the first silicon layer and having a higher resistance than the first silicon layer, a third silicon layer of a second conductivity type provided on the second silicon layer, a first nitride semiconductor layer provided on the third silicon layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a larger bandgap than the first nitride semiconductor layer, a first main electrode being in contact with a surface of the second nitride semiconductor layer and connected to the third silicon layer, a second main electrode being in contact with the surface of the second nitride semiconductor layer and connected to the first silicon layer, and a control electrode provided between the first main electrode and the second main electrode on the second nitride semiconductor layer.

Abstract: A semiconductor optical receiver device is provided, which a mesa comprising a plurality of semiconductor crystal layers formed on a semiconductor substrate including a pn junction having a first conductive semiconductor crystal layer and a second conductive semiconductor crystal layer and including a first contact layer on the semiconductor substrate, a plurality of electrodes to apply electric field to the pn junction are coupled on the semiconductor substrate, a second contact layer is formed on a buried layer in which the mesa is buried, and the electric field is applied to the pn junction through the first and second contact layers.

Abstract: A transmitted light absorption/recombination layer, a barrier layer, a wavelength selection/absorption layer, and an InP window layer having a p-type region are supported by an n-type substrate and arranged in that order. Light with a wavelength of 1.3 ?m reaches the wavelength selection/absorption layer through the InP window layer. Then, the light is absorbed by the wavelength selection/absorption layer and drawn from the device as an electric current signal. Light with a wavelength of 1.55 ?m reaches the transmitted light absorption/recombination layer through the barrier layer. Then, the light is absorbed by the transmitted light absorption/recombination layer, generating electrons and holes. These electrons and holes recombine with each other and, hence, disappear.

Abstract: A semiconductor system is described, which is made up of a highly n-doped silicon substrate and a first n-silicon epitaxial layer, which is directly contiguous to the highly n-doped silicon substrate, and having a p-doped SiGe layer, which is contiguous to a second n-doped silicon epitaxial layer and forms a heterojunction diode, which is situated above the first n-doped silicon epitaxial layer and in which the pn-junction is situated within the p-doped SiGe layer. The first n-silicon epitaxial layer has a higher doping concentration than the second n-silicon epitaxial layer. Situated between the two n-doped epitaxial layers is at least one p-doped emitter trough, which forms a buried emitter, a pn-junction both to the first n-doped silicon epitaxial layer and also to the second n-doped silicon epitaxial layer being formed, and the at least one emitter trough being completely enclosed by the two epitaxial layers.

Abstract: As semiconductor regions in contact with a first main surface of a semiconductor base composed by forming an N? silicon carbide epitaxial layer on an N+ silicon carbide substrate connected to a cathode electrode, there are provided both of an N+ polycrystalline silicon layer of a same conduction type as a conduction type of the semiconductor base and a P+ polycrystalline silicon layer of a conduction type different from the conduction type of the semiconductor base. Both of the N+ polycrystalline silicon layer and the P+ polycrystalline silicon layer are hetero-joined to the semiconductor base, and are ohmically connected to the anode electrode.

Abstract: Impurity concentration of a second semiconductor region is set such that when a predetermined reverse bias is applied to a heterojunction diode configured by a first semiconductor region and the second semiconductor region, a breakdown voltage at least in a heterojunction region other than outer peripheral ends of the heterojunction diode is a breakdown voltage of a semiconductor device.

Abstract: Disclosed are a light emitting device having a zener diode therein and a method of fabricating the light emitting device. The light emitting device comprises a P-type silicon substrate having a zener diode region and a light emitting diode region. A first N-type compound semiconductor layer is contacted to the zener diode region of the P-type silicon substrate to exhibit characteristics of a zener diode together with the P-type silicon substrate. Further, a second N-type compound semiconductor layer is positioned on the light emitting diode region of the P-type silicon substrate. The second N-type compound semiconductor layer is spaced apart from the first N-type compound semiconductor layer. Meanwhile, a P-type compound semiconductor layer is positioned on the second N-type compound semiconductor layer, and an active layer is interposed between the second N-type compound semiconductor layer and the P-type compound semiconductor layer.

Abstract: A nitride-based semiconductor device includes a diode provided on a semiconductor substrate. The diode contains a first nitride-based semiconductor layer made of non-doped AlXGa1-XN (0?X<1); a second nitride-based semiconductor layer made of non-doped or n-type AlYGa1-YN (0<Y?1, X<Y) having a lattice constant smaller than that of the first nitride-based semiconductor layer; a first electrode formed on the second nitride-based semiconductor layer; a second electrode formed on the second nitride-based semiconductor layer; and an insulating film that covers the second nitride-based semiconductor layer below a peripheral portion of the first electrode. In the diode, a recess structure portion is formed at a position near the peripheral portion of the first electrode on the second nitride-based semiconductor layer, and the first electrode covers the second nitride-based semiconductor layer and at least a part of the insulating film.