Abstract: The plurality of electrical leads of the semiconductor device have a connection portion exposed to the outer periphery on the back surface of the seal section and a thickness reduced portion formed to be thinner than said connection portion. The connection portion is provided with an inner groove and an outer groove in a wire bonding surface as disposed within the seal section of the connection portion. Wires are provided for electrical connection between the leads and pads of the semiconductor chip. The thickness reduced portion of the leads is covered by or coated with a sealing resin material while causing the wires to be contacted with the connection portion at specified part lying midway between the outer groove and inner groove to permit the thickness reduced portion of leads and the outer groove plus the inner groove to prevent the occurrence of any accidental lead drop-down detachment.

Abstract: A surface mounted power supply circuit apparatus, including a circuit substrate, circuit constituting parts mounted on the circuit substrate, and a sealing member provided on the circuit substrate for covering the circuit constituting parts, at least one portion of the circuit constituting parts being configured to be contained in a containing portion formed in the circuit substrate.

Abstract: A circuit board includes a base material, a conductive pattern which is formed on the base material, and a resin layer which is formed on the conductive pattern by a photocurable resin.

Abstract: A memory device includes an executable flash memory partition and a non-executable partition, both partitions being fabricated on a common die. Preferably, both partitions are fabricated using the same flash memory technology. Most preferably, the flash cells of both partitions have insulating floating gates.

Abstract: Reducing a dark current in a semiconductor photodetector provided with a second mesa including an regrown layer around a first mesa. An n-type buffer layer, a n-type multiplication layer, a p-type field control layer, a p-type absorption layer, a cap layer made of p-type InAlAs crystal, and a p-type contact layer 107 are made to grow on a main surface of a n-type substrate. Thereafter the p-type contact layer, the p-type cap layer, the p-type absorption layer and the p-type field control layer are patterned to form a first mesa. Next, after making a p-type regrown layer selectively grow around the first mesa or by forming a groove in the regrow layer located in a vicinity of the p-type cap type during a step of the selective growth, the p-type cap layer containing Al and the regrow layer are separated owing to the groove such that no current path is formed between both layers.

Abstract: A sequential mesa type avalanche photodiode (APD) comprises a semiconductor substrate and a sequential mesa portion formed on the substrate. In the sequential mesa portion, a plurality of semiconductor layers, including a light absorbing layer and a multiplying layer, are laminated by epitaxial growth. In the plurality of semiconductor layers, a pair of semiconductor layers forming a pn junction is included. The carrier density of a semiconductor layer which is near to the substrate among the pair of semiconductor layers is larger than the carrier density of a semiconductor layer which is far from the substrate among the pair of semiconductor layers. In the APD, light-receiving current based on movement of electrons and positive holes generated in the sequential mesa portion when light is incident from the substrate toward the light absorbing layer is larger at a central portion than at a peripheral portion of the sequential mesa portion.

Abstract: The present invention is directed to a novel semiconductor device, which can be efficiently fabricated for use in Zener diode applications. Precision Zener diodes and the method for manufacturing the same are provided. The Zener diodes of the present invention are made from a semiconductor substrate layer having a range or resistivity, on which is grown an epitaxial layer. The epitaxial layer has a resistivity greater than that of the substrate. The diode also has an interior region of doped semiconductor material of the same conductivity type as the substrate. The interior region extends through the epitaxial layer and into the substrate layer. The diode also has a junction layer of a conductivity type different from the substrate. The junction layer is formed in the epitaxial surface, and the junction layer forms an interior P/N junction with the interior region and a peripheral P/N junction with a peripheral portion of the device.

Abstract: The present invention relates to an impact ionisation avalanche transit time (IMPATT) diode device comprising an avalanche region and a drift region, wherein at least one narrow bandgap region, with a bandgap narrower than the bandgap in the avalanche region, is located adjacent to or within the avalanche region in order to generate within the narrow bandgap region a tunnel current which is injected into the avalanche region. This improves the predictability with which a current can be injected into the avalanche region and enables a relatively narrow pulse of current to be injected into the avalanche region in order to enable a relatively noise free avalanche multiplication. The narrow bandgap region may be located between a heavily doped contact region and the avalanche region and is preferably arranged to generate a tunnel current at the peak reverse bias applied to the diode.

Abstract: The invention relates to technology improving the withstand voltage of a Schottky diode. With a diode of the present invention, the distance a between the long sides of the narrow groove withstand voltage portions and the inner ring circumference of the intermediate withstand voltage portion is set to twice the distance b between the short sides of the narrow groove withstand voltage portions and the inner ring circumference of the intermediate withstand voltage portion. Furthermore, the distance c between the inner ring circumference of the innermost outer withstand voltage portions and the outer ring circumference of the intermediate withstand voltage portion, the distance u between the adjacent outer withstand voltage portions, and the distance d between the adjacent narrow groove withstand voltage portions are all equal to the distance a.

Abstract: In one aspect the invention relates to a high bandwidth shallow mesa semiconductor photodiode responsive to incident electromagnetic radiation. The photodiode includes an absorption narrow bandgap layer, a wide bandgap layer disposed substantially adjacent to the absorption layer, a first doped layer having a first conductivity type disposed substantially adjacent to the wide bandgap layer, and a passivation region disposed substantially adjacent to the wide bandgap layer and the first doped layer.

Abstract: A method for improving the mobility of holes and electrons within a structure comprising the following steps. A structure having at least an adjacent NMOS device and PMOS device is provided. A first stress layer is formed over the PMOS device and a second stress layer is formed over the NMOS device whereby the mobility of holes and electrons within the structure is improved. A semiconductor device comprising: at least one NMOS device; at least one PMOS device adjacent the at least one NMOS device; a first stress layer overlying the at least one PMOS device with the first stress layer having a first stress characteristic; and a second stress layer overlying the at least one NMOS device with the second stress layer having a second stress characteristic.

Abstract: A blue-violet-near-ultraviolet pin-photodiode with small dark current, high reliability and long lifetime. The pin-photodiode has a metallic n-electrode, a n-ZnSe single crystal substrate, an optionally added n-ZnSe buffer layer, an n-Zn1-xMgxSySe1-y layer, an i-Zn1-xMgxSySe1-y layer, a p-Zn1-xMgxSySe1-y layer, a p-(ZnTe/ZnSe)m SLE, a p-ZnTe contact layer, an optionally provided antireflection film and a metallic p-electrode. A blue-violet-near-ultraviolet avalanche photodiode with small dark current, high reliability and long lifetime. The avalanche photodiode has a metallic n-electrode, a n-ZnSe single crystal substrate, an optionally added n-ZnSe buffer layer, an n-Zn1-xMgxSySe1-y layer, an i-Zn1-xMgxSySe1-y layer, a p-Zn1-xMgxSySe1-y layer, a p-(ZnTe/ZnSe)m SLE, a p-ZnTe contact layer, an optionally provided antireflection film and a metallic p-electrode. Upper sides of the layered structure are etched into a mesa-shape and coated with insulating films.

Abstract: An N−-type silicon substrate (1) has a bottom surface and an upper surface which are opposed to each other. In the bottom surface of the N−-type silicon substrate (1), a P-type impurity diffusion layer (3) of high concentration is entirely formed by diffusing a P-type impurity. In the upper surface of the N−-type silicon substrate (1), a P-type isolation region (2) is partially formed by diffusing a P-type impurity. The P-type isolation region (2) has a bottom surface reaching an upper surface of the P-type impurity diffusion layer (3). As viewed from the upper surface side of the N−-type silicon substrate (1), the P-type isolation region (2) is formed, surrounding an N− region (1a) which is part of the N−-type silicon substrate (1). The N− region (1a) surrounded by the P-type isolation region (2) is defined as an element formation region of the N−-type silicon substrate (1).

Abstract: A diode for use in an under-the-hood automotive application has a TO 220 outline and consists of a diode die on a two piece lead frame which has a thick section to which the bottom of the die is soldered, and a thinner section which extends through a plastic housing as a connection tab and which has a forked end for easy connection to a node of a three phase bridge. The bottom of the thickened section is exposed through the insulation housing for easy connection to a d-c heat sink rail. The diode is particularly useful in applications greater than 2 KW.

Abstract: The diode of the present invention includes: a cathode electrode and an anode electrode that are disposed on a semiconductor substrate and are spaced apart from each other; and a shielding metal member placed between the cathode and anode electrodes.

Abstract: A first signal path of a circuit 300 of the present invention is formed by connecting a restricted area 331 in the electrically disconnected state, restricted areas 321 and 311 in the electrically connected state in series, using conductors 330, 320, and 310, and contacts 351 and 352. The circuit 300 is constructed by connecting in parallel six signal paths each being divided by a combination of one or two restricted areas provided thereon. Every time the circuit state is switched, a signal path disconnectedby one restricted area is changed suitably to a signal path disconnected by two restricted areas, and vice versa, so as to maintain a signal path disconnected by a combination of restricted areas. By doing so, the switch of the circuit between the disconnected state and the connected state can be repeated an unlimited number of times by a change in one freely-chosen layer.

Abstract: A high reverse voltage diode includes a hetero junction made up from a silicon carbide base layer, which constitutes a first semiconductor base layer, and a polycrystalline silicon layer, which constitutes a second semiconductor layer, and whose band gap is different from that of the silicon carbide base layer. A low concentration N type polycrystalline silicon layer is deposited on a first main surface side of the silicon carbide base layer, and a metal electrode is formed on a second main surface side of the silicon carbide base layer which is opposite to the first main surface side thereof.

Abstract: A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other.

Abstract: The invention relates to the protection of devices in a monolithic chip fabricated from an epitaxial wafer, such as a wafer for a Group III-V compound semiconductor or a wafer for a Group IV compound semiconductor. Devices fabricated from Group III-V compound semiconductors offer higher speed and better isolation than comparable devices from silicon semiconductors. Semiconductor devices can be permanently damaged when exposed to an undesired voltage transient such as electrostatic discharge (ESD). However, conventional techniques developed for silicon devices are not compatible with processing techniques for Group III-V compound semiconductors, such as gallium arsenide (GaAs). Embodiments of the invention advantageously include transient voltage protection circuits that are relatively efficiently and reliably manufactured to protect sensitive devices from undesired voltage transients.

Abstract: A method of epitaxially growing backward diodes and diodes grown by the method are presented herein. More specifically, the invention utilizes epitaxial-growth techniques such as molecular beam epitaxy in order to produce a thin, highly doped layer at the p-n junction in order to steepen the voltage drop at the junction, and thereby increase the electric field. By tailoring the p and n doping levels as well as adjusting the thin, highly doped layer, backward diodes may be consistently produced and may be tailored in a relatively easy and controllable fashion for a variety of applications. The use of the thin, highly doped layer provided by the present invention is discussed particularly in the context of InGaAs backward diode structures, but may be tailored to many diode types.

Abstract: In accordance with the present invention, a metal oxide semiconductor (MOS) transistor has a substrate of a first conductivity type. A drift region of a second conductivity type is formed over the substrate. A body region of the first conductivity type is formed in the drift region. A source region of the second conductivity is formed in the body region. A gate extends over a surface portion of the body region and overlaps each of the source region and the body region such that the surface portion of the body region forms a channel region of the transistor. A drain region of the second conductivity type is formed in the drift region. The drain region is laterally spaced from the source region a first predetermined distance. A first buried layer of the first conductivity type extends into the substrate and the drift region. The first buried layer laterally extends between the source and drain regions.

Abstract: A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and then also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits.

Abstract: A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, thus providing more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and thus also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits.

Abstract: Each memory cell has a cell transistor and a ferroelectric capacitor connected in parallel between a source and drain terminals of this cell transistor. The ferroelectric capacitor has a bottom electrode and a top electrode and a contact connects the top electrode and one of a source and drain terminals of the cell transistor. This contact is arranged at the position offset from the interval of the bottom electrodes.

Abstract: A diode for use in an under-the-hood automotive application has a TO 220 outline and consists of a diode die on a two piece lead frame which has a thick section to which the bottom of the die is soldered, and a thinner section which extends through a plastic housing as a connection tab and which has a forked end for easy connection to a node of a three phase bridge. The bottom of the thickened section is exposed through the insulation housing for easy connection to a d-c heat sink rail. The diode is particularly useful in applications greater than 2 KW.

Abstract: A buried Zener diode structure and method of manufacture requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation. The buried Zener diode has its N++/P+ junction removed from the silicon surface.

Abstract: An emitter of a heterojunction bipolar transistor has a double-layer protrusion formed of a first emitter layer and a second emitter layer and protruded outside an external base region. The protrusion of 50 nm in total thickness is enough to prevent damage during formation of the protrusion by etching or during later fabricating processes. Penetration of moisture through damaged places is eliminated. A base ohmic electrode is continuously formed on the first and second emitter layers on the external base region up to the protrusion. Thus, the protrusion is reinforced so as to be further hard to damage. By ensuring a large area for the base ohmic electrode, an alignment margin can be taken during formation of a base lead electrode.

Abstract: In a semiconductor device, a first semiconductor layer is formed on a semiconductor substrate. A second semiconductor layer is formed on a part of the first semiconductor layer, and a third semiconductor layer is formed on a part of the second semiconductor layer. A first electrode is formed on the third semiconductor layer, and a second electrode is formed on the first semiconductor layer in contact with the second semiconductor layer and apart from the semiconductor layer, thus forming a diode.

Abstract: This patent is generally directed towards a method and device for providing a diode structure that has a barrier height that may be readily engineered with a series resistance that may be independently varied while simultaneously providing for the complete characterization and discernment of the barrier height in a microwave and millimeter-wave rectifying diode without the need for device fabrication and electrical measurement. The present invention generally relates to microwave and millimeterwave diodes, and more particularly to low barrier structures within these diodes that are capable of rectification of microwave and millimeterwave radiation.

Abstract: Edges of a slit and cut to length foil having a dielectric oxide film on at least one surface are edge formed by comprising anodizing the foil in an aqueous oxalic acid electrolyte, further edge a forming the foil in an aqueous citrate electrolyte, preferably dibasic ammonium citrate electrolyte, depolarizing the foil, and then edge forming the foil in an aqueous phosphate electrolyte, preferably an ammonium dihydrogen phosphate.

Abstract: A Microwave/Millimeter-wave Monolithic Integrated Circuit (MMIC) device including PIN diode and Schottky diode circuits that provides improved performance with a reduced cost of manufacture. The planar, glass-passivated, MMIC device is fabricated in silicon technology and includes mesa isolation between the PIN diode and the Schottky diode. The PIN and Schottky diodes include respective anode regions having different thicknesses and resistivity for implementing the PIN and Schottky diode functions. Further, the Schottky anode region is formed relatively late in a process for fabricating the Si MMIC device to allow the Schottky anode region to be formed in approximately the same plane as the PIN anode region and to allow precise control of the relative thicknesses of the PIN and Schottky anode regions.

Abstract: A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and then also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits.

Abstract: A method of forming a lateral bipolar transistor without added mask in CMOS flow including a p-substrate; patterning and n-well implants; pattern and implant pocket implants for core nMOS and MOS; pattern and implants pocket implants I/O nMOS and pMOS; sidewall deposit and etch and then source/drain pattern and implant for nMOS and pMOS. The method includes the steps of forming emitter and collector contacts by implants used in source/drain regions; forming an emitter that includes implants done in core pMOS during core pMOS LDD extender and pocket implant steps and while the collector omits the core pMOS LDD extender and pocket implants; forming a base region below the emitter and collector contacts by the n-well region with said base region going laterally from emitter to collector being the n-well and including pocket implants; and forming base contact by said n-well region and by implants used in nMOS source/drain regions.

Abstract: A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and then also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits.

Abstract: A semiconductor light-emitting unit includes: a semiconductor laser diode; a photodetector functioning as a sub-mount for mounting the diode thereon; and a heating member, incorporated with the photodetector, for heating the diode. If the ambient temperature of the diode falls within a range where kinks are possibly caused in the low-temperature I-L characteristic of the diode, then current is supplied to the heating member, thereby heating the diode. The heating member may be either a doped region defined within a semiconductor substrate or a doped polysilicon film formed on the substrate. Also, the heating member is preferably located under the laser diode with a heat-dissipating layer and an insulating layer interposed therebetween. The semiconductor light-emitting unit with this structure can effectively eliminate kinks from the low-temperature I-L characteristic of the semiconductor laser diode.

Abstract: In a semiconductor device, a first semiconductor layer is formed on a semiconductor substrate. A second semiconductor layer is formed on a part of the first semiconductor layer, and a third semiconductor layer is formed on a part of the second semiconductor layer. A first electrode is formed on the third semiconductor layer, and a second electrode is formed on the first semiconductor layer in contact with the second semiconductor layer and apart from the semiconductor layer, thus forming a diode.

Abstract: A semiconductor device comprises a semiconductor body (10) in and on which a power transistor (T; 1, 2, 3) and a suppression diode (D; 100) are integrated. A diode junction (40; 40′) is present between the back metallization (22) and the adjacent region (2) of the power transistor so as to provide the diode in series with this region (2) and adjacent to the back surface (12) of the body. This diode junction (40; 40′) opposes the p-n junction (42) between the collector or drain region (2) of the transistor and its base region (3), so as to suppress reverse current flow in the transistor. The higher doped part (2b) of the adjacent transistor region (2) is sufficiently thick as to prevent any minority charge carriers injected by the diode junction (40; 40′) from reaching the p-n junction (42) with the base region (3). The diode junction may be a p-n junction (40) or a Schottky barrier (40′).

Abstract: A power semiconductor device of the present invention comprises a voltage drive type power MOS transistor, a series connection of a first resistor and Zener diode, a second resistor, and a series connection of a third resistor and MOS transistor. The power MOS transistor has a gate, source and drain. A drain-to-source voltage of the power MOS transistor is applied across the series connection of the first resistor and Zener diode. A gate-to-source voltage of the power MOS transistor is applied across the second resistor. The gate-to-source voltage of the power MOS transistor is applied across a series connection of a third resistor and the MOS transistor. The MOS transistor has a gate, source and drain. The gate of the MOS transistor is connected to a node between the first resistor and the Zener diode.

Abstract: An insulator film provided on a region for arranging a Zener diode has a plurality of groove portions successively arranged in a direction D1 of extension of each semiconductor region forming the diode. Each groove potion extends in a width direction D2 of each semiconductor region, and has a depth T3. Each semiconductor region is arranged on the upper surface of the insulator film. Therefore, it follows that each semiconductor region has a plurality of irregular shapes arranged in the direction D1 of extension and the Zener diode has a peripheral length not only in the transverse direction D1 but also in a vertical direction D3, so that a p-n junction area in the Zener diode is increased. Thus, parasitic resistance of an input protection Zener diode is reduced for improving a gate insulator film protective function of the diode.

Abstract: A method of manufacturing a metal-oxide-semiconductor field effect (MOSFET) device. A substrate having an isolating structure thereon is provided. A gate dielectric layer and a conductive layer are sequentially formed over the substrate. The conductive layer and the gate dielectric layer are patterned to form a gate structure. A low dielectric constant material spacer is formed on the sidewall of the gate structure. A source drain region is formed in the substrate on each side of the gate structure.

Abstract: An array of photodiodes in series on a common semi-insulating substrate has a non-conductive buffer layer between the photodiodes and the semi-insulating substrate. The buffer layer reduces current injection leakage between the photodiodes of the array and allows optical energy to be converted to high voltage electrical energy.

Abstract: A tunnel diode has a quantum well having at least one layer of semiconductor material. The tunnel diode also has a pair of injection layers on either side of the quantum well. The injection layers comprise a collector layer and an emitter layer. A barrier layer is positioned between each of the injection layers and the quantum well. The quantum well has an epitaxial relationship with the emitter layer. An amount of one element of the well layer is increased to increase the lattice constant a predetermined amount. The lattice constant may have a reduction in the conduction band energy. A second element is added to the well layer to increase the conduction band energy but not to change the lattice constant. By controlling the composition in this matter, the negative resistance, and thus the effective mass, may be controlled for various diode constructions.

Abstract: A semiconductor device with a tunnel diode comprises two mutually adjoining semiconductor regions (2, 3) of opposed conductivity types having high enough doping concentrations to provide a tunneling junction. Portions (2A, 3A) of the semiconductor regions adjoining the junction comprise a mixed crystal of silicon and germanium. The doping concentration of both phosphorus and boron are substantially increased, given the same amount of dopants being offered as during the formation of the remainder of the regions. The tunneling efficiency is substantially improved, and also because of the reduced bandgap of said portions (2A, 3A). A much steeper current-voltage characteristic both in the forward and in the reverse direction is achieved. Thus, the tunneling pn junction can be used as a transition between two conventional diodes which are stacked one on the other and formed in a single epitaxial growing process. The doping concentration may be 6×1019 or even more than 1020 at/cm3.

Abstract: A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and then also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/ electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits.

Abstract: The invention is a semiconductor avalanche photodetector including an essentially undoped multiplication layer; a thin, undoped light absorbing layer; and a doped waveguide layer which is separate from the light absorbing layer and is capable of coupling incident light into the light absorbing layer.

Abstract: An MSM semiconductor circuit formed on a semi-insulating substrate that includes a set of contacts, first and second absorption layers, and a wide band gap buffer layer. The first absorption layer is formed on the semi-insulating substrate. The second absorption layer operably coupled to the set of contacts. The wide band gap buffer layer disposed between the first absorption layer and the second absorption layer.

Abstract: An insulator film provided on a region for arranging a Zener diode has a plurality of groove portions successively arranged in a direction D1 of extension of each semiconductor region forming the diode. Each groove potion extends in a width direction D2 of each semiconductor region, and has a depth T3. Each semiconductor region is arranged on the upper surface of the insulator film. Therefore, it follows that each semiconductor region has a plurality of irregular shapes arranged in the direction D1 of extension and the Zener diode has a peripheral length not only in the transverse direction D1 but also in a vertical direction D3, so that a p-n junction area in the Zener diode is increased. Thus, parasitic resistance of an input protection Zener diode is reduced for improving a gate insulator film protective function of the diode.

Abstract: Methods of laying out avalanche light emitting diodes (LEDs) are described in which a heavily impurity doped region of one type of polarity, a second, lighter doped region of like polarity, and a heavy doped region of opposite type polarity are disposed in a silicon substrate. Electrodes are laid out such that light emitted by the avalanching PN junction is not blocked. Construction features include shallow implants to improve efficiency and implants which avoid the silicon-oxide interface for stability and implants which avoid junction corners to avoid concentrating injection. Construction of vertical and side emitting junctions are disclosed. Also disclosed are construction details of side emitting SOI junctions which are useful in SOI based opto couplers.

Abstract: A heterojunction bipolar transistor having reduced parasitic emitter resistance. The bipolar transistor comprises a semi-insulating substrate, a collector contact layer formed on the semi-insulating substrate, a collector layer formed on the collector contact layer, a base layer formed on the collector layer, an emitter layer formed on the base layer, a composition graded layer formed on the emitter layer, and an emitter contact layer formed on the composition graded layer. A forbidden band width of the emitter layer is wider than that of the base layer. A forbidden band width of the emitter contact layer is narrower than that of the emitter layer and impurity concentration of the emitter contact layer is higher than that of the emitter layer.

Abstract: A gas sensor having a pn junction including two discrete electrical conductive-type layers, namely, a first semiconductor layer and a second semiconductor layer, disposed in contact with each other. Ohmic electrodes are formed on the respective surfaces of the semiconductor layers. A catalytic layer containing a metallic catalytic component which dissociates hydrogen atom from a molecule having hydrogen atom is formed on one of the ohmic electrodes. The pn junction diode-type gas sensor has a simple constitution, exhibits a small change in diode characteristics with time in long-term service and is capable of detecting a gas concentration of a molecule having a hydrogen atom, for example, H2, NH3, H2S, a hydrocarbon and the like, contained in a sample gas.