Abstract: A high-frequency diode has a first semiconductor area with a first conductivity type as well as a barrier area adjacent to the first semiconductor area, which has a second conductivity type, which differs from the first conductivity type. Further, the high-frequency diode has a second semiconductor area adjacent to the barrier area, which has the second conductivity type and a dopant concentration which is lower than the dopant concentration of the barrier are or equal to zero. Further, the high-frequency diode has a third semiconductor area adjacent to the second semiconductor area, which has the same conductivity type and a higher dopant concentration than the barrier area. Through such a structure it is possible to provide a high-frequency diode with short switching times and low bias.

Abstract: An electrostatic discharge device includes a first protection element including a MOS transistor type first diode, which provides a first capacitor including a first insulation layer, and provides a first path between an input/output pad and a power supply voltage line using the first diode, for discharging static electricity, a second protection element providing a second path between the input/output pad and a ground voltage line for discharging the static electricity, a trigger circuit including a resistor that is connected in series to the first capacitor, and a power clamp element providing a third path for discharging the static electricity between the power supply voltage line and the ground voltage line by a voltage applied to the resistor.

Abstract: A single-photon avalanche detector is disclosed that is operable at wavelengths greater than 1000 nm and at operating speeds greater than 10 MHz. The single-photon avalanche detector comprises a thin-film resistor and avalanche photodiode that are monolithically integrated such that little or no additional capacitance is associated with the addition of the resistor.

Abstract: An integrated circuit includes a first and second diode connected in parallel. The first diode has a first breakdown voltage and has first P type region and first N type region adjacent to each other at the surface of the substrate of a substrate to form a lateral diode. The second diode has a second breakdown voltage less than the first breakdown voltage and has a second P type region and second N type region lateral adjacent to each other in the substrate to form a lateral diode below the surface The first and second N type regions overlap and the first and second P type region being electrically connected whereby the first and second diodes are in parallel.

Abstract: A device, and method for manufacturing the same, including a PFET having an embedded SiGe layer where a shallow portion of the SiGe layer is closer to the PFET channel and a deep portion of the SiGe layer is further from the PFET channel. Thus, the SiGe layer has a boundary on the side facing toward the channel that is tapered. Such a configuration may allow the PFET channel to be compressively stressed by a large amount without necessarily substantially degrading extension junction characteristics. The tapered SiGe boundary may be configured as a plurality of discrete steps. For example, two, three, or more discrete steps may be formed.

Abstract: An electrostatic discharge protection element and a protection resistor, which are formed on an N? drain region with a field oxide film interposed therebetween for the purpose of preventing electrical breakdown of a field effect transistor, are composed as a stacked bidirectional Zener diode of one or a plurality of N+ polycrystalline silicon regions of a first layer and a P+ polycrystalline silicon region of a second layer, and a stacked resistor of one or a plurality of N+ resistor layers of the first layer and an N+ resistor layer of the second layer, respectively. One end of the plurality of N+ polycrystalline silicon regions of the first layer is connected to an external gate electrode terminal, and the other end is connected to a source electrode. One end of the plurality of N+ resistor layers of the first layer is connected to a gate electrode, and the other end is connected to the external gate electrode terminal.

Abstract: A laterally configured electrooptical device including: a substrate having a surface; a first semiconductor layer of a first type semiconductor material; a second semiconductor layer formed of a second type semiconductor material different from the first type semiconductor material; a first electrode; and a second electrode. The lower surface of the first semiconductor layer is coupled to a section of the surface of the substrate. The lower surface of the second semiconductor layer is coupled to the upper surface of the first semiconductor layer to form a junction. The first electrode is directly electrically coupled to one side of the first semiconductor layer and the second electrode is directly electrically coupled to an opposite side of the second semiconductor layer. These electrodes are configured such that the lower surface of the first semiconductor layer and/or the upper surface of the second semiconductor layer are substantially unoccluded by them.

Abstract: It is desired for semiconductor devices to reduce leakage currents. In a semiconductor device having a stacked structure including a GaAs layer and an InGaP layer, p-type impurity is doped to the GaAs layer. Consequently, the conduction band of the GaAs is raised to higher than the Fermi level. As a result, electron accumulation is suppressed and the gate leakage current can be reduced.

Abstract: Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the, same conductivity type through an opening in a compound semiconductor material of the opposite conductivity type. Another embodiment discloses a transistor including multiple compound semiconductor layers where a highly doped compound semiconductor material is electrically connected to a compound semiconductor layer of the same conductivity type through an opening in a compound semiconductor layer of the opposite conductivity type. Embodiments further include metal contacts electrically connected to the highly doped compound semiconductor material. A substantially planar semiconductor device is disclosed. In embodiments, the compound semiconductor material may be silicon carbide.

Abstract: A silicon controlled rectifier structure is provided in a substrate having a first conductive type. A well region formed within the substrate has a second conductive type. A first dopant region formed within the substrate and the well region has the first conductive type. A second dopant region formed within the substrate and a portion of the well region has the second conductive type. A third dopant region formed under the second dopant region has the first conductive type, in which the second and the third regions form a vertical Zener diode. A fourth dopant region formed within the substrate and separated from the second dopant region by a separation structure has the second conductive type. A fifth dopant region is formed within the substrate in a manner that the fourth dopant region is between the isolation structure and the fifth dopant region, and has the first conductive type.

Abstract: A single-photon detector is disclosed that provides reduced afterpulsing without some of the disadvantages for doing so in the prior art. An embodiment of the present invention provides a stimulus pulse to the active area of an avalanche photodetector to stimulate charges that are trapped in energy trap states to detrap. In some embodiments of the present invention, the stimulus pulse is a thermal pulse.

Abstract: The present invention describes ESD apparatus, methods of forming the same, and methods of providing ESD protection. In certain aspects, the invention achieves the desired turn-on voltage and maintains low leakage in the ESD apparatus, and the methods of providing ESD protection. In one aspect, a zener diode that has a positive trigger voltage is used to quickly turn-on a transistor. In another aspect, different zener diodes that have positive and negative trigger voltages, respectively, are used to quickly turn on a transistor. In still another aspect, a linearly graded P-region is used to implement the ESD device of the present invention.

Abstract: A semiconductor device includes: a first semiconductor layer including AlXGa1-XN (0?X?1); a second semiconductor layer provided on the first semiconductor layer, including AlYGa1-YN (0?Y?1, X<Y), and having a larger bandgap than the first semiconductor layer; a source electrode provided on the second semiconductor layer; a drain electrode provided on the second semiconductor layer; and a gate electrode provided on the second semiconductor layer between the source electrode and the drain electrode. A region of the second semiconductor layer below the gate electrode at a depth short of the first semiconductor layer is doped with atoms to be negatively charged in the second semiconductor layer.

Abstract: In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.

Abstract: The present invention provides an avalanche photodiode capable of raising productivity. An n-type InP buffer layer, an n-type GaInAs light absorption layer, an n-type GaInAsP transition layer, an n-type InP electric field adjusting layer, an n-type InP avalanche intensifying layer, an n-type AlInAs window layer and a p-type GaInAs contact layer are grown in order on an n-type InP substrate. Next, Be is ion-injected into an annular area along the outer periphery of a light receiving area which is activated by heat treatment so as to form an inclined joint, to obtain a p-type peripheral area for preventing an edge break down. Further, Zn is selectively diffused thermally into the light receiving area until it reaches the n-type InP avalanche intensifying layer so as to form a p-type conductive area.

Abstract: A submount for a semiconductor light emitting device includes a semiconductor substrate having a cavity therein configured to receive the light emitting device. A first bond pad is positioned in the cavity to couple to a first node of a light emitting device received in the cavity. A second bond pad is positioned in the cavity to couple to a second node of a light emitting device positioned therein. Light emitting devices including a solid wavelength conversion member and methods for forming the same are also provided.

Abstract: A MOSFET device that includes a first Zener diode connected between a gate metal and a drain metal of said semiconductor power device for functioning as a gate-drain (GD) clamp diode. The GD clamp diode includes multiple back-to-back doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above the MOSFET device, having an avalanche voltage lower than a source/drain avalanche voltage of the MOSFET device wherein the Zener diode is insulated from a doped region of the MOSFET device for preventing a channeling effect.

Abstract: A semiconductor apparatus includes, a first silicon layer of a first conductivity type; a second silicon layer provided on the first silicon layer and having a higher resistance than the first silicon layer, a third silicon layer of a second conductivity type provided on the second silicon layer, a first nitride semiconductor layer provided on the third silicon layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a larger bandgap than the first nitride semiconductor layer, a first main electrode being in contact with a surface of the second nitride semiconductor layer and connected to the third silicon layer, a second main electrode being in contact with the surface of the second nitride semiconductor layer and connected to the first silicon layer, and a control electrode provided between the first main electrode and the second main electrode on the second nitride semiconductor layer.

Abstract: The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a semiconductor substrate (105), and an insulator (130) located over the first capacitor plate (120), at least a portion of the insulator (130) comprising an interlevel dielectric layer (135, 138, 143, or 148). The integrated high voltage capacitor further includes capacitance uniformity structures (910) located at least partially within the insulator (130) and a second capacitor plate (160) located over the insulator (130).

Abstract: An avalanche photodiode according to this invention include a light receiving region 101 surrounded by a ring-shaped trench 13, a first electrode 11 formed on the light receiving region 101, a second electrode 12 formed on the periphery of the ring-shaped trench 13 surrounding the light receiving region, a first semiconductor layer lying just under the first electrode 11, and a second semiconductor layer lying just under the second electrode 12. Conductivity types of the first semiconductor and the second semiconductor are identical.

Abstract: A nitride-based semiconductor device includes a diode provided on a semiconductor substrate. The diode contains a first nitride-based semiconductor layer made of non-doped AlXGa1-XN (0?X<1); a second nitride-based semiconductor layer made of non-doped or n-type AlYGa1-YN (0<Y?1, X<Y) having a lattice constant smaller than that of the first nitride-based semiconductor layer; a first electrode formed on the second nitride-based semiconductor layer; a second electrode formed on the second nitride-based semiconductor layer; and an insulating film that covers the second nitride-based semiconductor layer below a peripheral portion of the first electrode. In the diode, a recess structure portion is formed at a position near the peripheral portion of the first electrode on the second nitride-based semiconductor layer, and the first electrode covers the second nitride-based semiconductor layer and at least a part of the insulating film.

Abstract: An avalanche photodiode (APD) includes an anode layer, a cathode layer, an absorption layer between the anode layer and the cathode layer, a first multiplying stage between the absorption layer and the cathode layer, a second multiplying stage between the first multiplying stage and the cathode layer, and a carrier relaxation region between the first and second multiplying stages. Each multiplying stage includes, in the direction of drift of electrons, a first layer that is doped with acceptors, a second layer that is substantially undoped, a third layer that is doped with acceptors, a fourth layer that is substantially undoped, and a fifth layer that is doped with donors.

Abstract: A high power diode includes a cathode for emitting a primary electron discharge, an anode, and a porous dielectric layer, e.g. a honeycomb ceramic, positioned between the cathode and the anode for receiving the primary electron discharge and emitting a secondary electron discharge. The diode can operate at voltages 50 kV and higher while generating an electron beam with a uniform current density in the range from 1 A/cm2 to >10 kA/cm2 throughout the area of the cathode. It is capable of repetitively pulsed operation at a few Hz with pulse duration from a few nanoseconds to more than a microseconds, while the total number of pulses can be >107 pulses. The diode generates minimal out-gassing or debris, i.e. with minimal ablation, providing a greater diode lifetime, and can operate in a high vacuum environment of 10?4 Torr. The high power diode is useful in many applications requiring a high current electron beam.

Abstract: A semiconductor integrated circuit device according to the present invention includes a diode in a second island region. The anode region of the diode and the dividing region in a first island region having a horizontal PNP transistor are electrically connected to each other; the cathode region of the diode and the collector region of a power NPN transistor are electrically connected to each other. Accordingly, the dividing region in the first island region having a horizontal PNP transistor becomes lower in potential than the dividing regions in the other island regions, so that the inflow of free carriers (electrons) to the horizontal PNP transistor can be prevented.

Abstract: The present invention provides a heterojunction photodiode which includes a pn or Schottky-barrier junction formed in a first material region having a bandgap energy Eg1. When reverse-biased, the junction creates a depletion region which expands towards a second material region having a bandgap energy Eg2 which is less than Eg1. This facilitates signal photocurrent generated in the second region to flow efficiently through the junction in the first region while minimizing the process-related dark currents and associated noise due to near junction defects and imperfect surfaces which typically reduce photodiode device performance. The heterojunction photodiode can be included in an imaging system which includes an array of junctions to form an imager.

Abstract: A Si-based diode (10, 10?, 100) is formed by epitaxially depositing a Si-based diode structure on a silicon substrate. The Si-based diode structure includes a Si-based pn junction (16, 16?, 18, 18?, 30, 32, 160, 161) having a backward diode current-voltage characteristic in which the forward tunneling current is substantially smaller than the backward tunneling current at comparable voltage levels. In some embodiments, the Si-based pn junction includes at least one non-silicon or silicon alloy layer such as at least one SiGe layer (16, 16?, 160, 161). In some embodiments, at least one delta doping (30, 32) is disposed on the silicon substrate in or near the pn junction, that together with the Si-based pn junction define an electrical junction having the backward diode current-voltage characteristic. A large area detector array may include a plurality of such Si-based diodes (10, 10?, 100).

Abstract: The present invention realizes a heterobipolar transistor using a SiGeC base layer in order to improve its electric characteristics. Specifically, the distribution of carbon and boron within the base layer is controlled so that the concentration of boron is higher than the concentration of carbon on the side bordering on the emitter layer, and upon the formation of the emitter layer, both boron and carbon are dispersed into a portion of the emitter layer that comes into contact with the base layer.

Abstract: An avalanche photodiode has improved low-noise characteristics, high-speed response characteristics, and sensitivity. The avalanche photodiode includes a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, a semiconductor multiplication layer interposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and a semiconductor light-absorbing layer interposed between the semiconductor multiplication layer and the second conductivity type semiconductor layer. The avalanche photodiode further comprises a multiplication suppressing layer which suppresses multiplication of charge carriers in the semiconductor light-absorbing layer, located between the semiconductor light-absorbing layer and the second conductivity type semiconductor layer.

Abstract: The invention provides a method of manufacturing an avalanche diode comprising the steps of applying a mask (6) over an active diode region (5) in a wafer (1), and damaging the region the surrounding the active diode region by breaking bonds in the semiconductor lattice to provide gettering sites in this surrounding region.

Abstract: Integrated circuit varactors and methods for varactor fabrication are provided. Varactors are formed on integrated circuits that contain complementary metal-oxide-semiconductor (CMOS) transistors. The same semiconductor fabrication process steps are used to form both the varactors and CMOS transistors, thereby eliminating potentially cost-prohibitive changes to manufacturing process flows. Varactor performance is enhanced by including a deep n-well structure. The deep n-well reduces sheet resistance in the semiconductor portion of the varactor and improves the varactor's quality factor. The deep n-well is formed from the same deep n-well layer that is used to form the CMOS transistors on the integrated circuit. The varactor has two active electrodes. The electrodes are spaced farther apart than specified by semiconductor fabrication design rules. The number of contact vias used in one of the electrodes is less than the maximum specified by the design rules.

Abstract: A diode structure having high ESD stability is described. Other embodiments provide an integral power switching arrangement having an integrated low leakage diode.

Abstract: An avalanche photodiode has improved low-noise characteristics, high-speed response characteristics, and sensitivity. The avalanche photodiode includes a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, a semiconductor multiplication layer interposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and a semiconductor light-absorbing layer interposed between the semiconductor multiplication layer and the second conductivity type semiconductor layer. The avalanche photodiode further comprises a multiplication suppressing layer which suppresses multiplication of charge carriers in the semiconductor light-absorbing layer, has a thickness of 0.6 ?m or less, and is located between the semiconductor light-absorbing layer and the second conductivity type semiconductor layer. The thickness of the semiconductor light-absorbing layer is 0.5 ?m or more.

Abstract: A bipolar transistor structure and process technology is described incorporating a emitter, a base, and a collector, with most of the intrinsic base adjacent the collector having a graded energy bandgap and a layer of the intrinsic base adjacent the emitter having a substantially constant energy bandgap. The invention has a smaller base transit time than a conventional graded-base-bandgap bipolar transistor.

Abstract: The present invention realizes a heterobipolar transistor using a SiGeC base layer in order to improve its electric characteristics. Specifically, the distribution of carbon and boron within the base layer is controlled so that the concentration of boron is higher than the concentration of carbon on the side bordering on the emitter layer, and upon the formation of the emitter layer, both boron and carbon are dispersed into a portion of the emitter layer that comes into contact with the base layer.

Abstract: On a substrate made of e.g., sapphire single crystal is formed an Al underlayer having FWHM X-ray rocking curve value of 90 seconds or below. A buffer layer is formed on the AlN underlayer and has a composition of AlpGaqIn1?p?qN (0?p?1, 0?y?q). A GaN-based semiconductor layer group is formed on the buffer layer.

Abstract: A blue-ultraviolet on-p-GaAs substrate pin Zn1-xMgxSySe1-y photodiode with high quantum efficiency, small dark current, high reliability and a long lifetime. The ZnMgSSe photodiode has a metallic p-electrode, a p-GaAs single crystal substrate, a p-(ZnSe/ZnTe)m superlattice (m: integer number of sets of thin films), an optionally formed p-ZnSe buffer layer, a p-Zn1-xMgxSySe1-y layer, an i-Zn1-xMgxSySe1-y layer, an n-Zn1-xMgxSySe1-y layer, an n-electrode and an optionally provided antireflection film. Incidence light arrives at the i-layer without passing ZnTe layers. Since the incidence light is not absorbed by ZnTe layers, high quantum efficiency and high sensitivity are obtained.

Abstract: A cascaded diode structure with a deep N-well for effectively reducing the leakage current of the P-type substrate by floating the base of a parasitic transistor in the cascaded diode structure. The cascaded diode structure includes a P-type substrate, a deep N-well formed on the P-type substrate, a plurality of elemental diodes formed on the deep N-well, and a plurality of connecting parts for cascading the elemental diodes. Each elemental diode includes a P-well formed on the deep N-well, a heavily doped P-type region formed on the P-well, and a heavily doped N-type region formed on the P-well.

Abstract: A sequential mesa type avalanche photodiode (APD) includes a semiconductor substrate and a sequential mesa portion formed on the substrate. In the sequential mesa portion, a plurality of semiconductor layers, including a light absorbing layer and a multiplying layer, are laminated by epitaxial growth. In the plurality of semiconductor layers, a pair of semiconductor layers forming a pn junction is included. The carrier density of a semiconductor layer which is near to the substrate among the pair of semiconductor layers is larger than the carrier density of a semiconductor layer which is far from the substrate among the pair of semiconductor layers. In the APD, light-receiving current based on movement of electrons and positive holes generated in the sequential mesa portion when light is incident from the substrate toward the light absorbing layer is larger at a central portion than at a peripheral portion of the sequential mesa portion.

Abstract: A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region (160, 360) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer (180, 380) above the fourth semiconductor region and the fifth semiconductor region. A junction (145, 345) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region (170) circumscribes the third, fourth, fifth, and sixth semiconductor regions.

Abstract: A semiconductor arrangement including: a substrate having a substrate layer (13) with an upper and lower surface, the substrate layer (13) being of a first conductivity type; a first buried layer (12) in the substrate, extending along said lower surface below a first portion of said upper surface of said substrate layer (13), and a second buried layer (12) in the substrate, extending along said lower surface below a second portion of said upper surface of said substrate layer (13); a first diffusion (26) in said first portion of said substrate layer (13), being of a second conductivity type opposite to said first conductivity type and having a first distance to said first buried layer (12) for defining a first breakdown voltage between said first diffusion (26) and said first buried layer (12); a second diffusion (45) in said second portion of said substrate layer (13), being of said second conductivity type and having a second distance to said second buried layer (12) for defining a second breakdown volta

Abstract: A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and then also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits.

Abstract: A wavelength-selective photo detector device includes a transparent upper electrode including a capacitor, a first semiconductor layer disposed under the upper electrode, an optical absorption layer disposed under the first semiconductor layer for absorbing light to form pairs of electrons and holes, an amplification layer disposed under the optical absorption layer for generating secondary electrons, a second semiconductor layer disposed under the amplification layer, and a lower electrode disposed under the second semiconductor layer and including an inductance coupled in parallel with an external resistance. The photo detector improves the S/N ratio and filters only light having a particular wavelength band.

Abstract: In a photoelectric conversion device comprising a first-conductivity type first semiconductor region located in a pixel region, a second-conductivity type second semiconductor region provided in the first semiconductor region, and a wiring for electrically connecting the second semiconductor region to a circuit element located outside the pixel region, a shield is provided on the light-incident side of the wiring, via an insulator in such a way that it covers at least part of the wiring and also the shield comprises a conductor whose potential stands fixed. This photoelectric conversion device may hardly be affected with low-frequency radiated noises as typified by power-source noise.

Abstract: A blue-ultraviolet on-p-GaAs substrate pin Zn1-xMgxSySe1-y photodiode with high quantum efficiency, small dark current, high reliability and a long lifetime. The ZnMgSSe photodiode has a metallic p-electrode, a p-GaAs single crystal substrate, a p-(ZnSe/ZnTe)m superlattice (m: integer number of sets of thin films), an optionally formed p-ZnSe buffer layer, a p-Zn1-xMgxSySe1-y layer, an i-Zn1-xMgxSySe1-y layer, an n-Zn1-xMgxSySe1-y layer, an n-electrode and an optionally provided antireflection film. Incidence light arrives at the i-layer without passing ZnTe layers. Since the incidence light is not absorbed by ZnTe layers, high quantum efficiency and high sensitivity are obtained.

Abstract: A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits.

Abstract: A new gate-controlled, negative resistance diode device is achieved. The device comprises, first, a semiconductor layer in a substrate. The semiconductor layer contains an emitter region and a barrier region. The barrier region is in contact with the emitter region and is laterally adjacent to the emitter region. The semiconductor layer contains a collector region. A drift region comprises the semiconductor layer between the barrier region and the collector region. Finally, a gate comprises a conductor layer overlying the drift region, the barrier region, and at least a part of the emitter region with an insulating layer therebetween. A method of manufacture is achieved.

Abstract: A cold electron emitter may include a heavily a p-doped semiconductor, and dielectric layer, and a metallic layer (p-D-M structure). A modification of this structure includes a heavily n+ doped region below the p region (n+-p-D-M structure). These structures make it possible to combine high current emission with stable (durable) operation. The high current density is possible since under certain voltage drop across the dielectric layer, effective negative electron affinity is realized for the quasi-equilibrium “cold” electrons accumulated in the depletion layer in the p-region next to the dielectric layer. These electrons are generated as a result of the avalanche in the p-D-M structure or injection processes in the n+-p-D-M structure. These emitters are stable since they make use of relatively low extracting field in the vacuum region and are not affected by contamination and absorption from accelerated ions. In addition, the structures may be fabricated with current state-of-the-art technology.

Abstract: The invention relates to the protection of devices in a monolithic chip fabricated from an epitaxial wafer, such as a wafer for a Group III-V compound semiconductor or a wafer for a Group IV compound semiconductor. Devices fabricated from Group III-V compound semiconductors offer higher speed and better isolation than comparable devices from silicon semiconductors. Semiconductor devices can be permanently damaged when exposed to an undesired voltage transient such as electrostatic discharge (ESD). However, conventional techniques developed for silicon devices are not compatible with processing techniques for Group III-V compound semiconductors, such as gallium arsenide (GaAs). Embodiments of the invention advantageously include transient voltage protection circuits that are relatively efficiently and reliably manufactured to protect sensitive devices from undesired voltage transients.

Abstract: Vertically oriented semiconductor devices may be added to a separately fabricated substrate that includes electrical devices and/or interconnect. The plurality of vertically oriented semiconductor devices are physically separated from each other, and are not disposed within the same semiconductor body, or semiconductor substrate. The plurality of vertically oriented semiconductor devices may be added to the separately fabricated substrate as a thin layer including several doped semiconductor regions which, subsequent to attachment, are etched to produce individual doped stack structures. Alternatively, the plurality of vertically oriented semiconductor devices may be fabricated prior to attachment to the separately fabricated substrate. The doped stack structures may form the basis for diodes, capacitors, n-MOSFETs, p-MOSFETs, bipolar transistors, and floating gate transistors.

Abstract: Methods and apparatus for forming word line stacks comprise forming a thin nitride layer coupled between a bottom silicon layer and a conductor layer. In a further embodiment, a diffusion barrier layer is coupled between the thin nitride layer and the bottom silicon layer. The thin nitride layer is formed by annealing a silicon oxide film in a nitrogen-containing ambient.