Abstract: An avalanche photodiode (APD) of the present invention uses a distortion-compensated superlattice multiplication layer (103) for the superlattice multiplication layer. It also uses a multi-layered light-reflecting layer as the light-reflecting layer. This structure of the present invention makes it possible to reduce a layer thickness of the superlattice multiplication layer without decreasing an electron multiplication factor and increasing a dark current. Accordingly, the APD of the present invention shows high response and low operating voltage, while it also maintains low dark current, low noise and broad band at the same time.

Abstract: A plurality of connection holes 24 for connecting n+ type semiconductor region 20 of zener diodes (D1, D2) and wires 21 and 22 to each other are not arranged in the center of the n+ type semiconductor region 20, that is, in a region in which a p+ type semiconductor region 6 and the n+ type semiconductor region 20 form a junction but is arranged in the periphery which is deeper than the center in junction depth. In addition, these connection holes 24 are spaced from each other so that a pitch between the adjacent connection holes 24 is greater than a minimum pitch between connection holes of the circuit, and thereby a substrate shaving quantity is reduced when the respective connection holes 24 are formed by means of dry etching.

Abstract: A semiconductor device with a tunnel diode (23) is particularly suitable for various applications. Such a device comprises two mutually adjoining semiconductor regions (2, 3) of opposed conductivity types and having doping concentrations which are so high that breakdown between them leads to conduction by means of tunnelling. A disadvantage of the known device is that the current-voltage characteristic is not yet steep enough for some applications. In a device according to the invention, the portions (2A, 3A) of the semiconductor regions (2, 3) adjoining the junction (23) comprise a mixed crystal of silicon and germanium. It is surprisingly found that the doping concentration of both phosphorus and boron are substantially increased, given the same amount of dopants being offered as during the formation of the remainder of the regions (2, 3).

Abstract: A solid state electronic device exhibiting negative differential resistance is fabricated by depositing a thin layer of amorphous silicon on a single crystal substrate, doped N+. The amorphous silicon is simultaneously crystallized and oxidized in a dry N2 and O2 mixture. The result is a layer of amorphous SiO2 surrounding microclusters of crystalline silicon. A layer of polycrystalline silicon is deposited to a thickness of approximately 0.5 micron. Ohmic metal contacts are made to the top and bottom. These active layers are isolated by insulating SiO2. A bias voltage applied between the metal contacts results in negative differential resistance due to tunneling through resonant energy levels in microclusters.

Abstract: With the object of providing a high-speed high-sensitivity planar-type avalanche photodiode (APD) that has high reliability, great manufacturing tolerance and a wide dynamic range, there is presented a planar-type avalanche photodiode, having on a semiconductor substrate a layered structure comprising specific 6 layers, a specific conductive-type acquired region in a peripheral section of a photo-sensitive region and a specific ring-shaped isolation trench region in said photo-sensitive region, wherein a ring-shaped region of the second conductive-type semiconductor cap layer that is inscribed in said ring-shaped isolation trench and located in the periphery of the photo-sensitive region is formed thin to have a thickness equal to or less than the thickness of said semiconductor multiplication layer, and the first conductive-type semiconductor field buffer layer located directly under the ring-shaped cap region, together with a peripheral region in the field buffer layer, is formed to have a lower carrier con

Abstract: A method of fabricating an integrated circuit includes forming a gate stack upon an active region of a substrate which includes a gate dielectric, a polysilicon gate conductor and a polysilicon consumption metal layer portion. The polysilicon consumption metal layer portion is then reacted with the polysilicon gate conductor to form a high conductivity gate conductor (silicide). In one embodiment, the polysilicon gate conductor is fully consumed. In another embodiment, the polysilicon gate conductor is substantially consumed but a portion of the polysilicon gate conductor adjacent the gate dielectric remains. In forming such a gate structure, a gate dielectric layer is first formed and a polysilicon gate layer is formed upon the gate dielectric layer. A polysilicon consumption metal layer is then formed upon the polysilicon gate layer. The surface is then patterned mask so that the location of the gate structures is protected. The substrate is then anisotropically etched to form the gate structures.

Abstract: The present invention provides a power semiconductor device comprising a semiconductor substrate; a voltage-controlled transistor comprising a first electrode formed on the lower surface of the semiconductor substrate, a gate formed on the semiconductor substrate with a gate oxide interpolated in between and a second electrode formed on the semiconductor substrate; and a zener diode formed on the upper surface of the semiconductor substrate so as to be connected between the gate and the second electrode; wherein p-type regions and n-type regions alternately formed between the zener diode and the second electrode on the semiconductor substrate, a plurality of pad electrodes on the semiconductor substrate provided with the alternate p-type regions and n-type regions so as to allow one or not less than two diodes are series connected between the zener diode and the second electrode, and the distance between the adjacent pad electrodes is set so that when the diode is subjected to a current not less than a predet

Abstract: A semiconductor device is provided which includes a first conductivity type semiconductor substrate, a second conductivity type Zener region formed in a surface layer of the first conductivity type semiconductor substrate, a first conductivity type anode region formed within the second conductivity type Zener region, an anode electrode which is formed in contact with both of the semiconductor substrate and first conductivity type anode region and is grounded, and a cathode electrode formed on a surface of the second conductivity type Zener region and connected to input and output terminals. A diode that consists of the first conductivity type semiconductor substrate and the second conductivity type Zener region and a diode that consists of the first conductivity type anode region and the second conductivity type Zener region serve as protective elements for preventing electrostatic breakdown of the semiconductor device.

Abstract: A solid state electronic device exhibiting negative differential resistance s fabricated by depositing a thin layer of amorphous silicon on a single crystal substrate, doped N.sup.+. The amorphous silicon is simultaneously crystallized and oxidized in a dry N.sub.2 and O.sub.2 mixture. The result is a layer of amorphous Sio.sub.2 surrounding microclusters of crystalline silicon. A layer of polycrystalline silicon is deposited to a thickness of approximately 0.5 micron. Ohmic metal contacts are made to the top and bottom. These active layers are isolated by insulating SiO.sub.2. A bias voltage applied between the metal contacts results in negative differential resistance due to tunneling through resonant energy levels in microclusters.

Abstract: An light emitting diode of indium gallium aluminum phosphide with a substrate, an electrical contact to the substrate, a dual hetero structure as a active zone comprising a first cladding layer, an active layer and a second cladding layer to which, a window layer is applied, and to which in turn, an electrical contact is applied. This window layer is made of gallium aluminum phosphide.

Abstract: The present invention relates to a light-controlled semiconductor heterostructure component for generating microwave frequency oscillations, wherein the heterostructure comprises at least two semiconductor materials: at least one of them absorbing light by creating electron-hole pairs; and the other one of them having majority carriers with a relationship of velocity as a function of electric field that presents a region of negative slope.

Abstract: A semiconductor device is provided with a surface-inactivated semiconductor layer provided on the surface of a compound semiconductor on which surface a semiconductor layer forming the depletion layer is provided, the semiconductor layer forming the depletion layer being of a conduction type opposite that of the compound semiconductor, and having a carrier density and thickness being capable of forming a depletion layer on the compound semiconductor. When a depletion layer is formed on the surface of the compound semiconductor by the semiconductor layer forming the depletion layer, the depletion layer has no charge so that the concentration of electrical fields is relaxed, the surface of the semiconductor is stabilized, and excellent dielectric breakdown performance is obtained.

Abstract: A monolithic circuit including an IMPATT with the IMPATT formed as a plurality of parallel vertical fingers or an array of vertical mesas having a common doped region to apread the area for heat dissipation through the substrate.

Abstract: Integrated circuits and fabrication methods incorporating both two-terminal devices such as IMPATT diodes (446) and Schottky diodes (454) and three-terminal devices such as n-channel MESFETs (480) in a monolithic integrated circuit.

Abstract: A zener diode having a semiconductor body (1) with a surface zone (1') doped with more than 10.sup.18 atoms/cc, in which at least two regions (2, 3) are provided through diffusion, which regions have substantially the same concentration of doping atoms and adjoin a surface (4) of the surface zone (1') and form p-n junctions (5,6) with the surface zone (1'), a first region (2) having a smaller lateral cross-section and a smaller depth than a second region (3). Both regions (2, 3) are connected to a first connection electrode (7, 8) provided on the surface (4), and a second connection electrode (9), which is spaced apart from the regions (2, 3), is provided on the semiconductor body (1). The first region has a side edge (10) which is formed through lateral diffusion and which is at least partly spaced apart from the second region (3). A higher electric field is created locally in the junction (5) during operation of the zener diode owing to the side edge (10).

Abstract: A planar frequency tripler comprised of two semiconductor diode structures connected back-to-back by an n.sup.+ doped layer (N.sup.+) of semiconductor material utilizes an n doped semiconductor material for a drift region (N) over the back contact layer in order to overcome a space charge limitation in the drift region. A barrier layer (B) is grown over the drift region, after a sheet of n-type doping (N.sub.sheet) which forms a positive charge over the drift region, N, to internally bias the diode structure. Two metal contacts are deposited over the barrier layer, B, with a gap between them. To increase the power output of the diodes of a given size, stacked diodes may be provided by alternating barrier layers and drift region layers, starting with a barrier layer and providing a positive charge sheet at the interface of a barrier on both sides of each drift region layer with n-type .delta. doping. The stacked diodes may be isolated by etching or ion implantation to the back contact layer N.sup.

Abstract: An avalanche photodiode having a beryllium guard ring. The beryllium is implanted at a dosage of at least 5.times.10.sup.14 per cm.sup.2 and subsequently annealed to provide a guard ring profile with a p+core and a superlinearly graded tail. The doping profile of the guard ring immediately adjacent the core is superlogarithmic.

Abstract: A heterojunction bipolar transistor includes a tungsten layer formed on a base layer. An insulating sidewall is formed on the base layer and along a vertical wall of an emitter layer formed on the base layer. An end of the tungsten layer faces a base-emitter heterojunction through the sidewall.

Abstract: A GaAs/AlGaAs heterojunction IMPATT diode is described. The AlGaAs n-type avalanche layer is graded so that a 0.30 eV bandgap discontinuity of the pn heterojunction is provided without any bandgap discontinuity at the avalanche/drift layer interface. Minority carriers in the p-type GaAs layer are concentrated at the junction due to the discontinuity which occurs primarily in the conduction band thereby concentrating the zero bias electric field and thus minimizing the voltage drop across the avalanche layer. Furthermore, the zero bias depletion width is increased due to the increased field, which lowers the device capacitance.