Abstract: A method for fabricating a LDMOS device, including: forming a semiconductor substrate; forming a dielectric layer atop the semiconductor substrate and an electric conducting layer on the dielectric layer; forming a first photoresist layer on the electric conducting layer; patterning the first photoresist layer through a first mask to form a first opening; etching the electric conducting layer through the first opening; implanting dopants of a first doping type into the semiconductor substrate through the first opening to form a first body region adjacent to the surface of the semiconductor substrate, and a second body region located beneath the first body region; removing the first photoresist layer; etching the electric conducting layer using a second photoresist layer and a second mask.

Abstract: First electrically conductive lines can be formed over a substrate. A two-dimensional array of vertical stacks can be formed, each of which includes a first electrode, an in-process resistive memory material portion, and a second electrode over the first electrically conductive line. The sidewalls of the in-process resistive memory material portions are laterally recessed with respect to sidewalls of the first electrode and the second electrode to form resistive memory material portions having reduced lateral dimensions. A dielectric material layer is formed by an anisotropic deposition to form annular cavities that laterally surround a respective one of the resistive memory material portions. Second electrically conductive lines can be formed on the second electrodes.

Abstract: A method for producing a memory device includes depositing a second interlayer insulating film on a substrate, forming contact holes, and depositing a second metal and a nitride film. The second metal and the nitride film are removed to form pillar-shaped nitride layers, and to form lower electrodes surrounding the pillar-shaped nitride layers. The second interlayer insulating film is etched back to expose upper portions of the lower electrodes. The upper portions of the lower electrodes surrounding the pillar-shaped nitride film are removed and a phase change film is deposited to surround the pillar-shaped nitride film and connect with the lower electrodes. The phase change film is etched on upper portions of the pillar-shaped nitride film, and a reset gate insulating film is formed surrounding the phase change film and forming a reset gate having a side wall shape and remaining on the upper portions of the pillar-shaped nitride film.

Abstract: A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.

Abstract: Silicon single crystals are pulled from a melt in a crucible, the single crystal surrounded by a heat shield, the lower end of which is a distance h from the melt surface, wherein gas flows downward between the single crystal and the heat shield, outward between the lower end of the heat shield and the melt, and then upward in the region outside the heat shield. The internal diameter of the heat shield at its lower end is 55 mm or more than the diameter of the single crystal, and the radial width of the heat shield at its lower end is not more than 20% of the diameter of the single crystal. Highly doped single crystals pulled accordingly have a void concentration ?50 m?3.

Abstract: A memory system includes a semiconductor memory device, a controller configured to access the semiconductor module, a plurality of pins for connection to the outside of the memory system, the pins configured to receive and output serial data, and a test circuit. When one of the pins receives serial test data, the test circuit converts the serial test data into parallel test data, and outputs the parallel test data to the semiconductor memory device for writing therein, and when the test circuit receives parallel test data written in the semiconductor memory device, the test circuit converts the parallel test data to serial test data, and outputs the serial test data through one of the pins for test of the memory system.

Abstract: RF commutator including: a phase change material (7) arranged between a first conducting element (2) and a second conducting element (4), means of heating (11, 13) the phase change material provided with a first electrode (11) and a second electrode (13), the means of heating being capable of modifying the state of the phase change material (7) by injection of an electrical activation signal between the first electrode and the second electrode, at least one given electrode (11, 13) among the first electrode (11) and second electrode (13) comprising a conducting part (15a) arranged between the first conducting element (2) and the second conducting element (4), zones of the phase change material being laid out between the first conducting element (2) and the second conducting element (4) and being arranged on either side of this conducting part (15a).

Abstract: A data storage method applying to the phase change memory and a phase change memory are provided. After obtaining to-be-stored data, the phase change memory generates an erase pulse signal and a write pulse signal according to the to-be-stored data. The to-be-stored data is multi-bit data. The write pulse signal is a signal including at least two consecutive pulses with a same amplitude. The amplitude of the at least two consecutive pulses is a value determined according to the to-be-stored data. Then, the phase change memory applies the erase pulse signal to a storage unit of the phase change memory to allow the storage unit to switch to a crystalline state. Further, the write pulse signal is applied to the storage unit to allow the storage unit to switch to an amorphous state corresponding to a first resistance value, where the amorphous state represents the to-be-stored data.

Abstract: In an example, a printhead includes a memristor, in which the memristor may include a first electrode, a second electrode positioned in a crossed relationship with the first electrode to form a junction, and a switching element positioned at the junction between the first electrode and the second electrode, in which the switching layer includes a via formed in the switching element to reduce an area of the switching element.

Abstract: A method of depositing nanowires including generating wells disposed on a patterned conductive film. The patterned conductive film includes well-sites. The patterned conducive film covers a portion of a surface of a substrate. Each of the wells is disposed proximate to a corresponding wellsite. The method includes applying a nanowire mixture to the wells and, after applying the nanowire mixture, at least one nanowire is deposited on a first portion and a second portion of the patterned conductive film by generating an electric field proximate to the patterned conductive film. The first portion and the second portion of the patterned conductive film are separated by a gap.

Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a good yield, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer, and forming a variable resistance dielectric data storage layer having a first thickness onto the bottom electrode. A capping layer is formed onto the dielectric data storage layer. The capping layer has a second thickness that is in a range of between approximately 2 to approximately 3 times thicker than the first thickness. A top electrode is formed over the capping layer, and an upper metal interconnect layer is formed over the top electrode.

Abstract: As a cost effective alternative to lithography, there is provided a method of forming an electronic device comprising the steps of: depositing a first quantity of a first liquid medium comprising a dopant on a first portion of a planar surface and depositing a second quantity of the first liquid medium on a second portion of the surface, the first quantity spaced from the second quantity by a gap; heating the first quantity, the second quantity, and the surface, the heating configured to cause diffusion of at least some of the dopant from the first liquid medium into the surface; depositing a dielectric material on the surface in the gap; selectively removing the first quantity and the second quantity from the surface; depositing an electrical contact on each of the first portion and the second portion; and depositing a further electrical contact on the dielectric material.

Abstract: A semiconductor device includes an interconnection formed above a substrate, and the interconnection comprising interconnect layers respectively buried in dielectric layers; a lower conducting layer formed above the substrate; a memory cell structure formed on the lower conducting layer and buried in one of the dielectric layers; an upper conducting layer formed on the memory cell structure. The memory cell structure includes a bottom electrode formed on and electrically connected to the lower conducting layer; a transitional metal oxide (TMO) layer formed on the bottom electrode; and a top electrode formed on the TMO layer, wherein the upper conducting layer is formed on the top electrode and electrically connected to the top electrode. Also, the lower conducting layer and the upper conducting layer are positioned in the different dielectric layers.

Abstract: A communication circuit includes a first switch circuit having a first terminal at which a first signal of a first frequency can be input, a second terminal at which a second signal of a second frequency can be input, and a plurality of third terminals from which the first signal and the second signal can be output. A second switch circuit has a plurality fourth terminals corresponding to the plurality of third terminals and at which the first or second signal can be received from the first switch circuit, a fifth terminal at which the first signal can be output, and a sixth terminal at which the second signal can be output. Each fourth terminal is connectable to either of the fifth terminal and the sixth terminal.

Abstract: A memory device includes a substrate, a first conductive layer above the substrate and extending in a first direction parallel to a surface of the substrate, a second conductive layer above the first conductive layer and extending in the first direction, wherein centers of the first and second conductive layers are aligned in a second direction that is substantially perpendicular to the surface of the substrate, and a contact extending in the second direction from a position lower than the first conductive layer to a position higher than the second conductive layer, the contact being electrically connected to and in direct contact with the first conductive layer and electrically insulated and physically separated from the second conductive layer.

Abstract: Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.

Abstract: A graphene-based valley filter includes a bottom gate, a bilayer graphene and two top gates. The bilayer graphene is deposited on the bottom gate and includes scattering defects. The top gates are deposited on the bilayer graphene. The top gates define a channel in the bilayer graphene, and the scattering defects are located in the vicinity of the channel. A vertical electric field is formed to open a band gap and produce electronic energy subbands in the channel. A transverse in-plane electric field is formed to produce pseudospin splitting in the subbands of the bilayer graphene. The scattering defects are for producing scattering between two opposite energy valley states of the bilayer graphene, couples subband states of opposite pseudospins and opens a pseudogap at a crossing point of the two subbands. Electrons are passed through the channel to become valley polarized in the bilayer graphene.

Abstract: An optoelectronic device comprises a substrate; pads on a surface of the substrate; semiconductor elements, each element resting on a pad; a portion covering at least the lateral sides of each pad, the portion preventing the growth of the semiconductor elements on the lateral sides; and a dielectric region extending in the substrate from the surface and connecting, for each pair of pads, one of the pads in the pair to the other pad in the pair. A method of manufacturing an optoelectronic device is also disclosed.

Abstract: The present invention relates to IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a variant of the original set of design rules and methods for making the same.

Abstract: Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.

Abstract: The present invention provides a method of producing an epitaxial wafer having a highly flat rear surface without polishing top and rear surfaces of the epitaxial wafer after forming an epitaxial film. A method of producing an epitaxial wafer 100 according to the present invention comprises a step of preparing a semiconductor wafer 10 having a beveled portion 11 formed on its end portion, a first surface 12b, a second surface 12a opposite to the first surface 12b, and edges 13b and 13a on both of the first surface 12b and the second surface 12a, the each edge 13a and 13b is boundary with the beveled portion 11; a step of processing of rolling off an outer peripheral portion 14 of the first surface 12b to form a roll-off region, the outer peripheral portion 14 is extending outward of the wafer from a predetermined position P inner than the position of the edge 13b on 12a the first surface 12b; and a step of forming a first epitaxial film 20 on the second surface 12a.

Abstract: A monolithic three-dimensional memory device includes a first memory block containing a plurality of memory sub-blocks located on a substrate. Each memory sub-block includes a set of memory stack structures and a portion of alternating layers laterally surrounding the set of memory stack structures. The alternating layers include insulating layers and electrically conductive layers. A first portion of a neighboring pair of memory sub-blocks is laterally spaced from each other along a first horizontal direction by a backside contact via structure. A subset of the alternating layers contiguously extends between a second portion of the neighboring pair of memory sub-blocks through a gap in a bridge region between two portions of the backside contact via structure that are laterally spaced apart along a second horizontal direction to provide a connecting portion between the neighboring pair of memory sub-blocks.

Abstract: A semiconductor device according to embodiments described below includes an element region and a peripheral region. The element region is disposed on a substrate and semiconductor elements are collocated in the element region. The peripheral region is disposed on the substrate and surrounds the element region. The element region extends in a first direction parallel to the substrate and includes a plurality of wiring layers laminated on the substrate. The peripheral region includes a peripheral layer arranged to surround the element region. The peripheral layer includes a first part extending in the first direction and a second part extending in a second direction intersecting the first direction. The cross-section structures of the first part and the second part are different from one another.

Abstract: A first doped region is formed in a single crystalline semiconductor substrate. Light ions are implanted through a process surface into the semiconductor substrate to generate crystal lattice vacancies between the first doped region and the process surface, wherein a main beam axis of an implant beam used for implanting the light ions deviates by at most 1.5 degree from a main crystal direction along which channeling of the light ions occurs. A second doped region with a conductivity type opposite to the first doped region is formed based on the crystal lattice vacancies and hydrogen atoms.

Abstract: Heat-trapping bulk layers or thermal-boundary film stacks are formed between a heat-assisted active layer and an associated electrode to confine such transient heat to the active layer in a heat-assisted device (e.g., certain types of resistance-switching and selector elements used in non-volatile memory. Preferably, the heat-trapping layers or thermal-boundary stacks are electrically conductive while being thermally insulating or reflective. Heat-trapping layers use bulk absorption and re-radiation to trap heat. Materials may include, without limitation, chalcogenides with Group 6 elements. Thermal-boundary stacks use reflection from interfaces to trap heat and may include film layers as thin as 1-5 monolayers. Effectiveness of a thermal-boundary stack depends on the thermal impedance mismatch between layers of the stack, rendering thermally insulating bulk materials optional for thermal-boundary stack components.

Abstract: A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and regions, with implant regions and covered regions, in the semiconductor substrate. A hardmask covers a first covered region and a second covered. The first implant region having a first concentration of ions, and at least one second implant region having a second concentration that is less than the first concentration. First and second FETs are formed on the regions. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.

Abstract: Phase transition devices may include a functional layer made of functional material that can undergo a change in conductance in response to an external stimulus such as an electric or magnetic or optical field, or heat. The functional material transitions between a conducting state and a non-conducting state, upon application of the external stimulus. A capacitive device may include a functional layer between a top electrode and a bottom electrode, and a dielectric layer between the functional layer and the top electrode. A three terminal phase transition switch may include a functional layer, for example a conductive oxide channel, deposited between a source and a drain, and a gate dielectric layer and a gate electrode deposited on the functional layer. An array of phase transition switches and/or capacitive devices may be formed on a substrate, which may be made of inexpensive flexible material.

Abstract: A method can include epitaxially growing epitaxial growth material within a logic region of a semiconductor structure. A method can include performing simultaneously with the growing epitaxial growth within an analog region of the semiconductor structure. A method can include performing epitaxial growth to form an epitaxial growth formation that defines an electrode of an analog device within an analog region of the semiconductor structure, wherein the performing includes using a first surface and a second surface as seed surfaces.

Abstract: A method has been developed to overcome deficiencies in the prior art in the properties and fabrication of semi-polar group III-nitride templates, films, and materials. A novel variant of hydride vapor phase epitaxy has been developed that provides for controlled growth of nanometer-scale periodic structures. The growth method has been utilized to grow multi-period stacks of alternating AlGaN layers of distinct compositions. The application of such periodic structures to semi-polar III-nitrides yielded superior structural and morphological properties of the material, including reduced threading dislocation density and surface roughness at the free surface of the as-grown material. Such enhancements enable to fabrication of superior quality semi-polar III-nitride electronic and optoelectronic devices, including but not limited to transistors, light emitting diodes, and laser diodes.

Abstract: According to the present invention, there is provided an indium recovery method for recovering indium from an indium-containing product, including a leaching step of allowing indium to leach into an aqueous hydrochloric acid solution by hydrothermal leaching using the aqueous hydrochloric acid solution as a leaching agent from the indium-containing product to obtain a leachate composed of an aqueous hydrochloric acid solution containing indium, and a separating step of adding a microbe for adsorbing In ions to the leachate to separate indium from the leachate.

Abstract: According to one embodiment, a semiconductor memory device includes a first array extending in a first direction, a second array extending in the first direction, and a second electrode film. The second array is arranged with the first array in a second direction crossing the first direction. The second electrode film provided between the first array and the second array. The second electrode film extends in the first direction. Each of the first array and the second array include a first structure, a second structure arranged in the first direction, a fourth insulating film provided between the first structure and the second structure, and a third insulating film provided between the first structure and the second electrode film, provided also between the first structure and the fourth insulating film.

Abstract: Magnetic memory cells include a magnetic tunnel junction and a first electrode, which is electrically coupled to the magnetic tunnel junction by a first conductive structure. This conductive structure includes a blocking layer and a seed layer, which extends between the blocking layer and the magnetic tunnel junction. The blocking layer is formed as an amorphous metal compound. In some of the embodiments, the blocking layer is a thermally treated layer and an amorphous state of the blocking layer is maintained during and post thermal treatment.

Abstract: A resistance change nonvolatile memory device, includes: a first wiring; an interlayer insulating layer formed over the first wiring; and a second wiring formed over the interlayer insulating layer, wherein the interlayer insulating layer is interposed between the first wiring and the second wiring and includes a hole having a width not greater than a width of the first wiring, wherein the resistance change nonvolatile memory device further includes a lower electrode formed at a bottom portion of the hole and contacting the first wiring; a resistance change layer formed on the lower electrode; and an upper electrode formed over the resistance change layer, wherein the lower electrode, the resistance change layer, and the upper electrode are formed inside the hole, wherein an entirety of the resistance change layer is disposed inside the hole.

Abstract: An embodiment relates to a transistor device including a pillar of semiconductor material extending vertically from a bottom portion in contact with an electrically conductive contact line, where the electrically conductive contact line extends laterally past the pillar in a horizontal direction, a gate insulating liner layer on a lateral side of the pillar, a gate electrode on the gate insulating layer extending along the lateral side of the pillar, and a region of electrically insulating semiconductor oxide material filling a space between a bottom portion of the gate electrode and a top portion of the electrically conductive contact line.

Abstract: An optoelectronic device comprises a substrate; pads on a surface of the substrate; semiconductor elements, each element resting on a pad; a portion covering at least the lateral sides of each pad, the portion preventing the growth of the semiconductor elements on the lateral sides; and a dielectric region extending in the substrate from the surface and connecting, for each pair of pads, one of the pads in the pair to the other pad in the pair. A method of manufacturing an optoelectronic device is also disclosed.

Abstract: Pressure sensing systems comprising bulk-solidifying amorphous alloys and pressure-sensitive switches containing bulk-solidifying amorphous alloys. The bulk-solidifying amorphous alloys are capable of repeated deformation upon application of pressure, and change their electrical resistivity upon deformation, thereby enabling measurement of the change in resistivity and consequently, measuring the deformation and amount of pressure applied.

Abstract: Majority and minority logic can be implemented by voltage controlled switching of magneto-electric layers of magneto electric magnetic tunnel junction (ME-MTJ) devices. A ME-MTJ device includes an exchange bias-controlled switching element and a pinned ferromagnetic layer on an antiferromagnetic layer. In one case, the switching element includes a magneto electric (ME) layer on a free ferromagnetic (FM) layer, and is separated from the pinned FM layer by an insulator. To implement a majority or minority logic gate a single ME-MTJ device may be used where the device is provided with three electrodes contacting the ME layer in an overlaying relationship with the ME layer. The orientation of the pinned FM layer indicates whether the gate is a majority or a minority logic gate.

Abstract: Various embodiments of a composite material are provided. In one embodiment of the present invention a nanometer-scale composite material comprises, by volume, from about 1% to about 99% variable-conductivity material and from about 99% to about 1% conductive material. The composite material exhibits memristive properties when a voltage differential is applied to the nanocomposite. In another embodiment, a variable resistor device includes a first electrode terminal and a second electrode terminal and a nanocomposite in electrical communication with the electrode terminals. The composite material comprises, by volume, from about 1% to about 99% variable-conductivity material and from about 99% to about 1% conductive material. The memristor is tunable as the minimum instantaneous resistance can be altered several orders of magnitude by varying the composition and ratio of the variable-conductivity material and conductive material constituents of the composites.

Abstract: A device is disclosed. The device includes a top electrode, a bottom electrode and a storage element between the top and bottom electrodes. The storage element includes a heat generating element disposed on the bottom electrode, a phase change element wrapping around an upper portion of the heat generating element, and a dielectric liner sandwiched between the phase change element and the heat generating element.

Abstract: A low-current FN channel scheme for erase, program, program-inhibit and read operations is disclosed for NAND NVM memories. This invention discloses a block array architecture and 3-step half-page program algorithm to achieve less error rate of NAND cell threshold voltage level. Thus, the error correction code capability requirement can be reduced, thus the program yield can be increased to reduce the overall NAND die cost at advanced nodes below 20 nm. As a result, this NAND array can still use the LV, compact PGM buffer for saving in the silicon area and power consumption. In addition, the simpler on-chip state-machine design can be achieved with the superior quality of less program errors.

Abstract: A semiconductor structure for emitting light including a substrate made of a first semi-conductor material having a first type of conductivity, a first electrical contact, a second semiconductor material, having a second type of conductivity to form a junction, a second electrical contact contacting the second semiconductor material, a polarizer configured to polarize at least one portion of the semiconductor structure, and a plurality of micro- or nano-structures each including a first end connected to the substrate. Each micro- or nano-structure includes at least one portion made from the second semiconductor material, or each micro- or nano-structure having the first type of conductivity, a second end contacting the second semiconductor material to form the junction.

Abstract: Provided is a nonvolatile magnetic device that is capable of realizing low power consumption by performing writing with a voltage and is also excellent in retention characteristics. The nonvolatile magnetic device includes a nonvolatile magnetic element. The nonvolatile magnetic element includes: a first free layer made of a ferromagnetic substance; a first insulating layer made of an insulator, the first insulating layer being provided to be connected to the first free layer; a charged layer provided adjacent to the first insulating layer; a second insulating layer made of an insulator, the second insulating layer being provided adjacent to the charged layer; and an injection layer provided adjacent to the second insulating layer. The charged layer is smaller in electric resistivity than both of the first insulating layer and the second insulating layer. The injection layer is smaller in electric resistivity than the second insulating layer.

Abstract: A negative active material for a rechargeable lithium battery including a flake powder including a plurality of flakes, each flake including a plurality of silicon atoms and a plurality of oxygen atoms, wherein an oxygen atom amount for each flake ranges from 5 wt % to 36 wt % based on a total amount of silicon atoms and oxygen atoms, each flake having a thickness ranging from 30 nm to 500 nm and a ratio of an average longest dimension to the thickness ranging from 10 to 100.

Abstract: According to one embodiment, an information recording device includes first and second electrodes, a variable resistance layer between the first and second electrodes, and a control circuit which controls the variable resistance layer to n (n is a natural number except 1) kinds of resistance. The variable resistance layer comprises a material filled between the first and second electrodes, and particles arranged in a first direction from the first electrode to the second electrode in the material, and each of the particles has a resistance lower than that of the material. A resistance of the variable resistance layer is decided by a short between the first electrode and at least one of the particles.

Abstract: A semiconductor device includes a first conductive layer extending in a first direction, a second conductive layer extending in a second direction and disposed over the first conductive layer, the first and second directions being substantially perpendicular to each other, and a variable resistance layer disposed over the first conductive layer, the variable resistance layer extending in the second direction. An upper portion of the variable resistance layer is disposed between lower portions of two neighboring second conductive layers including the second conductive layer.

Abstract: A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.

Abstract: A memristor structure has two electrodes sandwiching an insulating region, and includes a nanoparticle providing a conducting path between the two electrodes, wherein either the insulating region comprises an inorganic material and nanoparticle comprises a solid nanoparticle or a core/shell nanoparticle or the insulating region comprises an inorganic or organic material and the nanoparticle comprises a core/shell nanoparticle.

Abstract: A mid-infrared tunable metamaterial comprises an array of resonators on a semiconductor substrate having a large dependence of dielectric function on carrier concentration and a semiconductor plasma resonance that lies below the operating range, such as indium antimonide. Voltage biasing of the substrate generates a resonance shift in the metamaterial response that is tunable over a broad operating range. The mid-infrared tunable metamaterials have the potential to become the building blocks of chip based active optical devices in mid-infrared ranges, which can be used for many applications, such as thermal imaging, remote sensing, and environmental monitoring.

Abstract: A light emitting device and method for making the same is disclosed. The light-emitting device includes an active layer sandwiched between a p-type semiconductor layer and an n-type semiconductor layer. The active layer emits light when holes from the p-type semiconductor layer combine with electrons from the n-type semiconductor layer therein. The active layer includes a number of sub-layers and has a plurality of pits in which the side surfaces of a plurality of the sub-layers are in contact with the p-type semiconductor material such that holes from the p-type semiconductor material are injected into those sub-layers through the exposed side surfaces without passing through another sub-layer. The pits can be formed by utilizing dislocations in the n-type semiconductor layer and etching the active layer using an etching atmosphere in the same chamber used to deposit the semiconductor layers without removing the partially fabricated device.

Abstract: A resistance change element includes a first conductive layer, a second conductive layer, and a memory layer. The memory layer is provided between the first conductive layer and the second conductive layer. The memory layer is capable of reversibly transitioning between a first state and a second state due to at least one of a voltage and a current supplied via the first conductive layer and the second conductive layer. A resistance of the second state is higher than a resistance of the first state. The memory layer includes niobium oxide. One of a (100) plane, a (010) plane, and a (110) plane of the memory layer is oriented in a stacking direction from the first conductive layer toward the second conductive layer.