Particular Layout Of Complementary Fets With Regard To Each Other Patents (Class 257/206)
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Patent number: 8334579Abstract: An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The integrated circuit device includes a substrate, a diffusion source, and a lightly doped diffusion region in contact with a conductive layer. A junction of the lightly doped diffusion region with the conductive layer forms a Schottky region. An annealing process is performed to form the lightly doped diffusion region. The annealing process causes dopants from the diffusion source (for example, an n-well disposed in the substrate) of the integrated circuit device to diffuse into a region of the substrate, thereby forming the lightly doped diffusion region.Type: GrantFiled: October 7, 2010Date of Patent: December 18, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ping Chun Yeh, Der-Chyang Yeh, Chih-Ping Chao
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Patent number: 8324056Abstract: A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresponding to the active region. The group of channel patterns may protrude from a surface of the active region and may be arranged parallel to each other. A second impurity region may be formed on an upper portion of the group of channel patterns. The gate insulation layer pattern may be formed on the substrate and a sidewall of the group of channel patterns. The gate insulation layer pattern may be spaced apart from an upper face of the group of channel patterns. The gate electrode may contact the gate insulation layer and may enclose a sidewall of the group of channel patterns.Type: GrantFiled: October 7, 2011Date of Patent: December 4, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hoon Son, Jong-Wook Lee, Jong-Hyuk Kang
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Patent number: 8278689Abstract: A memory array including a diffusion layer, a poly layer, a metal one layer, a metal two layer, and a contact. The diffusion layer comprises diffusion lines extending in a first direction. The poly layer comprises poly lines extending in the first direction and being arranged on top of and insulated from the diffusion layer. The metal one layer comprises metal one lines extending in the first direction and being arranged on top of and insulated from the poly layer. The metal two layer comprises a metal two line extending in the first direction and being arranged on top of and insulated from the metal one layer. The contact extends through the poly layer, and connects a metal one line to a diffusion line. A poly line further extends in a second direction to bend around the contact such that a predetermined distance separates the poly lines from the contact.Type: GrantFiled: September 19, 2011Date of Patent: October 2, 2012Assignee: Marvell International Ltd.Inventors: Qiang Tang, Min She, Ken Liao
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Patent number: 8274099Abstract: A semiconductor device includes conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along a second gate electrode track. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.Type: GrantFiled: April 5, 2010Date of Patent: September 25, 2012Assignee: Tela Innovations, Inc.Inventor: Scott T. Becker
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Patent number: 8264007Abstract: A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by one or more non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. The cell also includes a number of interconnect levels formed above the gate electrode level.Type: GrantFiled: October 1, 2009Date of Patent: September 11, 2012Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling
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Patent number: 8264044Abstract: Each of first and second PMOS transistors, and first and second NMOS transistors has a respective diffusion terminal with a direct electrical connection to a common node, and has a respective gate electrode formed from an originating rectangular-shaped layout feature. Centerlines of the originating rectangular-shaped layout features are aligned to be parallel with a first direction. The first PMOS transistor gate electrode is electrically connected to the second NMOS transistor electrode. The second PMOS transistor gate electrode is electrically connected to the first NMOS transistor gate electrode. The first and second PMOS transistors, and the first and second NMOS transistors together define a cross-coupled transistor configuration having commonly oriented gate electrodes formed from respective rectangular-shaped layout features.Type: GrantFiled: April 2, 2010Date of Patent: September 11, 2012Assignee: Tela Innovations, Inc.Inventor: Scott T. Becker
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Patent number: 8264010Abstract: In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry comprises providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each other by an average spacing x in a first region of the first metal layer. The method further comprises elevating a portion of the plurality of bit lines into a second metal layer overlying the first metal layer. The elevated bit lines are separated from each other by an average spacing y in the second metal layer, with y>x. The method further comprises extending a portion of the plurality of bit lines into a second region of the first metal layer. The extended bit lines are separated from each other by an average spacing z in the second region of the first metal layer, with z>x. The method further comprises connecting a bit line in the second metal layer and a bit line in the first metal layer to the sense circuitry.Type: GrantFiled: July 6, 2010Date of Patent: September 11, 2012Assignee: Round Rock Research, LLCInventors: Qiang Tang, Ramin Ghodsi
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Patent number: 8264008Abstract: A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions separated by a central inactive region. The cell layout also includes a gate electrode level layout for the entire cell defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal and minimized across the gate electrode level layout. Linear-shaped layout features within the gate electrode level layout extend over one or more of the p-type and/or n-type diffusion regions to form PMOS and NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight.Type: GrantFiled: October 1, 2009Date of Patent: September 11, 2012Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling
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Patent number: 8264009Abstract: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell. A width of the conductive features in the gate electrode level is less than a wavelength of light used in a photolithography process for their fabrication.Type: GrantFiled: October 1, 2009Date of Patent: September 11, 2012Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling
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Patent number: 8258631Abstract: Provided is a pad layout structure of a semiconductor chip capable of preventing lead-broken problems when packaging the semiconductor chip with a high aspect ratio in a tape carrier package (TCP). In the pad layout structure of the semiconductor chip, a plurality pads are arranged along upper, lower, left and right sides of the semiconductor chip with a high aspect ratio, and a longitudinal width of pads arranged at the left and right sides and a transverse width of pads arranged at both edges of the upper and lower sides are greater than a transverse width of pads arranged at centers of the upper and lower sides.Type: GrantFiled: December 17, 2007Date of Patent: September 4, 2012Assignee: Silicon Works Co., Ltd.Inventors: Dae-Keun Han, Dae-Seong Kim, Joon-Ho Na
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Patent number: 8258550Abstract: A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes. The cell layout also includes a gate electrode level layout defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. The cell layout also includes a number of interconnect level layouts each defined to pattern conductive features within corresponding interconnect levels above the gate electrode level of the cell.Type: GrantFiled: October 1, 2009Date of Patent: September 4, 2012Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling
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Patent number: 8258577Abstract: A CMOS inverter formed with narrowly spaced fins structures including transistors formed on sidewalls of each fin structure. A high-k dielectric material is deposited on the fins to provide mechanical stability to the fins and serve as a gate dielectric material. A mid gap metal gate layer may be formed on the high-k dielectric layer.Type: GrantFiled: June 4, 2009Date of Patent: September 4, 2012Assignee: International Business Machines CorporationInventor: Abhisek Dixit
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Patent number: 8258548Abstract: A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by one or more non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level of the cell. The cell also includes a number of interconnect levels formed above the gate electrode level.Type: GrantFiled: October 1, 2009Date of Patent: September 4, 2012Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling
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Patent number: 8258547Abstract: A restricted layout region includes a diffusion level layout including a number of diffusion region layout shapes that define at least one p-type diffusion region and at least one n-type diffusion region separated by a central inactive region. A gate electrode level layout is defined above the diffusion level layout to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. A number of PMOS transistor devices is equal to a number of NMOS transistor devices in the restricted layout region. The restricted layout region corresponds to an entire gate electrode level of a cell layout.Type: GrantFiled: September 18, 2009Date of Patent: September 4, 2012Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling
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Patent number: 8258551Abstract: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell. The cell also includes a number of interconnect levels formed above the gate electrode level.Type: GrantFiled: October 1, 2009Date of Patent: September 4, 2012Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling
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Patent number: 8258549Abstract: A cell of a semiconductor device includes a substrate portion formed to include at least one p-type diffusion region and at least one n-type diffusion region separated by non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. The cell also includes a number of interconnect levels formed above the gate electrode level.Type: GrantFiled: October 1, 2009Date of Patent: September 4, 2012Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling
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Patent number: 8258552Abstract: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level region. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. A width of the conductive features within a five wavelength photolithographic interaction radius is less than a wavelength of light of 193 nanometers as used in a photolithography process for their fabrication.Type: GrantFiled: October 1, 2009Date of Patent: September 4, 2012Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling
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Patent number: 8258553Abstract: The chip area of a semiconductor device having a plurality of standard cells is to be made smaller. A semiconductor device includes first and second standard cells. The first standard cell includes a diffusion region, a functional device region opposed to the diffusion region, and a metal layer. The second standard cell includes another diffusion region continuous with the diffusion region, another functional device region opposed to the other diffusion region, and further another diffusion region formed between the other diffusion region and the other functional device region. The metal layer and the other functional device region are coupled together electrically through the diffusion regions.Type: GrantFiled: May 5, 2011Date of Patent: September 4, 2012Assignee: Renesas Electronics CorporationInventor: Hiroshi Omura
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Patent number: 8258581Abstract: A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected. However, the first PMOS and second NMOS transistor devices are physically separate within the gate electrode level region. The gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected. However, the second PMOS and first NMOS transistor devices are physically separate within the gate electrode level region.Type: GrantFiled: April 2, 2010Date of Patent: September 4, 2012Assignee: Tela Innovations, Inc.Inventor: Scott T. Becker
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Patent number: 8253173Abstract: A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. A width size of the conductive features within a five wavelength photolithographic interaction radius within the gate electrode level is less than a wavelength of light of 193 nanometers. Some of the conductive features form respective PMOS and/or NMOS transistor devices. The cell includes an equal number of PMOS and NMOS transistor devices. The cell also includes a number of interconnect levels formed above the gate electrode level.Type: GrantFiled: October 1, 2009Date of Patent: August 28, 2012Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling
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Patent number: 8253172Abstract: A cell of a semiconductor device includes a substrate portion including a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated by one or more non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features is fabricated from a respective originating rectangular-shaped layout feature. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level. The cell also includes a number of interconnect levels formed above the gate electrode level.Type: GrantFiled: October 1, 2009Date of Patent: August 28, 2012Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling
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Publication number: 20120205721Abstract: A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit includes a plurality of bit line structures, a plurality of word line structures intersecting said plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at said plurality of cell locations, each of said cells being selectively coupled to a corresponding bit line structure under control of a corresponding word line structure, each of said cells comprising a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor, wherein said at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of said bit line structures, and said at least first p-type field effect transistor is formed with a relatively thin buried oxide layer.Type: ApplicationFiled: April 18, 2012Publication date: August 16, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ching-Te K. Chuang, Fadi H. Gebara, Keunwoo Kim, Jente Benedict Kuang, Hung C. Ngo
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Patent number: 8242541Abstract: A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered.Type: GrantFiled: January 9, 2007Date of Patent: August 14, 2012Assignee: Renesas Electronics CorporationInventors: Takayuki Sasaki, Yasuto Igarashi, Naozumi Morino
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Patent number: 8237203Abstract: A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.Type: GrantFiled: August 5, 2009Date of Patent: August 7, 2012Assignee: Renesas Electronics CorporationInventors: Nobuhiro Tsuda, Hidekatsu Nishimaki, Hiroshi Omura, Yuko Yoshifuku
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Patent number: 8222676Abstract: A transistor and a semiconductor integrated circuit with a reduced layout area. Area reduction of a transistor is realized by arranging contacts at higher density. Specifically, in a transistor including a pair of impurity regions and a gate electrode 604 sandwiched therebetween, one of the impurity regions has respective contact holes (a first contact hole 601 and a second contact hole 602) and the other impurity region has a contact hole (a third contact hole 603), and contacts of the contact holes 601 to 603 or regions 605 to 607 each including a margin for a contact are arranged so as to be a triangular lattice except for the gate electrode 604.Type: GrantFiled: April 5, 2007Date of Patent: July 17, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Kiyoshi Kato
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Patent number: 8217429Abstract: A semiconductor device includes a first well region 3a; a second well region 3b; a first active region 21a surrounded by an isolation region 2; a second active region 21b surrounded by the isolation regions 2 and 2B; a first MIS transistor MP2 of a second conductivity type formed on the first active region 21a; and including a source/drain region formed of a Si mixed crystal layer buried in a recess; a second MIS transistor MN2 of a first conductivity type formed on the second active region 21b; and an isolation MIS transistor DP2 of the second conductivity type formed on the first active region 21a. The source/drain region of the first MIS transistor is not in contact with the isolation region 2 located at an end of the first active region 21a in a gate length direction.Type: GrantFiled: January 19, 2010Date of Patent: July 10, 2012Assignee: Panasonic CorporationInventor: Kyouji Yamashita
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Patent number: 8217427Abstract: A memory circuit includes a plurality of bit line structures, a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells is selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures, and each of the cells in turn includes a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor. The at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of the bit line structures, and the at least first p-type field effect transistor is formed with a relatively thin buried oxide layer.Type: GrantFiled: October 2, 2007Date of Patent: July 10, 2012Assignee: International Business Machines CorporationInventors: Ching-Te K. Chuang, Fadi H. Gebara, Keunwoo Kim, Jente Benedict Kuang, Hung C. Ngo
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Patent number: 8216894Abstract: A finFET structure is made by forming a fin (14), followed by a gate stack of gate dielectric (16), metal gate layer (18), polysilicon layer (20) and silicon-germanium layer (22). The gate stack is then patterned, and source and drain implants formed in the fin (14) away from the gate. The silicon germanium layer (22) is selectively etched away, a metal deposited over the gate, and silicidation carried out to convert the full thickness of the polysilicon layer (20) at the top of the fin. A region of unreacted polysilicon (38) may be left at the base of the fin and across the substrate.Type: GrantFiled: June 10, 2009Date of Patent: July 10, 2012Assignee: NXP B.V.Inventor: Robert J. P. Lander
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Patent number: 8217428Abstract: A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width of the conductive features within the gate electrode level is measured perpendicular to the first parallel direction and is less than a wavelength of light used in a photolithography process to fabricate the conductive features. The cell also includes a number of interconnect levels formed above the gate electrode level.Type: GrantFiled: September 30, 2009Date of Patent: July 10, 2012Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling
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Patent number: 8203173Abstract: A semiconductor integrated circuit has: a substrate; a basic logic cell placed on the substrate and configured to function as a part of a logic circuit; and a dummy cell placed on the substrate and not configured to function as a part of a logic circuit. The basic logic cell includes a diffusion layer formed in the substrate, and a distance from the diffusion layer to a boundary between the basic logic cell and another cell adjacent to the basic logic cell is equal to a first distance. The dummy cell includes a dummy diffusion layer that is a diffusion layer formed in the substrate, and a distance from the dummy diffusion layer to a boundary between the dummy cell and another cell adjacent to the dummy cell is equal to the first distance.Type: GrantFiled: July 7, 2009Date of Patent: June 19, 2012Assignee: Renesas Electronics CorporationInventor: Toshifumi Uemura
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Patent number: 8198654Abstract: A first gate electrode surrounding the periphery of the first gate insulating film, a second gate insulating film surrounding the periphery of the first gate electrode, a first columnar silicon layer surrounding the periphery of the second gate insulating film, a first upper part high concentration semiconductor layer of the first conductivity type formed in the upper part of the first island-shaped silicon layer, a second lower part high concentration semiconductor layer of the first conductivity type formed in the lower part of the first island-shaped silicon layer, a first upper part high concentration semiconductor layer of the second conductivity type formed in the upper part of the first columnar silicon layer, and a second lower part high concentration semiconductor layer of the second conductivity type formed in the lower part of the first columnar silicon layer.Type: GrantFiled: September 15, 2010Date of Patent: June 12, 2012Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 8198656Abstract: A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width size of the conductive features within a five wavelength photolithographic interaction radius within the gate electrode level is less than a wavelength of light of 193 nanometers. The cell also includes a number of interconnect levels formed above the gate electrode level.Type: GrantFiled: September 30, 2009Date of Patent: June 12, 2012Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling
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Patent number: 8198655Abstract: An integrated circuit comprising both memory and logic wherein at least one layer of the integrated circuit is fabricated using a common grating pattern for both memory and logic is described. In one embodiment, the integrated circuit comprises a substrate, an active layer, and a gate material layer such as a polysilicon layer, and the active layer, the gate material layer, or both the active layer and the gate material layer are formed using a common grating pattern for both memory and logic. By using a common grating pattern for both memory and logic, a corresponding layer of the integrated circuit can be reliably and affordably manufactured using sub-wavelength lithography.Type: GrantFiled: April 27, 2009Date of Patent: June 12, 2012Assignee: Carnegie Mellon UniversityInventors: Lawrence T. Pileggi, Daniel Morris
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Patent number: 8187924Abstract: A design method for a semiconductor integrated circuit, includes: a first calculating step; a second calculating step; and a setting step. The first step is a step of calculating a consumption current amount of a layout target circuit based on circuit information. The second calculating step is a step of calculating a suppliable current amount per unit area in a region where a power can be supplied from a power wiring line. The setting step is a step of setting a cell size of the layout target circuit based on the consumption current amount so that a consumption current amount per unit area of the layout target circuit is smaller than the suppliable current amount per unit area.Type: GrantFiled: June 29, 2010Date of Patent: May 29, 2012Assignee: Renesas Electronics CorporationInventors: Yohei Nakajima, Makoto Nonaka
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Patent number: 8188516Abstract: Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.Type: GrantFiled: March 4, 2010Date of Patent: May 29, 2012Assignee: International Business Machines CorporationInventors: Anthony Correale, Jr., Benjamin J. Bowers, Douglass T. Lamb, Nishith Rohatgi
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Patent number: 8188564Abstract: A method for manufacturing a semiconductor device including a thin film device unit including a TFT, and a peripheral device unit provided around the thin film device unit and including a semiconductor element, includes a first step of preparing a substrate, a second step of bonding the peripheral device unit directly to the substrate, and a third step of forming the thin film device unit on the substrate to which the peripheral device unit is bonded.Type: GrantFiled: July 24, 2008Date of Patent: May 29, 2012Assignee: Sharp Kabushiki KaishaInventors: Kazuhide Tomiyasu, Yutaka Takafuji, Yasumori Fukushima, Kazuo Nakagawa
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Patent number: 8183600Abstract: A technique permitting reduction in size of a standard cell is provided. In a semiconductor integrated circuit device comprising a first tap formed in a first direction to supply a power-supply potential, a second tap formed in the first direction to supply a power-supply potential and positioned so as to confront the first tap in a second direction intersecting the first direction, and a standard cell formed between the first and second taps, a cell height (distance) between the center of the first tap and that of the second tap both in the second direction is set to ((an integer+0.5)×a wiring pitch of the second-layer wiring lines) or [(an integer+0.25)×a wiring pitch of the second-layer wiring lines].Type: GrantFiled: December 7, 2009Date of Patent: May 22, 2012Assignee: Renesas Electronics CorporationInventor: Hiroharu Shimizu
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Patent number: 8178904Abstract: A gate array of a semiconductor substrate on which plural unit cells are arranged in parallel, the unit cells having the same pattern that includes a source potential region VDD, a PMOS, an NMOS and a ground potential region GND. Metal wiring lines being formed, with an insulating layer between, on the unit cells, with contacts that make electrical connection between the metal wiring lines and the unit cell transistors. The gate wiring of a transistor in a non-used unit cell is used in place of a metal wiring line. By doing so, the area of metal wiring lines in a gate array is reduced and the array wiring efficiency is increased.Type: GrantFiled: December 10, 2010Date of Patent: May 15, 2012Assignee: Oki Semiconductor Co., Ltd.Inventor: Hirofumi Uchida
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Patent number: 8178902Abstract: A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over the first gate dielectric material. A second gate dielectric material comprising a different material than the first gate dielectric material is deposited over the first region of the workpiece. A second gate material is deposited over the second gate dielectric material. The first gate material, the first gate dielectric material, the second gate material, and the second gate dielectric material are then patterned to form a CMOS device having a symmetric Vt for the PMOS and NMOS FETs.Type: GrantFiled: June 17, 2004Date of Patent: May 15, 2012Assignee: Infineon Technologies AGInventor: Hong-Jyh Li
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Patent number: 8178903Abstract: A semiconductor device in accordance with an exemplary aspect of the present invention includes: an even number of transistor pairs; connection nodes connecting the n-type transistors and the p-type transistors of the transistor pairs; and inter-gate wiring lines connected to the connection nodes, each inter-gate wiring line connecting a gate of the p-type transistor of one of the transistor pairs disposed in the subsequent stage of one of the transistor pairs for which each connection node is provided, wherein the n-type transistor of a first transistor pair is disposed in a p-well region different from both a p-well region in which the n-type transistor of a second transistor pair disposed in two stages preceding of the first transistor pair is disposed and a p-well region in which the n-type transistor of a third transistor pair disposed in two stages subsequent of the first transistor pair is disposed.Type: GrantFiled: October 6, 2009Date of Patent: May 15, 2012Assignee: Renesas Electronics CorporationInventor: Hideyuki Nakamura
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Patent number: 8174052Abstract: A standard cell library includes a first power rail, a second power rail, a third power rail, a first standard cell, and second standard cells. The first power rail extends in a first direction. The second power rail extends in the first direction, and is spaced apart from the first power rail by a predetermined spacing in a second direction perpendicular to the first direction. The third power rail extends in the first direction between the first power rail and the second power rail. The first standard cell has at least one cell having a first cell height, and is arranged between the first power rail and the second power rail. The second standard cells have at least two cells, each having a second cell height, that are in contact with each other in the second direction, and are in contact with the first standard cell in the first direction.Type: GrantFiled: February 23, 2009Date of Patent: May 8, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Ha-Young Kim, Sang-Jin Cheong
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Patent number: 8154055Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor includes a photodiode formed in a substrate structure, first to fourth gate electrodes formed over the substrate structure, spacers formed on both sidewalls of the first to fourth gate electrodes and filled between the third and fourth gate electrodes, a first ion implantation region formed in a portion of the substrate structure below the spacers filled between the third and fourth gate electrodes, and second ion implantation regions formed in portions of the substrate structure exposed between the spacers, the second ion implantation regions having a higher concentration than the first ion implantation region.Type: GrantFiled: April 4, 2007Date of Patent: April 10, 2012Assignee: Intellectual Ventures II LLCInventor: Man-Lyun Ha
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Patent number: 8148754Abstract: The present invention is related to a metal-oxide semiconductor field-effect transistor (MOSFET) having a symmetrical layout such that the resistance between drains and sources is reduced, thereby reducing power dissipation. Drain pads, source pads, and gates are placed on the MOSFET such that the distances between drains, sources, and gates are optimized to reduce resistance and power dissipation. The gates may be arranged in a trapezoidal arrangement in order to maximize a ratio of the gate widths to gate lengths for current driving while reducing resistance and power dissipation.Type: GrantFiled: June 9, 2008Date of Patent: April 3, 2012Assignee: Atmel Rousset S.A.S.Inventors: Maud Pierrel, Bilal Manai
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Patent number: 8138525Abstract: A cell of a semiconductor device includes a substrate portion formed to include at least one p-type diffusion region and at least one n-type diffusion region separated by non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. A width size of the conductive features within a five wavelength photolithographic interaction radius within the gate electrode level is less than a wavelength of light of 193 nanometers. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. The cell also includes a number of interconnect levels formed above the gate electrode level.Type: GrantFiled: October 1, 2009Date of Patent: March 20, 2012Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling
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Patent number: 8134183Abstract: A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent are fabricated from respective originating layout features separated from each other by an end-to-end spacing of substantially equal and minimum size across the gate electrode level region. A width of the conductive features within a 5 wavelength photolithographic interaction radius is less than a 193 nanometer wavelength of light used in a photolithography process for their fabrication. Some conductive features extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the gate electrode level region is greater than or equal to eight.Type: GrantFiled: September 25, 2009Date of Patent: March 13, 2012Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling
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Patent number: 8134185Abstract: A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes, including a p-type and an n-type diffusion region separated by a central inactive region. The layout of the cell includes a gate electrode level layout corresponding to an entire gate level of the cell. The gate electrode layout includes a number of linear-shaped layout features placed to extend in only a first parallel direction. Each of the number of the linear-shaped layout features within the gate electrode level layout of the restricted layout region is rectangular-shaped. Linear-shaped layout features within the gate electrode level layout extend over one or more of the p-type and/or n-type diffusion regions to form PMOS and NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight.Type: GrantFiled: September 25, 2009Date of Patent: March 13, 2012Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling
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Patent number: 8134184Abstract: A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes, including a p-type and an n-type diffusion region separated by a central inactive region. The layout of the cell includes a gate electrode level layout corresponding to an entire gate level of the cell. The gate electrode layout includes a number of linear-shaped layout features placed to extend in only a first parallel direction. Each of the number of the linear-shaped layout features within the gate electrode level layout of the restricted layout region is rectangular-shaped. Linear-shaped layout features within the gate electrode level layout extend over one or more of the p-type and/or n-type diffusion regions to form PMOS and NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell.Type: GrantFiled: September 25, 2009Date of Patent: March 13, 2012Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling
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Patent number: 8134186Abstract: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. The cell also includes a number of interconnect levels formed above the gate electrode level.Type: GrantFiled: October 1, 2009Date of Patent: March 13, 2012Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling
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Patent number: 8129757Abstract: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. A width of the conductive features in the gate electrode level is less than a wavelength of light used in a photolithography process for their fabrication.Type: GrantFiled: October 1, 2009Date of Patent: March 6, 2012Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling
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Patent number: 8129756Abstract: A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication.Type: GrantFiled: October 1, 2009Date of Patent: March 6, 2012Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling