Semiconductor memory device
A semiconductor memory device is constructed to include a memory cell formed by a plurality of transistors, wherein each of gate wiring layers of all of the transistors forming the memory cell is arranged to extend in one direction.
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This application is a divisional of U.S. patent application Ser. No. 10/968,819 filed Oct. 20, 2004, which is a reissue of U.S. Pat. No. 6,469,328, issued Oct. 22, 2002, which claims benefits of Japanese Application Patent No. 10-305888 filed Oct. 27, 1998, the above applications are incorporated by reference herein their entireties.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to a semiconductor memory device such as a static random access memory (SRAM).
In semiconductor memory devices, memory cells occupy a large portion of the device area. Hence, the memory cell is an important factor which determines the size, access speed and power consumption of the semiconductor memory device.
2. Description of the Related Art
First, a description will be given of a memory cell of a conventional 1-read-write/1-read (1RW/1R) RAM.
In
In
When the layout shown in
On the other hand, since the gate polysilicon layer 61 of the transistors Trn3 and Trn4 cannot be arranged in the same direction as gate polysilicon layers 63 and 64 of the other transistors, the 1RW/1R RAM is easily affected by inconsistencies introduced during the production process of the memory cell. In other words, the dimensional accuracies of the gate polysilicon layers 61 and 62 and the gate polysilicon layers 63 and 64 which extend in different directions become different due to the inconsistencies introduced during the production process. For this reason, even if the gate polysilicon layers 61 and 62 are designed to have the same length as the gate polysilicon layers 63 and 64, for example, the actual resistances of the gate polysilicon layers 61 and 62 become different from the actual resistances of the gate polysilicon layers 63 and 64. As a result, the access speed and the power consumption of the memory cell are affected by the different resistances, and the balance of the memory cell as a whole deteriorates. Therefore, it is difficult to guarantee a stable operation of the semiconductor memory device.
As described above, in the conventional semiconductor memory device, there were problems in that it is difficult to reduce the area occupied by the memory cell, and that it is difficult to guarantee a stable operation of the semiconductor memory device due to the effects of the inconsistencies introduced during the production process.
SUMMARY OF THE INVENTIONAccordingly, it is a general object of the present invention to provide a novel and useful semiconductor memory device in which the problems described above are eliminated.
Another and more specific object of the present invention is to provide a semiconductor memory device which can reduce an area occupied by a memory cell and can guarantee a stable operation of the semiconductor memory device by minimizing effects caused by inconsistencies which are introduced during a production process of the semiconductor memory device.
Still another object of the present invention is to provide a semiconductor memory device comprising a memory cell formed by a plurality of transistors, wherein each of gate wiring layers of all of the transistors forming the memory cell is arranged to extend in one direction. According to the semiconductor memory device of the present invention, it is possible to reduce an area occupied by the memory cell, and to guarantee a stable operation of the semiconductor memory device by taking measures so as to be less affected by inconsistencies introduced during a production process of the semiconductor memory device.
Of the transistors forming the memory cell, first transistors which are coupled to word lines may be arranged on an outer side of second transistors which are coupled to a power supply, within the semiconductor memory device. In addition, of the second transistors, a source/drain of a second transistor coupled to the power supply and a substrate contact of the power supply may be used in common. Furthermore, of the second transistors, a source/drain of a second transistor coupled to another power supply which is different from the power supply and a substrate contact of the other power supply may be used in common. According to the semiconductor memory device of the present invention, it is possible to effectively reduce the area occupied by the memory cell by the transistor arrangement and the common use of the contact.
The first transistors and the second transistors which are coupled to the power supply are made of N-channel MOS transistors, and the second transistor which is coupled to the other power supply may be made of a P-channel MOS transistor.
The semiconductor memory device may further comprise signal lines including word lines, and a power line, where the power line is arranged between the signal lines in a single wiring layer. According to the semiconductor memory device of the present invention, it is possible to reduce the coupling capacitance introduced between the signal lines, and prevent generation of noise and inversion (transformation) of data.
A plurality of memory cells may be arranged in an array, an adjacent memory cell may be arranged adjacent to a certain memory cell, and a source/drain of the transistors forming the adjacent memory cell and a bulk layer of a substrate contact may be used in common by reversing a layout of the certain cell with respect to both an x-axis direction and a y-axis direction. In addition, the semiconductor memory device may further comprise power lines, and signal lines, where a plurality of memory cells are arranged in an array, an adjacent memory cell is arranged adjacent to a certain memory cell, and the power lines and the signal lines with respect to the adjacent memory cell are used in common with the certain memory cell by reversing a layout of the certain memory cell with respect to both an x-axis direction and a y-axis direction. According to the semiconductor memory device of the present invention, it is possible to effectively reduce the area occupied by the memory cell array.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
A description will be given of embodiments of the present invention, by referring to FIG. 4 and the subsequent figures.
In this embodiment, the transistors Trn3 and Trn4 which are connected to the word line WLA and the transistors Trn5 and Trn7 which are connected to the word lines WLB are arranged on the outer side of the other transistors in the cell frame, as shown in FIG. 4. More particularly, the transistors Trn4 and Trn5 are arranged in an upper portion in
In other words, the power supply sides VSS (sources 11) of the transistors Trn1; Trn2, Trn6 and Trn8 may be used in common, and by further common use with substrate contacts (contact regions of the P-type wells) 13, it is possible to reduce the number of contacts 14 to the power supply VSS to one. In addition, common sources/drains 21 and 22 may be used with respect to the transistors Trp1 and Trp2. By similarly using the power supply sides VDD (sources 21) of the transistors Trp1 and Trp2 in common, and by further common use with substrate contacts (contact regions of the N-type wells) 23, it is possible to reduce the number of contacts 24 to the power supply VDD to one.
Accordingly, the conventional concept of using a polysilicon layer to connect the gates of the transistors which are connected to the word lines as shown in
The present inventors conducted experiments to compare the layout of this embodiment shown in FIG. 4 and the conventional layout shown in FIG. 2. It was confirmed from the results of the experiments that the area of one memory cell of this embodiment can be reduced by approximately 20% as compared to the area of one conventional memory cell.
As will be described later in conjunction with
As may be seen from
In other words, the gate polysilicon layers of all of the transistors forming the memory cells are arranged to extend in the same direction In addition, the sources/drains of the transistors connected to all of the bit lines are arranged to be used in common among the certain memory cell and the adjacent memory cells located above and below in the plan view. Moreover, the sources/drains of the transistors on the power supply side and the substrate contacts are used in common among the memory cells. Furthermore, the substrate contacts are used in common among the certain memory cell and the adjacent memory cells located on the right and left.
In
As may be seen from
In the embodiments described above, the present invention is applied to the 1RW/1R RAM. However, the application of the present invention is not limited to the 1RW/1R RAM, and the present invention is similarly applicable to various other kinds of semiconductor memory devices.
Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.
Claims
1. A semiconductor memory device comprising:
- a memory cell formed by a plurality of transistors, gate wiring layers of all of the transistors forming said memory cell being arranged to extend in one direction, wherein: of the transistors forming said memory cell, first transistors which are coupled to word lines are arranged on an outer side of second transistors which are coupled to a power supply, within the memory cell, and
- the gate wiring layers of at least two of said second transistors which are coupled to the power supply are connected to each other,
- a plurality of power lines, a first one of which running within the memory cell, two word lines running on both sides of the first power line,
- a second power line intersecting the first power line,
- and two bit line pairs running on both sides of the second power line; and
- wherein a plurality of memory cells are arranged in an array, an adjacent memory cell is arranged adjacent to a certain memory cell, and a source/drain of the transistor, forming said adjacent memory cell and a bulk layer of a substrate contact are used in common by reversing a layout of said certain cell with respect to both an x-axis direction and a y-axis direction.
2. The semiconductor memory device as claimed in claim 1, wherein: of said second transistors, a source/drain of a second transistor coupled to the power supply and a substrate contact of the power supply are used in common.
3. The semiconductor memory device as claimed in claim 1, wherein: of said second transistors, a source/drain of a second transistor coupled to another power supply which is different from said power supply and a substrate contact of the other power supply are used in common.
4. The semiconductor memory device as claimed in claim 3, wherein said first transistors and said second transistors which are coupled to said power supply are made of N-channel MOS transistors, and said second transistor which is coupled to said other power supply is made of a P-channel MOS transistor.
5. The semiconductor memory device as claimed in claim 1, which further comprises:
- signal lines including word lines; and
- wherein said power lines are arranged between said signal lines in a single wiring layer.
6. A semiconductor memory device comprising:
- a memory cell formed by a plurality of transistors,
- gate wiring layers of all of the transistors forming said memory cell being arranged to extend in one direction, wherein: of the transistors forming said memory cell, first transistors which are coupled to word lines are arranged on an outer side of second transistors which are coupled to a power supply, within the memory cell,
- the gate wiring layers of at least two of said second transistors which are coupled to the power supply are connected to each other,
- a plurality of power lines, a first one of which running within the memory cell,
- a plurality of signal lines,
- two word lines running on both sides of the first power line,
- a second power line intersecting the first power line,
- two bit line pairs running on both sides of the second power lines;
- a plurality of memory cells being arranged in an array, and
- an adjacent memory cell being arranged adjacent to a certain memory cell,
- said power lines and said signal lines with respect to said adjacent memory cell are used in common with said certain memory cell by reversing a layout of said certain memory cell with respect to both an x-axis direction and a y-axis direction.
7. The semiconductor memory device as claimed in claim 1, wherein said plurality of memory cells arranged in an array, said adjacent memory cell arranged adjacent to a certain memory cell, and said source/drain of the transistors forming said adjacent memory cell and said bulk layer of a substrate contact are used in common on all four adjacent sides by reversing a layout of said certain cell with respect to both an x-axis direction and a y-axis direction.
8. The semiconductor memory device as claimed in claim 1, wherein
- said plurality of memory cells arranged in an array,
- said adjacent memory cell arranged adjacent to a certain memory cell, and
- said power lines with respect to said adjacent memory cell are used in common with said certain memory cell by reversing a layout of said certain memory cell with respect to an x-axis direction.
9. The semiconductor memory device as claimed in claim 6, wherein: of said second transistors, a source/drain of a second transistor coupled to the power supply and a substrate contact of the power supply are used in common.
10. The semiconductor memory device as claimed in claim 6, wherein: of said second transistors, a source/drain of a second transistor coupled to another power supply which is different from said power supply and a substrate contact of the other power supply are used in common.
11. The semiconductor memory device as claimed in claim 10, wherein said first transistors and said second transistors which are coupled to said power supply are made of N-channel MOS transistors, and said second transistor which is coupled to said other power supply is made of a P-channel MOS transistor.
12. The semiconductor memory device as claimed in claim 6, wherein
- said signal lines include word lines; and
- said power lines are arranged between said signal lines in a single wiring layer.
13. The semiconductor memory device as claimed in claim 6, wherein said plurality of memory cells arranged in an array, said adjacent memory cell arranged adjacent to a certain memory cell, and a source/drain of the transistor forming said adjacent memory cell and a bulk layer of a substrate contact are used in common on all four adjacent sides by reversing a layout of said certain cell with respect to both an x-axis direction and a y-axis direction.
14. The semiconductor memory device as claimed in claim 6, wherein said plurality of memory cells arranged in an array,
- said adjacent memory cell arranged adjacent to a certain memory cell, and
- said power lines with respect to said adjacent memory cell are used in common with said certain memory cell by reversing a layout of said certain memory cell with respect to an x-axis direction.
15. A semiconductor device comprising:
- a plurality of SRAM memory cells each formed by first and second P-channel transistors and first through fourth N-channel transistors;
- first and second bit lines;
- a word line;
- first and second power lines;
- a first wiring layer forming a gate of the first P-channel transistor and a gate of the first N-channel transistor;
- a second wiring layer forming a gate of the second P-channel transistor and a gate of the second N-channel transistor;
- a third wiring layer forming a gate of the third N-channel transistor that is coupled to the word line; and
- a fourth wiring layer forming a gate of the fourth N-channel transistor that is coupled to the word line,
- said first through fourth wiring layers extending linearly and in parallel along an x-axis direction,
- each of the first and second P-channel transistors having a source/drain with a first contact that couples to the first power line;
- each of the first and second N-channel transistors having a source/drain with a second contact that couples to the second power line,
- the third N-channel transistor having a source/drain with a third contact that couples to the first bit line,
- the fourth N-channel transistor having a source/drain with a fourth contact that couples to the second bit line,
- said first through fourth contacts being used in common by adjacent memory cells,
- each of the first and second power lines being arranged between the first and second bit lines such that the first and second power lines and the first and second bit lines are mutually parallel,
- said word line being disposed above the first through fourth wiring layers and extending in the x-axis direction,
- each of the first and second power lines and the first and second bit lines being disposed above the word line and extending in a y-axis direction that is perpendicular to the x-axis direction,
- the adjacent memory cells having layouts that are reversed in the x-axis direction or the y-axis direction.
16. A semiconductor device comprising:
- a plurality of SRAM memory cells each formed by first and second P-channel transistors and first through fourth N-channel transistors;
- first and second bit lines;
- a word line;
- first and second power lines;
- a first wiring layer forming a gate of the first P-channel transistor and a gate of the first N-channel transistor;
- a second wiring layer forming a gate of the second P-channel transistor and a gate of the second N-channel transistor;
- a third wiring layer forming a gate of the third N-channel transistor; and
- a fourth wiring layer forming a gate of the fourth N-channel transistor,
- said first through fourth wiring layers extending linearly and in parallel along an x-axis direction,
- said third and fourth wiring layers being coupled to the word line,
- each of the first and second P-channel transistors having a source/drain with a first contact that couples to the first power line;
- each of the first and second N-channel transistors having a source/drain with a second contact that couples to the second power line,
- the third N-channel transistor having a source/drain with a third contact that couples to the first bit line,
- the fourth N-channel transistor having a source/drain with a fourth contact that couples to the second bit line,
- said first through fourth contacts being used in common by adjacent memory cells,
- each of the first and second power lines being arranged between the first and second bit lines such that the first and second power lines and the first and second bit lines are mutually parallel,
- said word line being disposed above the first through fourth wiring layers and extending in the x-axis direction,
- each of the first and second power lines and the first and second bit lines being disposed above the word line and extending in a y-axis direction that is perpendicular to the x-axis direction,
- the adjacent memory cells having layouts that are reversed in the x-axis direction or the y-axis direction.
17. A semiconductor device comprising:
- a plurality of SRAM memory cells each formed by first and second P-channel transistors and first through fourth N-channel transistors;
- first and second bit lines;
- a word line;
- first and second power lines;
- a first wiring layer forming a gate of the first P-channel transistor and a gate of the first N-channel transistor;
- a second wiring layer forming a gate of the second P-channel transistor and a gate of the second N-channel transistor;
- a third wiring layer forming a gate of the third N-channel transistor; and
- a fourth wiring layer forming a gate of the fourth N-channel transistor,
- said first through fourth wiring layers extending linearly and in parallel along an x-axis direction,
- said third and fourth wiring layers being extending linearly to adjacent memory cells that are adjacent to each other along the x-axis direction and being used in common by the adjacent memory cells that are adjacent to each other along the x-axis direction,
- said third N-channel transistor having a source/drain which is used in common as a first bit line contact by adjacent memory cells that are adjacent to each other along a y-axis direction that is perpendicular to the x-axis direction,
- said fourth N-channel transistor having a source/drain which is used in common as a second bit line contact by the adjacent memory cells that are adjacent to each other along the y-axis direction,
- said third and fourth wiring layers being coupled to word line,
- each of the first and second power lines being arranged between the first and second bit lines such that the first and second power lines and the first and second bit lines are mutually parallel,
- said word line being disposed above the first through fourth wiring layers and extending in the x-axis direction,
- each of the first and second power lines and the first and second bit lines being disposed above the word line and extending in the y-axis direction,
- the adjacent memory cells having layouts that are reversed in the x-axis direction or the y-axis direction.
18. The semiconductor device as claimed in claim 17, wherein each of the first and second P-channel transistors has a source/drain with a first contact that couples to the first power line, and each of the first and second N-channel transistors has a source/drain with a second contact that couples to the second power line.
19. The semiconductor device as claimed in claim 18, wherein each of the first and second contacts is used in common by adjacent memory cells.
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Type: Grant
Filed: Apr 4, 2008
Date of Patent: Nov 30, 2010
Assignee: Fujitsu Semiconductor Limited (Yokohama)
Inventors: Tsuyoshi Yanai (Kawasaki), Yoshio Kajii (Kawasaki), Takashi Ohkawa (Kawasaki)
Primary Examiner: Eugene Lee
Application Number: 12/078,739
International Classification: H01L 27/10 (20060101);