Programmable Signal Paths (e.g., With Fuse Elements, Laser Programmable, Etc) Patents (Class 257/209)
  • Patent number: 10730294
    Abstract: A liquid-discharge-head substrate includes a first covering portion covering a first heating resistance element and having electrical conductivity, a second covering portion covering a second heating resistance element and having electrical conductivity, a fuse, and a common wiring line for electrically connecting the first and second covering portions. The common wiring line is electrically connected with the first covering portion via the fuse. The common wiring line and the fuse each have a multilayer structure including a stack of a plurality of conductive layers including a first conductive layer and a second conductive layer that is less oxidizable than the first conductive layer.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: August 4, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tsubasa Funabashi, Takahiro Matsui, Yoshinori Misumi, Maki Kato, Yuzuru Ishida
  • Patent number: 10734391
    Abstract: A first contact hole is formed so as to extend to a NiSi layer as a lower wiring conductor layer connecting to an N+ layer of an SGT formed within a Si pillar, and so as to extend through a NiSi layer as an upper wiring conductor layer connecting to a gate TiN layer, and a NiSi layer as an intermediate wiring conductor layer connecting to an N+ layer. A second contact hole is formed so as to extend to the NiSi layer, and surround, in plan view, the first contact hole. An insulating SiO2 layer is formed on a side surface of the NiSi layer. A wiring metal layer in the contact holes connects the NiSi layer and the NiSi layer to each other.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: August 4, 2020
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Patent number: 10672651
    Abstract: A structure and a formation method of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive feature over the semiconductor substrate. The semiconductor device structure also includes a dielectric layer over the conductive feature and the semiconductor substrate and a via hole in the dielectric layer. The via hole has an oval cross section. The semiconductor device structure further includes a trench in the dielectric layer, and the via hole extends from a bottom portion of the trench. The trench has a trench width wider than a hole width of the via hole. In addition, the semiconductor device structure includes one or more conductive materials filling the via hole and the trench and electrically connected to the conductive feature.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-Yen Peng, Jyu-Horng Shieh
  • Patent number: 10666265
    Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Kevin Clark, Scott J. Weber, James Ball, Simon Chong, Ravi Prakash Gutala, Aravind Raghavendra Dasu, Jun Pin Tan
  • Patent number: 10656885
    Abstract: The present disclosure is directed to a method of creating an object flow integrity (OFI) library module, capable of redirecting an object-like programmatic call, by initiating a multi-pass, recursive process to analyze a module's interfaces, function parameters, and data types. In another aspect, a method is disclosed to modify the binary code of an untrusted module to enable its usage of the OFI library module. In another aspect, during runtime operations of an untrusted module, the OFI library module can receive an object from a caller module, substitute a proxy object, stored in a secure location, and continue the programmatic call using the proxy object.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: May 19, 2020
    Assignee: Board of Regents, The University of Texas System
    Inventor: Kevin W. Hamlen
  • Patent number: 10629738
    Abstract: An integrated circuit and a code generating method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: April 21, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Hiroshi Watanabe
  • Patent number: 10615120
    Abstract: Provided is a semiconductor device including a fuse element arranged on an interlayer insulating film formed on a semiconductor substrate. The fuse element is formed of polysilicon and a silicide region arranged on an upper surface of the polysilicon. A region of the polysilicon included in a range to be irradiated with a laser beam in plan view is non-doped polysilicon into which impurities are not introduced. With this structure, it is possible to provide the semiconductor device including the fuse element, which can be stably cut with a laser beam while an underlying film is not damaged.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: April 7, 2020
    Assignee: ABLIC INC.
    Inventor: Yuichiro Kitajima
  • Patent number: 10593682
    Abstract: A method for producing a semiconductor memory device includes forming two Si pillars on a substrate. In the Si pillars, inverter circuits are formed. The inverter circuits include drive N-channel SGTs each including first and second N+ layers functioning as a source and a drain, and load SGTs each including first and second P+ layers functioning as a source and drain. Selection SGTs each including third and fourth N+ layers functioning as a source and a drain are formed above SiO2 layers disposed above the inverter circuits. The first N+ layer is connected to a ground wiring metal layer. The first P+ layers are connected to a power supply wiring metal layer through a NiSi layer. Gate TiN layers are connected to a word-line wiring metal layer through a NiSi layer. The third N+ layers are connected to an inverted bit-line wiring metal layer and a bit-line wiring metal layer.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: March 17, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Patent number: 10580780
    Abstract: Provided is a semiconductor structure including a substrate, an isolation structure, a fuse and two gate electrodes. The isolation structure is located in the substrate and defines active regions of the substrate. The fuse is disposed on the isolation structure. The gate electrodes are disposed on the active regions and connected to ends of the fuse. In an embodiment, a portion of a bottom surface of the fuse is lower than top surfaces of the active regions of the substrate.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: March 3, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Zi-Jun Liu, Ping-Chia Shih, Chi-Cheng Huang, Kuo-Lung Li, Hung-Wei Lin, An-Hsiu Cheng, Chih-Hao Pan, Cheng-Hua Chou, Chih-Hung Wang
  • Patent number: 10573596
    Abstract: A semiconductor structure is provided in which metal semiconductor alloy pillars are formed at least partially within the sidewall surfaces of each semiconductor fin that extends from a surface of a substrate. These pillars are fuses (i.e., FinFET fuses) that are formed at a very tight pitch dimensions. The pillars can be trimmed after forming FinFET devices. The present application provides a method for forming on-chip FinFET fuses easily by choice of the metal semiconductor alloy, the amount of pillar trim, the number of contacted pillars and to a lower design degree the height of each pillar.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Oscar van der Straten, Praneet Adusumilli, Bahman Hekmatshoartabari
  • Patent number: 10503402
    Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: December 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel G. Berger, Troy L. Graves-Abe, Subramanian S. Iyer, Toshiaki Kirihata, Arvind Kumar, Winfried W. Wilcke
  • Patent number: 10490479
    Abstract: A semiconductor package includes an integrated circuit (IC), a heat dissipation structure, a molding layer and an antenna. The IC is mounted on a first surface of a first redistribution layer (RDL). The heat dissipation structure is mounted on a second surface of the first RDL. The molding compound is disposed over the first surface of the first RDL. The antenna is disposed on the second surface of the first RDL, wherein the antenna is disposed side-by-side to the heat dissipation structure.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Chao-Wen Shih, Han-Ping Pu, Hsin-Yu Pan, Sen-Kuei Hsu
  • Patent number: 10461073
    Abstract: A power module includes a first MOS transistor and a first Schottky barrier diode for a lower arm, and a second MOS transistor and a second Schottky barrier diode for an upper arm. In one embodiment, one positive-side power supply terminal and one negative-side power supply terminal are provided, while an output terminal to which the first and second MOS transistors are connected and an output terminal to which the first and second Schottky barrier diodes are connected are provided as separate output terminals.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: October 29, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Seiya Sugimachi, Masataka Shiramizu
  • Patent number: 10461028
    Abstract: A vertical OTP fuse formed in a semiconductor device has a substrate and an insulating layer formed over the substrate with an opening through the insulating layer extending to the substrate. A conductive layer, such as silicide, is formed over a sidewall of the opening. A resistive material, such as polysilicon, is deposited within the opening over the first conductive layer to form a first vertical OTP fuse. A plurality of vertical OTP fuses can be arranged in an array. A PN junction diode or transistor is formed in the substrate aligned with the first vertical OTP fuse. A second conductive layer is formed over the first vertical OTP fuse. The first vertical OTP fuse can be disposed between the second conductive layer and a third conductive layer. A second vertical OTP fuse can be formed over the first vertical OTP fuse for redundancy.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: October 29, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jefferson W. Hall, Gordon M. Grivna
  • Patent number: 10438956
    Abstract: A method for integrating vertical transistors and electric fuses includes forming fins through a dielectric layer and a dummy gate stack on a substrate; thinning top portions of the fins by an etch process; epitaxially growing top source/drain regions on thinned portions of the fins in a transistor region and top cathode/anode regions on the thinned portions of the fins in a fuse region; and removing the dummy gate layer and exposing sidewalls of the fins. The fuse region is blocked to form a gate structure in the transistor region. The transistor region is blocked and the fuse region is exposed to conformally deposit a metal on exposed sidewalls of the fins. The metal is annealed to form silicided fins. Portions of the substrate are separated to form bottom source/drain regions for vertical transistors in the transistor region and bottom cathode/anode regions for fuses in the fuse region.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Michael A. Guillorn, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10283567
    Abstract: A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and conductive oxide material layer, forming a first barrier material layer between the word line and the nonvolatile memory material, forming a second barrier material layer between the bit line and the nonvolatile memory material, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: May 7, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Juan Saenz, Deepak Kamalanathan, Guangle Zhou, Ming-Che Wu, Tanmay Kumar
  • Patent number: 10269809
    Abstract: An SRAM includes two Si pillars on a substrate. In the Si pillars, inverter circuits are formed. The inverter circuits include drive N-channel SGTs each including first and second N+ layers functioning as a source and a drain, and load SGTs each including first and second P+ layers functioning as a source and a drain. Selection SGTs each including third and fourth N+ layers functioning as a source and a drain are formed above SiO2 layers disposed above the inverter circuits. The first N+ layer is connected to a ground wiring metal layer. The first P+ layers are connected to a power supply wiring metal layer through a NiSi layer. Gate TiN layers are connected to a word-line wiring metal layer through a NiSi layer. The third N+ layers are connected to an inverted bit-line wiring metal layer and a bit-line wiring metal layer.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: April 23, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Patent number: 10256190
    Abstract: A variable resistance memory device includes different variable resistance patterns on different memory regions of a substrate. The different variable resistance patterns may be at different heights from the substrate and may have different intrinsic properties. The different variable resistance patterns may at least partially comprise separate memory cells that are each configured to function as a non-volatile memory cell or a random access memory cell, respectively.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: April 9, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongkyu Lee, Gwanhyeob Koh, Boyoung Seo
  • Patent number: 10242990
    Abstract: After forming a first functional gate stack located on a first body region of a first semiconductor material portion located in a first region of a substrate and a second functional gate stack located on a second body region of a second semiconductor material portion located in a second region of the substrate, a ferroelectric gate interconnect structure is formed connecting the first functional gate stack and the second functional gate stack. The ferroelectric gate interconnect structure includes a U-shaped bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10217865
    Abstract: A first contact hole is formed so as to extend to a NiSi layer as a lower wiring conductor layer connecting to an N+ layer of an SGT formed within a Si pillar, and so as to extend through a NiSi layer as an upper wiring conductor layer connecting to a gate TiN layer, and a NiSi layer as an intermediate wiring conductor layer connecting to an N+ layer. A second contact hole is formed so as to extend to the NiSi layer, and surround, in plan view, the first contact hole. An insulating SiO2 layer is formed on a side surface of the NiSi layer. A wiring metal layer in the contact holes connects the NiSi layer and the NiSi layer to each other.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: February 26, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Patent number: 10181713
    Abstract: At least one method, apparatus and system disclosed herein involves providing an integrated circuit device comprising a protection circuit. And integrated circuit device is formed. A protection component is formed in parallel to the integrated circuit device. The protection component is configured for protecting the integrated circuit device from a portion of a charge. A circuit break device in series to the protection component, wherein the protection component and the circuit break device are in parallel to the integrated circuit device. The circuit break device is configured to break an electrical path of the protection component for electrically terminating the protection component based upon a current signal.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: January 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Arnaud Bousquet, Geetha Sai Aluri, Suresh Uppal
  • Patent number: 10163783
    Abstract: An integrated circuit structure includes a first fuse line formed in a first metal layer; a second fuse line formed in the first metal layer; a first pair of fuse wings formed in the first metal layer on opposite sides of a first end of the first fuse line; a second pair of fuse wings formed in the first metal layer on opposites sides of a first end of the second fuse line; a third pair of fuse wings formed in the first metal layer on opposite sides of a second end of the first fuse line; and a fourth pair of fuse wings formed in the first metal layer on opposites sides of a second end of the second fuse line. The first and second pairs of fuse wings share a first common fuse wing and the third and fourth pairs of wings share a second common fuse wing.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Sheng Chang, Shao-Tung Peng, Shao-Yu Chou, Liang Chuan Chang, Yao-Jen Yang
  • Patent number: 10128256
    Abstract: A one-time programming cell includes a first metal oxide semiconductor (MOS) structure and a second transistor having a common gate electrode electrically connected to a word line. The first MOS structure has a first gate dielectric layer and the second MOS structure has a second gate dielectric layer. The second gate dielectric layer is thicker than the first gate dielectric layer. Source nodes of the first MOS structure and the second MOS structure are electrically connected, and a drain node of the second MOS structure is electrically connected to a bit line.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: November 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10109654
    Abstract: A manufacturing method of a display substrate, a display substrate and a display device are provided. The manufacturing method of a display substrate including: forming a first metal pattern forming a first insulation layer; forming a second metal pattern; forming a second insulation layer forming a first conductive layer; patterning the first conductive layer to form a first conductive pattern; patterning the second insulation layer to form a second insulation pattern; wherein, an orthographic projection of the first conductive pattern on the base substrate and an orthographic projection of the second metal pattern on the base substrate have an overlapping part; and during patterning the second insulation layer, an orthographic projection of the first conductive pattern on the base substrate at least covers the overlapping part.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: October 23, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Seungjin Choi
  • Patent number: 10068983
    Abstract: An integrated circuit containing metal replacement gates may be formed by forming a nitrogen-rich titanium-based barrier between a high-k gate dielectric layer and a metal work function layer of a PMOS transistor. The nitrogen-rich titanium-based barrier is less than 1 nanometer thick and has an atomic ratio of titanium to nitrogen of less than 43:57. The nitrogen-rich titanium-based barrier may be formed by forming a titanium based layer over the gate dielectric layer and subsequently adding nitrogen to the titanium based layer. The metal work function layer is formed over the nitrogen-rich titanium-based barrier.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: September 4, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATION
    Inventors: Hiroaki Niimi, James Joseph Chambers
  • Patent number: 10056331
    Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey P. Jacob, Suraj K. Patil, Min-hwa Chi
  • Patent number: 10026714
    Abstract: Aspects of the invention relate to an integrated circuit device and method of production thereof. The integrated circuit device comprises at least one application semiconductor die comprising at least one functional component arranged to provide application functionality, at least one functional safety semiconductor die comprising at least one component arranged to provide at least one functional safety undertaking for the at least one application semiconductor die, and at least one System in Package, SiP, connection component operably coupling the at least one functional safety semiconductor die to the at least one application semiconductor die to enable the at least one functional safety semiconductor die to provide the at least one functional safety undertaking for the at least one application semiconductor die.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: July 17, 2018
    Assignee: NXP USA, Inc.
    Inventors: Robert Moran, Derek Beattie
  • Patent number: 10020365
    Abstract: In accordance with an example embodiment of the present invention, a device comprising one or more porous graphene layers, the or each graphene porous layer comprising a multiplicity of pores. The device may form at least part of a flexible and/or stretchable, and or transparent electronic device.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: July 10, 2018
    Assignee: Nokia Technologies Oy
    Inventors: Asta Maria Karkkainen, Samiul Md Haque, Alan Colli, Pirjo Marjaana Pasanen, Leo Mikko Karkkainen, Mikko Aleksi Uusitalo, Reijo Kalervo Lehtiniemi
  • Patent number: 10020256
    Abstract: A structure including a dual damascene feature in a dielectric layer, the dual damascene feature including a first via, a second via, and a trench, the first via, the second via being filled with a conductive material, a fuse line at the bottom of the trench on top of the first via and the second via, the fuse line including the conductive material; an insulating layer on top of the fuse line and along a sidewall of the trench, and a fill material on top of the insulating layer and substantially filling the trench.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: July 10, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chad M. Burke, Baozhen Li, Keith Kwong Hon Wong, Chih-Chao Yang
  • Patent number: 10008541
    Abstract: A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: June 26, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy
  • Patent number: 9941303
    Abstract: The present application provides an array substrate, a display panel and a display device. The array substrate includes: a substrate; gate lines and data lines located on the substrate, intersecting and insulated from each other, which define a plurality of sub-pixel areas; the sub-pixel areas each comprises: a thin-film transistor; a pixel electrode, a barrier metal electrode. An orthographic projection of the drain electrode on the substrate is located between orthographic projections of two adjacent data lines on the substrate, an orthographic projection of the barrier metal electrode on the substrate is located between the orthographic projection of the drain electrode on the substrate and the orthographic projection of at least one of the two adjacent data lines on the substrate.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: April 10, 2018
    Assignee: XIAMEN TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventor: Hongbo Zhou
  • Patent number: 9899351
    Abstract: A semiconductor package includes a package substrate. A first semiconductor chip is mounted on the package substrate. The first semiconductor chip includes a first chip region and first chip pads formed on a top surface of the first chip region. A second semiconductor chip is mounted on the package substrate. The second semiconductor chip includes a second chip region and second chip pads formed on a top surface of the second chip region. A boundary region having a groove divides the first chip region and the second chip region. The first chip region, the second chip region and the boundary region share a semiconductor substrate of a one-body type.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: February 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Museob Shin
  • Patent number: 9859891
    Abstract: A MOS device may include a first logic component with a first input located on a second track and a first output located on the third track. The MOS device may include a second logic component with a second input located on the fourth track and a second output located on a fifth track. For example, the MOS device includes a first interconnect on a Mx layer that is coupled to the first input on the second track. In another example, the MOS device includes a second interconnect on the Mx layer that is coupled to the first output on the third track. The MOS device includes a third interconnect on a My layer that is coupled to the second input on the fourth track. Still further, the MOS device includes a fourth interconnect on the My layer that is coupled to the second output on the fifth track.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: January 2, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Dorav Kumar, Venkatasubramanian Narayanan, Bala Krishna Thalla, Seid Hadi Rasouli, Radhika Vinayak Guttal, Sivakumar Paturi
  • Patent number: 9831175
    Abstract: Methods, apparatus, and systems for fabricating and using a semiconductor device comprising a first conductive element; a second conductive element; and an e-fuse comprising a first region comprising a conductive oxide of a first metal; and a second region comprising a second metal, wherein an oxide of the second metal is resistive; wherein the e-fuse is electrically connected to both the first conductive element and the second conductive element.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: November 28, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Suraj Kumar Patil, Min-Hwa Chi
  • Patent number: 9811585
    Abstract: The invention relates to forming a prediction using an experience matrix, a matrix based on sparse vectors such as random index vectors. At least a part of a first experience matrix and at least a part of at least a second experience matrix are caused to be combined (1410) to obtain a combined experience matrix. The experience matrices comprise sparse vectors or essentially similar vectors in nature, and said experience matrices comprise information of at least one system, for example contexts of a system. At least a part of at least one sparse vector of the combined experience matrix is accessed to form a prediction output (1420), and a system is controlled (1430) in response to said prediction output.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: November 7, 2017
    Assignee: Nokia Technologies Oy
    Inventors: Minna Hellstrom, Mikko Lonnfors, Eki Monni, Istvan Beszteri, Mikko Terho, Leo Karkkainen
  • Patent number: 9767915
    Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors with at least one heat sink or heater to assist programming for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The heat sink can be at least one thin oxide area, extended OTP element area, or other conductors coupled to the OTP element to assist programming. A heater can be at least one high resistance area such as an unsilicided polysilicon, unsilicided active region, contact, via, or combined in serial, or interconnect to generate heat to assist programming. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: September 19, 2017
    Assignee: Attopsemi Technology Co., LTD
    Inventor: Shine C. Chung
  • Patent number: 9754876
    Abstract: A semiconductor device including: a fuse element; and a fuse window that is formed above a region including the fuse element, that includes a pair of first sidewalls extending in a first direction running along a direction that current flows in the fuse element and a pair of second sidewalls extending in a second direction intersecting the first direction, and that is formed with a projection projecting out from a sidewall side toward the inside at an inner wall of at least one out of the first sidewalls or the second sidewalls, the projection having a sidewall side width that is narrower than a projecting side width.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: September 5, 2017
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Kenichirou Kusano
  • Patent number: 9754875
    Abstract: On-chip, doped semiconductor fuse regions compatible with FinFET CMOS fabrication are formed from the channel regions of selected fins. One or more fin dimensions are optionally reduced in selected channel regions of the fins following dummy gate removal, such as height and/or width. The channel regions from which the fuse regions are formed are doped to provide electrical conductivity, amorphized using ion implantation, and then annealed to form substantially polycrystalline fuse regions. Source/drain regions function as terminals for the fuse regions.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: September 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Pouya Hashemi, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 9748201
    Abstract: A semiconductor package may include a first semiconductor chip, second semiconductor chips disposed to respectively overlap with portions of the first semiconductor chip, a interposer disposed to overlap with a portion of the first semiconductor chip, and a package substrate disposed on backside surfaces of the second semiconductor chips opposite to the first semiconductor chip. The interposer may be disposed between the first semiconductor chip and the package substrate. First conductive coupling members connect the first semiconductor chip to the second semiconductor chips. Second conductive coupling members connect the first semiconductor chip to the interposer. Third conductive coupling members connect the interposer to the package substrate.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: August 29, 2017
    Assignee: SK hynix Inc.
    Inventor: Jong Hoon Kim
  • Patent number: 9735354
    Abstract: A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: August 15, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Agostino Pirovano, Umberto Maria Meotto, Giorgio Servalli
  • Patent number: 9728542
    Abstract: A method for integrating vertical transistors and electric fuses includes forming fins through a dielectric layer and a dummy gate stack on a substrate; thinning top portions of the fins by an etch process; epitaxially growing top source/drain regions on thinned portions of the fins in a transistor region and top cathode/anode regions on the thinned portions of the fins in a fuse region; and removing the dummy gate layer and exposing sidewalls of the fins. The fuse region is blocked to form a gate structure in the transistor region. The transistor region is blocked and the fuse region is exposed to conformally deposit a metal on exposed sidewalls of the fins. The metal is annealed to form silicided fins. Portions of the substrate are separated to form bottom source/drain regions for vertical transistors in the transistor region and bottom cathode/anode regions for fuses in the fuse region.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: August 8, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Michael A. Guillorn, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9698098
    Abstract: A method for manufacturing a semiconductor device includes forming a fin extending between first and second pads on a substrate, removing a central portion of the fin to create an opening between a first part of the fin extending from the first pad and a second part of the fin extending from the second pad, growing first and second epitaxial layers in the opening on a side of respective first and second parts of the fin, stopping the growth of the first and second epitaxial layers prior to merging, forming a silicide layer on the first and second pads, first and second parts of the fin and first and second epitaxial layers, wherein there is a gap between portions of the silicide layer on the first and second epitaxial layers in the opening, and depositing a dielectric layer on the silicide layer, filling in the gap.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: July 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hong He, Juntao Li, Junli Wang, Chih-Chao Yang
  • Patent number: 9679845
    Abstract: Interconnect fuse structures including a fuse with a necked line segment, as well as methods of fabricating such structures. A current driven by an applied fuse programming voltage may open necked fuse segments to affect operation of an IC. In embodiments, the fuse structure includes a pair of neighboring interconnect lines equidistant from a center interconnect line. In further embodiments, the center interconnect line, and at least one of the neighboring interconnect lines, include line segments of lateral widths that differ by a same, and complementary amount. In further embodiments, the center interconnect line is interconnected at opposite ends of a necked line segment. In further embodiments, the necked line segment is fabricated with pitch-reducing spacer-based patterning process.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: June 13, 2017
    Assignee: Intel Corporation
    Inventors: Zhanping Chen, Andrew W. Yeoh, Seongtae Jeong, Uddalak Bhattacharya, Charles H. Wallace
  • Patent number: 9672263
    Abstract: Exemplary practice of the present invention provides an electronic system for integrating information from various network sources. The inventive system includes a server computer and at least one client computer (e.g., tablet). According to the software logic resident in the server computer, information is transmitted from various online resources (e.g., web-accessible collections of data) to an enterprise service bus (ESB), and the ESB collates some or all of the information received and stores the collated information in a network database. According to the software logic resident in each client computer, the collated information stored in the network database is downloaded onto an online webpage, parsed, stored in a local database, synched, and downloaded onto an offline webpage. A client can direct the server to collate a particular segment of information, thus affording the client offline access to pertinent, well-organized information on a portable, wireless platform such as a tablet.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: June 6, 2017
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Michael A. diPilla
  • Patent number: 9659862
    Abstract: Methods, apparatus, and systems for fabricating and using a semiconductor device comprising a first conductive element; a second conductive element; and an e-fuse comprising a first region comprising a conductive oxide of a first metal; and a second region comprising a second metal, wherein an oxide of the second metal is resistive; wherein the e-fuse is electrically connected to both the first conductive element and the second conductive element.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: May 23, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Suraj Kumar Patil, Min-Hwa Chi
  • Patent number: 9653469
    Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a substrate area, two storage units, a spacer structure and two control units. The storage units include two anti-fuse gates each having a gate dielectric layer between the anti-fuse gate and the substrate area and two diffusion areas. The spacer structure is formed on the substrate area and between the two anti-fuse gates and contacts thereto. Each of the diffusion areas is a first doping area doped with a first type dopant contacting one of the two anti-fuse gates. Each of the control units includes a select gate formed on the substrate area and a second doping area. A first side of the select gate contacts one of the diffusion areas of the storage unit. The second doping area is doped with the first type dopant and contacts a second side of the select gate.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: May 16, 2017
    Assignee: Copee Technology Company
    Inventors: Chrong-Jung Lin, Ya-Chin King
  • Patent number: 9647092
    Abstract: An e-Fuse structure is provided on a surface of an insulator layer of a semiconductor-on-insulator substrate (SOI). The e-Fuse structure includes a first metal semiconductor alloy structure of a first thickness, a second metal semiconductor alloy structure of the first thickness, and a metal semiconductor alloy fuse link is located laterally between and connected to the first and second metal semiconductor alloy structures. The metal semiconductor alloy fuse link has a second thickness that is less than the first thickness.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: May 9, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hong He, Juntao Li, Chih-Chao Yang, Yunpeng Yin
  • Patent number: 9637834
    Abstract: A method for fabricating an electrically programmable fuse structure is provided. The method includes providing a substrate. The method also includes forming an anode and a cathode on the substrate. Further, the method includes forming a fuse between the anode and the cathode and having an anode-connecting-end connecting with the anode and a cathode-connecting-end connecting with the cathode over the substrate. Further, the method also includes forming a compressive stress region in the cathode-connecting-end, wherein the anode-connecting-end has a tensile stress region.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: May 2, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Zhenghao Gan
  • Patent number: 9627529
    Abstract: In one embodiment, an integrated circuit includes an array of active structures, an array of dummy structures and multiple well-tap structures. The array of dummy structures surrounds the array of active structures. The well-tap structures may be interposed between the array of active structures and the array of dummy structures. In one embodiment, each of the well-tap structures may include a well, a diffusion region and a gate-like structure. The well may be formed in a substrate and is of a first doping type. The diffusion region may be formed in the well and is also of the first doping type. The gate-like structure may be formed above the substrate and adjacent to the diffusion region.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: April 18, 2017
    Assignee: Altera Corporation
    Inventors: Yue Teng Tang, Albert Victor Kordesch
  • Patent number: 9620449
    Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: April 11, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takehiro Ueda