Abstract: An integrated component includes a semiconductor substrate; at least one interconnect applied on the semiconductor substrate; an insulating layer applied on the at least one interconnect; and at least one opening through the insulating layer which interrupts the at least one interconnect into a first section and a second section.

Abstract: A semiconductor device includes a fuse pattern formed as conductive polymer layer having a low melting point. The fuse pattern is easily cut at low temperature to improve repair efficiency. The semiconductor device includes first and second fuse connecting patterns that are separated from each other by a distance, a fuse pattern including a conductive polymer layer formed between the first and second fuse connection patterns and connecting the first and second fuse connection patterns, and a fuse box structure that exposes the fuse pattern. The conductive polymer layer includes a nano-sized metal powder and a polymer.

Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.

Abstract: The semiconductor device includes: a substrate; an electric fuse that includes a lower-layer wiring formed on the substrate, a first via provided on the lower-layer wiring and connected to the lower-layer wiring, and an upper-layer wiring provided on the first via and connected to the first via, a flowing-out portion of a conductive material constituting the electric fuse being formed in a cut-off state of the electric fuse; and a heat diffusion portion that includes a heat diffusion wiring that is formed in the same layer as one of the upper-layer wiring and the lower-layer wiring and is placed on a side of the one of the upper-layer wiring and the lower-layer wiring, the heat diffusion portion being electrically connected to the one of the upper-layer wiring and the lower-layer wiring.

Abstract: A memory cell is provided that includes a diode and a resistance-switching material layer coupled in series with the diode. The resistance-switching material layer: (a) has a dielectric constant in the range of about 5 to about 27, and (b) includes a material from the family consisting of XvOw, wherein X represents an element from the family consisting of Hf and Zr, and wherein the subscripts v and w have non-zero values that form a stable compound. Other aspects are also provided.

Abstract: Techniques for incorporating nanotechnology into electronic fuse (e-fuse) designs are provided. In one aspect, an e-fuse structure is provided. The e-fuse structure includes a first electrode; a dielectric layer on the first electrode having a plurality of nanochannels therein; an array of metal silicide nanopillars that fill the nanochannels in the dielectric layer, each nanopillar in the array serving as an e-fuse element; and a second electrode in contact with the array of metal silicide nanopillars opposite the first electrode. Methods for fabricating the e-fuse structure are also provided as are semiconductor devices incorporating the e-fuse structure.

Abstract: An object is to provide a semiconductor device mounted with memory which can be driven in the ranges of a current value and a voltage value which can be generated from a wireless signal. Another object is to provide write-once read-many memory to which data can be written anytime after manufacture of a semiconductor device. An antenna, antifuse-type ROM, and a driver circuit are formed over an insulating substrate. Of a pair of electrodes included in the antifuse-type ROM, the other of the pair of the electrodes is also formed through the same step and of the same material as a source electrode and a drain electrode of a transistor included in the driver circuit.

Abstract: A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate.

Abstract: A semiconductor device includes an electric fuse formed on a substrate. The electric fuse includes: a first interconnect formed on one end side thereof; a second interconnect formed in a layer different from a layer in which the first interconnect is formed; a first via provided in contact with the first interconnect and the second interconnect to connect those interconnects; a third interconnect formed on another end side thereof, the third interconnect being formed in the same layer in which the first interconnect is formed, as being separated from the first interconnect; and a second via provided in contact with the third interconnect and the second interconnect to connect those interconnects, the second via being lower in resistance than the first via. The electric fuse is disconnected by a flowing-out portion to be formed of a conductive material forming the electric fuse which flows outwardly during disconnection.

Abstract: One-time programmable (OTP) Electronically Programmable Read-Only Memories (EPROMs) have been used in a number of applications for many years. One drawback with these OTP EPROMs is that these nonvolatile memories tend to be slow and/or may use a considerable amount of area. Here, however, a bit cell is provided that employs a compact dual cell, which generally includes two OTP cells. These OTP cells are generally arranged in differential configuration to increase speed and are arranged to have a small impact on area.

Abstract: A method for forming a fuse of a semiconductor device includes performing an ion-implanting process at sides of a fuse blowing region of a metal fuse, thereby increasing the concentration of impurity ions of a thermal transmission path region. In a subsequent laser blowing process, as a result of the increased resistance of metal fuse the electric and thermal conductivity is reduced, thereby increasing the thermal condensation efficiency of the fuse blowing region and improving the efficiency of the laser blowing process.

Abstract: Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.

Abstract: A three dimensional multilayer circuit (600) includes a plurality of crossbar arrays (512) made up of intersecting crossbar segments (410, 420) and programmable crosspoint devices (514) interposed between the intersecting crossbar segments (410, 420). Shift pins (505, 510) are used to shift connection domains (430) of the intersecting crossbar segments (410, 420) between stacked crossbar arrays (512) such that the programmable crosspoint devices (514) are uniquely addressed. The shift pins (505, 510) make electrical connections between crossbar arrays (512) by passing vertically between crossbar segments (410, 510) in the first crossbar array (512) and crossbar segments in a second crossbar array. A method for transforming multilayer circuits is also described.

Abstract: A semiconductor memory device includes at least one first semiconductor chip including a plurality of memory cells and a second semiconductor chip including a fuse circuit configured to repair defective cells among the memory cells of the at least one first semiconductor chip.

Abstract: In some embodiments, a semiconductor device includes a fuse having a conductive portion configured to be blown when a current exceeding a rated value flows through the conductive portion, a first monitor wiring configured to monitor blowing of the conductive portion of the fuse, and a second monitor wiring configured to monitor blowing of the conductive portion of the fuse. The first monitor wiring and the second monitor wiring are connected to the conductive portion of the fuse so as to be away from a longitudinal center of the conductive portion.

Abstract: A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region.

Abstract: A conductor-filled damage propagation barrier is formed extending into a low-k dielectric layer between a fuse and an adjacent circuit element for preventing propagation of damage during a fuse blow operation. Conductor material filling the damage propagation barrier is formed from the same conductor layer as that used to form an interconnect structure.

Abstract: A programmable passive device comprising a first node and a second node. A plurality of passive device elements electrically coupled to the first node. A plurality of switches are electrically coupled to at least the second node and selectively coupled to a number of the plurality of passive device elements to provide the programmable passive device with a pre-determined value.

Abstract: A memory device without additional logic circuits, including a memory cell which cannot be accessed by a third party and which is always accessible when needed. One embodiment is a memory device including a first memory cell and a second memory cell, and the second memory cell includes a second transistor having a second channel formed of an oxide semiconductor film. Data is read from the second memory cell when the second transistor is being irradiated with ultraviolet rays.

Abstract: A memory array including a diffusion layer, a poly layer, a metal one layer, a metal two layer, and a contact. The diffusion layer comprises diffusion lines extending in a first direction. The poly layer comprises poly lines extending in the first direction and being arranged on top of and insulated from the diffusion layer. The metal one layer comprises metal one lines extending in the first direction and being arranged on top of and insulated from the poly layer. The metal two layer comprises a metal two line extending in the first direction and being arranged on top of and insulated from the metal one layer. The contact extends through the poly layer, and connects a metal one line to a diffusion line. A poly line further extends in a second direction to bend around the contact such that a predetermined distance separates the poly lines from the contact.

Abstract: The present invention relates to a fuse for a semiconductor device, and discloses the technique capable of preventing fuse damage, which might occur during a fuse blowing step, with reducing area of the fuse occupying the semiconductor device. The present invention includes a common source region, wherein a plurality of fuses are radially arranged about the common source region, and a fuse box wall is formed outside the fuses.

Abstract: An electrical device with a fin structure, a first section of the fin structure having a first width and a first height, a second section of the fin structure having a second width and a second height, wherein the first width is smaller than the second width and the first height is lower than the second height.

Abstract: A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P?/N+ device or a P+/N?/P+ device.

Abstract: A tamper resistant fuse design is generally presented. In this regard, an apparatus is introduced comprising a plurality of fuses in an integrated circuit device to store values and a plurality of resistors in parallel to the fuses, wherein each fuse includes a parallel resistor to provide a potential dissipation path around the fuse. Other embodiments are also described and claimed.

Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.

Abstract: A typical switching device according to the present invention comprises first insulating layer 1003 having an opening and made of a material for preventing metal ions from being diffused, first electrode 104 disposed in the opening and including a material capable of supplying the metal ions, ion conduction layer 105 disposed in contact with an upper surface of the first electrode 104 and capable of conducting the metal ions, and second electrode 106 disposed in contact with an upper surface of the ion conduction layer 105 and including a region made of a material incapable of the metal ions. A voltage is applied between the first electrode 104 and the second electrode 106 for controlling a conduction state between the first electrode 104 and the second electrode 106.

Abstract: A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered.

Abstract: A semiconductor device includes an electric fuse formed on a semiconductor substrate and composed of an electric conductor. The electric fuse includes an upper layer interconnect, a via coupled to the upper interconnect and a lower layer interconnect coupled to the via, which are formed in different layers, respectively, in a condition before cutting the electric fuse, and wherein the electric fuse includes a flowing-out region formed of the electric conductor being flowed toward outside from the second interconnect and a void region formed between the first interconnect and the via or in the via, in a condition after cutting the electric fuse.

Abstract: A dynamic and end-user configurable controlled impedance interconnect line includes a plurality of conductive pixels, a plurality of thin-film transition material interconnects to electrically connect adjacent conductive pixels in the plurality of conductive pixels, and a plurality of addressable pixel interconnect actuators to selectively heat a respective plurality of the thin-film transition material interconnects. The plurality of addressable pixel interconnect actuators is operable to selectively heat a respective plurality of the thin-film transition material interconnects to form an interconnect line.

Abstract: A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

Abstract: A semiconductor device has a semiconductor substrate and a first electrical fuse and a second electrical fuse, which are provided on the semiconductor substrate. The first electrical fuse has a first upper layer wire and a first lower layer wire formed in different wire layers, and a via for connecting the first upper layer wire to the first lower layer wire. The second electrical fuse has a second upper layer wire and a second lower layer wire formed in different wire layers, and a via for connecting the second upper layer wire to the second lower layer wire. The semiconductor device has a connection portion for connecting the above described first upper layer wire of the first electrical fuse to the second lower layer wire of the second electrical fuse. The connection portion connects the first electrical fuse and the second electrical fuse in series.

Abstract: Under one aspect, a non-volatile nanotube switch includes a first terminal; a nanotube block including a multilayer nanotube fabric, at least a portion of which is positioned over and in contact with at least a portion of the first terminal; a second terminal, at least a portion of which is positioned over and in contact with at least a portion of the nanotube block, wherein the nanotube block is constructed and arranged to prevent direct physical and electrical contact between the first and second terminals; and control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube block can switch between a plurality of electronic states in response to a plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube block provides an electrical pathway of different resistance between the first and second terminals.

Abstract: A via-configurable circuit block may contain chains of p-type and n-type transistors that may or may not be interconnected by means of configurable vias. Configurable vias may also be used to connect various transistor terminals to a ground line, a power line and/or to various terminals that may provide connections outside of the circuit block.

Abstract: An image sensor and a method for fabricating the same are provided. The image sensor includes a first conductive type substrate including a trench formed in a predetermined portion of the first conductive type substrate, a second conductive type impurity region for use in a photodiode, formed below a bottom surface of the trench in the first conductive type substrate, and a first conductive type epitaxial layer for use in the photodiode, buried in the trench.

Abstract: Reconfigurable 3D interconnect is provided that can be used for digital and RF signals. The reconfigurable 3D interconnect can include an array of vertical interconnect vias (or TSVs) providing a signal path between a first core element of a 3D IC and a second core element of the 3D IC stacked above the first core element. A routing circuit can be used to route a signal from the first core element to the second core element through selected TSVs of the array of TSVs providing the signal path between the first core element and the second core element. The routing circuit allows re-routing of the signal through different selected TSVs during operation, which can provide real time adjustments and capacity optimization of the TSVs passing the particular signal between the elements.

Abstract: Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.

Abstract: An electrically alterable circuit (EAC), suitable for use in an integrated circuit, includes a first interconnect, a link element, and a second interconnect. A first set of interconnect vias provides an electrically conductive connection between the first interconnect and a first end of the link element; A second set of interconnect vias provides an electrically conductive connection between the second interconnect and a second end of the link element. The EAC further includes a third interconnect and a one or more fuse vias that provide an electrical connection between the third interconnect and the link element. A conductance of the one or more fuse vias is less than a conductance of the first set of interconnect vias, a conductance of the second set of interconnect vias, or both.

Abstract: According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure including a gate metal segment situated between a dielectric segment and a polysilicon segment, a gate metal fuse being formed in a portion of the gate metal segment. The method further includes doping the polysilicon segment so as to form first and second doped polysilicon portions separated by an undoped polysilicon portion where, in one embodiment, the gate metal fuse is substantially co-extensive with the undoped polysilicon portion. The method can further include forming a first silicide segment on the first doped polysilicon portion and a second silicide segment on the second doped polysilicon portion, where the first and second silicide segments form respective terminals of the one-time programmable metal fuse structure.

Abstract: A laser activated phase change device for use in an integrated circuit comprises a chalcogenide fuse configured to connect a first patterned metal line and a second patterned metal line and positioned between an inter layer dielectric and an over fuse dielectric. The fuse interconnects active semiconductor elements manufactured on a substrate. A method for activating the laser activated phase change device includes selecting a laser condition of a laser based on characteristics of the fuse and programming a phase-change of the fuse with the laser by direct photon absorption until a threshold transition temperature is met.

Abstract: A dielectric material layer is formed on a metal gate layer for a metal gate electrode, and then lithographically patterned to form a dielectric material portion, followed by formation of a polycrystalline semiconductor layer thereupon. A semiconductor device employing a metal gate electrode is formed in a region of the semiconductor substrate containing a vertically abutting stack of the metal gate layer and the polycrystalline semiconductor layer. A material stack in the shape of an electrical fuse is formed in another region of the semiconductor substrate containing a vertical stack of the metal gate layer, the dielectric material portion, and the polycrystalline semiconductor layer. After metallization of the polycrystalline semiconductor layer, an electrical fuse containing a polycrystalline semiconductor portion and a metal semiconductor alloy portion is formed over the dielectric material portion that separates the electrical fuse from the metal gate layer.

Abstract: An upper electrode of a capacitor has a two-layer structure of first and second upper electrodes. A gate electrode of a MOS field effect transistor and a fuse are formed by patterning conductive layers used to form the lower electrode, first upper electrode and second upper electrode of the capacitor. In forming a capacitor and a fuse on a semiconductor substrate by a conventional method, at least three etching masks are selectively used to pattern respective layers to form the capacitor and fuse before wiring connection. The number of etching masks can be reduced in manufacturing a semiconductor device having capacitors, fuses and MOS field effect transistors so that the number of processes can be reduced and it becomes easy to improve the productivity and reduce the manufacture cost.

Abstract: A semiconductor device includes: a lower layer interconnection formed on a chip; an upper layer interconnection formed in an upper layer above the lower layer interconnection above the chip; an interconnection via formed to electrically connect the lower layer interconnection and the upper layer interconnection; a via-type electric fuse formed to electrically connect the lower layer interconnection and the upper layer interconnection. The fuse is cut through heat generation, and a sectional area of the fuse is smaller than a sectional area of the upper layer interconnection and a via diameter of the fuse is smaller than that of the interconnection via.

Abstract: An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF.

Abstract: A capacitance trimming circuit of a semiconductor device may include a plurality of capacitor layers and/or a plurality of fuses. The plurality of capacitor layers may be vertically stacked. The plurality of fuses may be arranged to correspond to the plurality of capacitor layers, and/or the plurality of fuses may be configured to select corresponding ones of the plurality of capacitor layers for controlling a capacitance of the plurality of capacitor layers.

Abstract: An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

Abstract: Integrated mask-programmable device, having a plurality of metal levels including a top metal level, a bottom metal level and a first intermediate metal level formed between the top and bottom metal levels, and a plurality of via levels arranged between the bottom and the first intermediate metal levels and between the first intermediate and the top metal levels and connecting each metal level to adjacent metal levels. The plurality of metal levels forms a first, a second and at least a third terminal, the top and bottom metal levels having at least two metal regions, and the first intermediate metal level having at least three metal regions. The first terminal is connected to third terminal or the second terminal is connected to the third terminal by modifying a single metal or via level.

Abstract: Nanotube switching devices having nanotube bridges are disclosed. Two-terminal nanotube switches include conductive terminals extending up from a substrate and defining a void in the substrate. Nantoube articles are suspended over the void or form a bottom surface of a void. The nanotube articles are arranged to permanently contact at least a portion of the conductive terminals. An electrical stimulus circuit in communication with the conductive terminals is used to generate and apply selected waveforms to induce a change in resistance of the device between relatively high and low resistance values. Relatively high and relatively low resistance values correspond to states of the device. A single conductive terminal and a interconnect line may be used. The nanotube article may comprise a patterned region of nanotube fabric, having an active region with a relatively high or relatively low resistance value. Methods of making each device are disclosed.

Abstract: A nonvolatile memory device (21) is provided with a semiconductor substrate, a plurality of active regions (3) formed on the semiconductor substrate and extending in a band, a plurality of select active elements (23) formed in the active regions (3) and having a first impurity diffusion region and a second impurity diffusion region, a plurality of first electrodes (13) electrically connected to the first impurity diffusion region, a variable resistance layer (12) electrically connected to the first electrodes (13), and a plurality of second electrodes electrically connected to the variable resistance layer (12). Among the plurality of first electrodes (13) and the plurality of second electrodes, an array direction of at least one pair of the first electrodes (13) and the second electrodes that are electrically connected to the same variable resistance layer (12), and a direction of extension of the activation regions (3) are not parallel.

Abstract: One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower resistivity materials allows device dimension to be reduced by mitigating increases in resistance that occur when the size of the conductors is reduced. As such, more cells can be produced over a given area, thus increasing the density and storage capacity of a resulting memory array.

Abstract: A phase-change channel transistor includes a first electrode; a second electrode; a memory layer provided between the first and second electrodes; and a third electrode provided for the memory layer with an insulating film interposed therebetween, wherein the memory layer includes at least a first layer formed from a phase-change material which is stable in either an amorphous phase or a crystalline phase at room temperature and a second layer formed from a resistive material, and wherein the resistance value of the second layer is smaller than the resistance value of the first layer in the amorphous phase, but is larger than the resistance value of the first layer in the crystalline phase.