Abstract: A semiconductor device that enables to prevent the electron transport property of a semiconductor active layer from degrading even if a semiconductor compositionally-graded buffer layer is used. This device contains a semiconductor substrate, a semiconductor active layer lattice-mismatched with the substrate, and a semiconductor compositionally-graded buffer layer formed between the substrate and the active layer. The compositionally-graded buffer layer has a semiconductor superlattice structure including first semiconductor sublayers and second semiconductor sublayers that are alternately stacked in a direction perpendicular to the substrate. Each of the first sublayers is made of a first semiconductor material. Each of the second sublayers is made of a second semiconductor material different in composition from the first semiconductor material. The lattice constant of the first and second sublayers decreases or increases stepwise from a side near the substrate and the other side near the active layer.

Abstract: Disclosed is a semiconductor device comprising an undoped GaAs layer, an intermediate undoped layer and an undoped Ga.sub.1-x Al.sub.x As layer which are successively provided on a substrate made of a semiinsulating GaAs crystal; the intermediate undoped layer being an undoped In.sub.y Ga.sub.1-y As layer, an undoped GaAs.sub.1-z Sb.sub.z layer, a superlattice layer which includes an undoped In.sub.y Ga.sub.1-y As layer and an undoped GaAs.sub.1-z Sb.sub.z layer, a superlattice layer which includes an undoped In.sub.y Ga.sub.1-y As layer and an undoped GaAs layer, or a superlattice layer which includes an undoped GaAs.sub.1-z Sb layer and an undoped GaAs layer. When applied to a high electron mobility transistor, this semiconductor device affords a high current and a high speed and has the merit of a small dispersion in the threshold voltage thereof.

Abstract: A double electron layer tunneling device is presented. Electrons tunnel from a two dimensional emitter layer to a two dimensional tunneling layer and continue traveling to a collector at a lower voltage. The emitter layer is interrupted by an isolation etch, a depletion gate, or an ion implant to prevent electrons from traveling from the source along the emitter to the drain. The collector is similarly interrupted by a backgate, an isolation etch, or an ion implant. When the device is used as a transistor, a control gate is added to control the allowed energy states of the emitter layer. The tunnel gate may be recessed to change the operating range of the device and allow for integrated complementary devices. Methods of forming the device are also set forth, utilizing epoxy-bond and stop etch (EBASE), pre-growth implantation of the backgate or post-growth implantation.

Abstract: An active layer of a field effect transistor disposed on an InP substrate (101) comprises at least an InAs layer (105) and two InGaAs layers (104, 106). The InGaAs layer (104) is In.sub.x Ga.sub.1-x As (wherein 0.55<x<1) and the InGaAs layer (106) is In.sub.y Ga.sub.1-y As (wherein 0.55<y<1). The active layer comprises, for example, In.sub.0.53 Ga.sub.0.47 As layer (103)/In.sub.0.8 Ga.sub.0.2 As layer (104)/InAs layer (105)/In.sub.0.8 Ga.sub.0.2 As layer (106)/In.sub.0.53 Ga.sub.0.47 As layer (107). Electrons which have been leached out of the InAs layer (105) are confined into the InGaAs layers (104, 106), and about 90% of the active electrons are accumulated in the layers (104, 105, 106) to achieve an excellent electron transport performance, so that an excellent high frequency characteristic can be obtained exhibiting a high cut-off frequency and an improved transconductance.

Abstract: On a compound semiconductor substrate on which a compound semiconductor device is formed, a film having a multilayer structure formed by alternately depositing a multi-element compound semiconductor layer and a GaAs layer containing arsenic excessively deviating from a stoichiometric ratio repeatedly and an active layer deposited on said film having a multilayer structure are formed.When the thickness of the GaAs layer is made to a critical film thickness or less, even if the GaAs layer and the multi-element compound semiconductor layer have different lattice constants, the strain of lattice mismatch is confined in the vicinity of the interface, and a high resistance is achieved while maintaining a crystal of high quality as it is.

Abstract: Disclosed is a GaAs power semiconductor device operating at a low voltage and a method for fabricating the device, the method comprising the steps of sequentially forming a first undoped GaAs buffer layer, a superlattice layer, a second undoped GaAs buffer layer, a channel layer and a surface passivation layer on a semi-insulating GaAs substrate; etching a plurality of layers formed on the substrate using a device isolating mask so as to electrically isolate elements; selectively etching the surface passivation layer to form contact holes for source/drain formation and forming ohmic metallic layers in the contact holes; sequentially removing the surface passivation layer and the channel layer to some deep extent to form a contact hole for gate formation between the source and the drain; forming a gate in the contact hole and at the same time forming source and drain electrodes on the ohmic metallic layers; depositing a first SiN layer over the gate, the source and drain electrodes and the surface passivation

Abstract: A memory device and memory incorporating a plurality of the memory devices is described wherein each memory device has spaced apart source and drain regions, a channel, a barrier insulating layer, a nanocrystal or a plurality of nanocrystals, a control barrier layer, and a gate electrode. The nanocrystal which may be a quantum dot, stores one electron or hole or a discrete number of electrons or holes at room temperature to provide threshold voltage shifts in excess of the thermal voltage for each change in an electron or a hole stored. The invention utilizes Coulomb blockade in electrostatically coupling one or more stored electrons or holes to a channel while avoiding in-path Coulomb-blockade controlled conduction for sensing the stored charge.

Abstract: The tunnel transistor of the present invention has either a junction structure wherein a degenerated first semiconductor having one conduction type, a non-degenerated second semiconductor and a degenerated third semiconductor having the reverse conduction type to that of the first semiconductor are connected on a substrate or a laminated layer structure comprising a degenerated first semiconductor having one conduction type, a non-degenerated second semiconductor and a degenerated third semiconductor of the reverse conduction type to that of the first semiconductor all laminated on a part of a substrate. The tunnel transistor further includes a fourth semiconductor layer formed on an exposed surface of the second semiconductor, having a forbidden band wider than that of the second semiconductor and containing an ionized impurity therein, a gate electrode formed on the fourth semiconductor layer, and a pair of electrodes individually forming ohmic junctions to the first and third semiconductors.

Abstract: A semiconductor device includes a semi-insulating semiconductor substrate, a semiconductor layer structure including at least an undoped layer of a first semiconductor, an undoped spacer layer of a second semiconductor having an electron affinity smaller than that of the first semiconductor, and an n type electron supply layer of the second semiconductor successively laminated on the substrate, the undoped layer having a flat top surface and a flat rear surface on the flat top surface of the undoped spacer layer, having, at a top surface, a concavo-convex periodic structure, and a flat rear surface, the n-type electron supply layer of the second semiconductor having a flat top surface and a rear surface that buries concavities of the concavo-convex structure of the undoped spacer layer, and a plurality of periodically arranged Schottky electrodes on the flat top surface of the n type electron supply layer, arranged in a direction perpendicular to the concavo-convex periodic structure of the undoped spacer lay

Abstract: According to the present invention, there is provided a correlation tunnel device capable of achieving a low power consumption without decreasing a drive force when a large-scale-integrated circuit is constituted.

Abstract: An electronic device which includes, a couple of first conduction regions which are capable of confining carriers, a second conduction region having a higher energy level than those of the first conduction regions, and a first electrode for impressing a voltage on the first conduction regions, wherein when a voltage is impressed via the first electrode between the couple of first conduction regions, carriers are caused to move due to a tunneling effect from one of the first conduction regions via the second conduction region to the other of the first conduction regions, and when the voltage impressed between the couple of first conduction regions is removed, carriers are confined mainly in the one of the first conduction regions.

Abstract: A thin film transistor includes, a) a thin film source region; b) a thin film drain region; c) a polycrystalline thin film channel region intermediate the thin film source region and the thin film drain region; d) a transistor gate and gate dielectric operatively positioned adjacent the thin film channel region; and e) the thin film channel region comprising at least an inner layer, an outer layer and a middle layer sandwiched between the inner layer and the outer layer, the inner layer and the outer layer comprising polycrystalline silicon and having respective energy bandgaps, the middle sandwich layer comprising a polycrystalline material and having a lower energy bandgap than either of the inner and outer layers. Alternately, the channel region is homogeneous, comprising germanium or an alloy of polycrystalline silicon and germanium.

Abstract: A GaAs-InGaAs high electron mobility transistor includes: a GaAs substrate; a GaAs buffer layer overlaying on the GaAs substrate; a graded InGaAs channel overlaying on the GaAs layer; a GaAs spacer layer overlaying on the graded InGaAs channel layer; a .delta.-doping layer overlaying on the GaAs spacer layer; a GaAs cap layer overlaying on the .delta.-doping layer; drain and source terminals overlaying on the GaAs cap layer and contacting the graded InGaAs channel layer; and a gate terminal overlaying on the GaAs cover layer and located between the drain terminal and the source terminal. One kind of modified transistor uses the symmetric channel .delta.-doping structure to replace the graded InGaAs channel of the transistor.

Abstract: The single electron transistor can be operated at room temperature. The distance between the electrodes 5, 5 can be adjusted by the length of the protein and/or the wideness of the lipid bilayer and the distance between the quantum dot 4 and one of the electrodes 5 can be adjusted in units of 1.5 .ANG. by means of .alpha.-helix confirmation of a G segment of the protein.

Abstract: A semiconductor device in which a current is controlled by light includes a semiconductor member having a source unit and a drain unit and a channel unit through which electrons may flow between the source unit and the drain unit. The channel unit has a quantum well layer having a plurality of quantum energy levels and barrier layers provided adjacent to the well layer. Upon light irradiation of the quantum well layer, electrons make transitions between the different quantum energy levels, and the current flowing between the source unit and the drain unit is controlled by varying the mobility of these transitioned electrons.

Abstract: A strained quantum well structure comprises a substrate, and a strained quantum well. The strained quantum well has at least one well layer and a plurality of barrier layers. The well layer is sandwiched by the barrier layers. At least a portion of the well layer and the barrier layers is composed of semiconductor crystal whose amount of strain is distributed, and the band structure of the quantum well is constructed so that the transition in the quantum well layer can be exchanged between states in which first polarization-state, typically transverse electric, transition is dominant and in which second polarization-state, typically transverse magnetic, transition is dominant.

Abstract: A semiconductor device according to the invention has a channel layer, which is sandwiched by a first and a second barrier layers, and an electron supply layer for supplying the channel layer with electrons through at least one of the barrier layers. The channel layer has a superlattice structure formed by periodically repeating, in the direction of electron movement, a first and a second semiconductor material regions, each of which has a different band gap from the other. With this superlattice structure, a plurality of mini-bands are formed within a potential well, which is formed by the first and second barrier layers. Impurity concentration of the electron supply layer is so controlled that electrons may move mainly within a mini-band in which effective mass of electrons is minimum among those mini-bands. Thus, a semiconductor device having a high electron mobility in the room temperature can be obtained without requiring high purification of crystal.

Abstract: A high electron mobility transistor type group III-V compound semiconductor device includes a substrate of a group III-V compound semiconductor, an electron transfer layer of a group III-V compound semiconductor formed on the substrate, an impurity doped electron supply layer of a group III-V compound semiconductor having a wider band gap and smaller electron affinity than the electron transfer layer, and a spacer layer of a group III-V compound semiconductor having a lattice mismatch with the electron supply layer, the spacer layer being formed between the electron transfer layer and the electron supply layer. A HEMT type group III-V compound semiconductor device is provided which uses an Si-doped electron supply layer of material such as InGaP other than AlGaAs and has good device properties.

Abstract: A field effect transistor has a channel between a source electrode and a drain electrode made from an organic semiconductor. In one form of the invention, the channel is a mixture of at least two different organic compounds. In another form of the invention, the channel is a lamination of at least two films of different organic compounds. The channel can also be a .pi.-conjugated block copolymer of at least two different types of monomers.

Abstract: A semiconductor crystalline laminate structure wherein between a first semiconductor layer consisting of a first alloyed semiconductor and a second semiconductor layer which has an energy gap wider than that of the first alloyed semiconductor and a lattice constant smaller than that of the first alloyed semiconductor and consists of one semiconductor selected from a group of single-element semiconductor, compound semiconductor, and alloyed semiconductor which contain no semiconductor having a largest lattice constant among the semiconductor constituting the first alloyed semiconductor, a third semiconductor layer which consists of a second alloyed semiconductor having an energy gap wider than that of the first alloyed semiconductor and contains the semiconductor having a largest lattice constant among the semiconductors constituting the first alloyed semiconductor is formed in contact with these layers, a forming method for the semiconductor crystalline laminate structure, and a semiconductor device using the

Abstract: An electrically isolated MESFET includes a compound semiconductor substrate; a plurality of compound semiconductor layers disposed on the compound semiconductor substrate; a MESFET structure in a prescribed region of the compound semiconductor layers; an electrically isolating region in the compound semiconductor layers surrounding and electrically isolating the MESFET structure from the compound semiconductor layers outside the electrically isolating region, wherein the compound semiconductor layer most remote from the compound semiconductor substrate has the highest conductivity of the compound semiconductor layers; a recess penetrating the compound semiconductor layer most remote from the compound semiconductor substrate and at least the compound semiconductor layer adjacent the compound semiconductor layer most remote from the compound semiconductor substrate, the recess dividing the compound semiconductor layer most remote from the compound semiconductor substrate into mutually separated first and second

Abstract: An undoped GaAs layer is epitaxially grown on a substrate in a crystal growth device. An undoped Al.sub.x Ga.sub.1-x As layer is then epitaxially grown to form an undoped hetero-junction structure. After this, a sample is transferred to a focused ion beam (FIB) apparatus. A dopant ion beam is focused and implanted into the Al.sub.x Ga .sub.1-x As layer in a dot-like or wire-like pattern so that it does not extend to the undoped GaAs layer or channel layer, and a zero- or one-dimensional carrier gas 8 is generated in the channel layer. The invention allows maskless ion implantation, and makes the fabrication process much easier because quantum wires and dots are drawn, patterned or formed directly by ion implantation. In addition, no etching process is required, so quantum wires and quantum dots can be fabricated precisely.

Abstract: Novel semiconductor devices are monolithically defined with p-type and n-type wide bandgap material formed by impurity induced layer disordering of selected regions of multiple semiconductor layers. The devices are beneficially fabricated by simultaneously forming the n-type and p-type layer disordered regions with sufficiently abrupt transitions from disordered to as-grown material. The novel devices include a heterojunction bipolar transistor monolithically integrated with an edge emitting heterostructure laser or a surface emitting laser, a heterostructure surface emitting laser, a heterostructure surface emitting laser having active distributed feedback, devices containing multiple buried layers which are individually contacted such as p-n junction surface emitting lasers, carrier channeling devices, and "n-i-p-i" or hetero "n-i-p-i" devices, and novel interdigitated structures, such as optical detectors and distributed feedback lasers.

Abstract: A heterostructure includes a stained epitaxial layer of either silicon or germanium that is located overlying a silicon substrate, with a spatially graded Ge.sub.x Si.sub.1-x epitaxial layer overlain by a ungraded Ge.sub.x.sbsb.0 Si.sub.1-x.sbsb.0 intervening between the silicon substrate and the strained layer. Such a heterostructure can serve as a foundation for such devices as surface emitting LEDs, either n-channel or p-channel silicon-based MODFETs, and either n-channel or p-channel silicon-based MOSFETs.

Abstract: The invention provides a FET by forming a channel layer in layer including "n" type impurity at high concentration, which is sandwiched by a first semiconductor layer and a second semiconductor layer lightly doped with impurity. Therefore even when electrons in the channel layer obtain high energy, the electrons in this arrangement rush out essentially to the second semiconductor layer excelling in electron carrying characteristic, thus a travelling speed of the electrons in the channel layer is not lowered. Furthermore the channel layer being formed in layer and allowed to include impurity at high concentration, the current drive capability can be improved.

Abstract: A superconducting thin film formed on a substrate, comprising at least one oxide superconductor layer formed on the principal surface of said substrate and at least one oxide layer formed of an oxide which compensates for crystalline incompleteness at the surface of said oxide superconductor layer, and which is arranged on or under the superconducting layer.

Abstract: High speed Group III-Sb materials are n-doped in a molecular beam epitaxy process by forming a superlattice with n-doped strained layers of a Group III-V compound upon Group III-Sb base layers. The base layers have lower conduction band energy levels than the strained layers, and allow doping electrons from the strained layers to flow into the base layers. The base layers preferably comprise Al.sub.x Ga.sub.1-x Sb, while the strained layers preferably comprise a binary or ternary compound such as Al.sub.y Ga.sub.1-y As having a single Group V component, where x and y are each from 0 to 1.0. The strained layers can be n-doped with silicon or tin, which would produce p-type doping if added directly to the base layers.

Abstract: A quantum multifunction transistor including a plurality of conduction layers of semiconductor material with a tunnel barrier layer sandwiched therebetween. The conduction layers each being very thin to form discrete energy levels, and the material being chosen so that discrete energy levels therein are not aligned across the tunnel barrier layer in an equilibrium state. A gate coupled to a portion of one of the conduction layers for aligning, in response to a voltage applied thereto, discrete energy levels in the conduction layers across the tunnel barrier layer, whereby majority carrier current flows through the transistor. Application of a higher voltage to the gate results in minority carrier current flow through the transistor.

Abstract: In a semiconductor device having quantum wire structure formed by first and second semiconductor layers, the first and the second semiconductor layers are used as quantum well and quantum barrier layers, respectively. The quantum well layer has a first conduction band having a first .GAMMA.-valley and a first L-valley. The first .GAMMA.-valley has a first .GAMMA.-valley energy level. The first L-valley has a first L-valley energy level which is not lower than the first .GAMMA.-valley energy level. The quantum barrier layer has a second conduction band having a second energy level which is higher than the first L-valley energy level. The quantum wire structure is extended towards a predetermined direction. More particularly, the predetermined direction is parallel to a crystal orientation of (100).

Abstract: A semiconductor device exploiting a quantum interference effect is disclosed. The device comprises: a rod-shaped semiconductor portion extending in one direction; a prism-shaped semiconductor portion covering side faces of the rod-shaped semiconductor portion and extending in the one direction; and one or more source electrodes and one or more drain electrodes electrically connected to opposite ends of the prism-shaped semiconductor portion. Channels extend in the one direction in the prism-shaped semiconductor portion along a plurality of sides of side faces thereof. Alternatively, the prism-shaped semiconductor portion has a twisted structure about an axis extending in the one direction, and channels each having a twisted structure extend in the one direction in the prism-shaped semiconductor portion along a plurality of sides of side faces thereof.

Abstract: A field effect semiconductor device having multiple vertically stacked channels (12, 14, 16) separated by barrier layers comprising wide bandgap material (18) is provided. The channels (12, 14, 16) are formed on a wide bandgap buffer layer (11) and each channel is coupled a N-type drain region (22b). Each channel is also coupled to an N-type source region (25b). With appropriate gate bias on a gate electrode (17), quantized energy levels in the channels (12, 14, 16) are aligned to provide self-doping by electrons in the valence band of the P-channel (14) moving to the conduction band of the N-channels (12, 16) providing peak channel conductivity. At higher gate bias, one of the N-channels (12) becomes non-conductive creating a negative resistance region.

Abstract: A field effect semiconductor device having multiple vertically stacked channels (12, 14, 16) separated by barrier layers comprising wide bandgap material (18) is provided. The channels (12, 14, 16) are formed on a wide bandgap buffer layer (11) and each channel is coupled a P-type drain region (22b). Each channel is also coupled to an N-type source region (25b). With appropriate gate bias on a gate electrode (17), quantized energy levels in the channels (12, 14, 16) are aligned providing peak current flow by electrons tunneling from the conduction band of one or more N-channels (12, 16) to the valence band of the P-channel (14).

Abstract: A unipolar electronic component is proposed with a quasi one dimensional carrier channel which has all the characteristics of an FET. This component can be very simply produced, has "self-alignment" and linear gates with a low capacity in place of planar gates. In this way a very high operating frequency of the component is possible. The structure comprises an initially homogenous 2D-layer with a high carrier mobility which is formed by epitaxy of for example GaAs. The implantation of focussed ions (for example Ga.sup.+ with 100 keV) locally destroys the conductivity of the electron layer. The irradiated regions remain insulating at low temperature or room temperature even after illuminating the cristal with bandgap radiation. The writing in of the insulating layer is carried out along two paths on the chip so that the 2D-carrier layer is subdivided into three regions insulated from one another.

Abstract: The semiconductor device has a semiconductor substrate composed essentially of a III-V compound semiconductor containing Ga and As, and a surface layer structure provided on the semiconductor substrate and this layer has a composition different from that of the semiconductor substrate. The surface layer structure includes a strained layer epitaxially grown on the surface of the semiconductor substrate and composed essentially of at least one-element selected from the group consisting of indium, gallium, aluminum and boron, and at least one element selected from the group consisting of arsenic and phosphorus. The strained layer has a composition different from that of the semiconductor substrate The strained layer has a valence band maximum lower in energy than that of the valence band maximum of the semiconductor substrate.

Abstract: A semiconductor device consisting of epitaxial material is provided with at least one monoatomic layer of doping atoms, i.e. with a layer which is just one atom thick. A preferred device is a bipolar transistor in which case the Dirac-delta doped p-type layer 38 is directly between n-type collector and emitter layers (32, 33). The bipolar transistor described herein has an extremely low base width and is capable of operating at high frequencies.

Abstract: The invention provides a compound semiconductor multilayer structure having a two-dimensional electron gas, which is applicable to field effect transistors. A ternary compound InGaAs planar channel layer serving as a quantum well has a variation of an In (indium) fraction in a perpendicular direction to a heterojunction interface. The variation has a step-graded profile with taking a maximum value at or in the vicinity of a portion where the two-dimensional electron gas takes a maximum density. Such quantum well has most large depth at a portion except for adjacent portions to the heterojunction interfaces. Such multilayer structure provides a great electron mobility and a strong electron confinement to major electrons at a high electron density portion.

Abstract: An optical device which uses a heterojunction field effect detector (HFED) having wavelength selectivity through the use of ion-implantation, and a wavelength selective grating. The device incorporates a Grinsch layer structure with a single GaAs quantum well. The optical power from the lens couples into a guided mode. The absorbing region is the quantum well itself. In the operation of the HFED, a positive bias is applied to the gate, and the depleted GaAs quantum well below the gate absorbs the photons, generating electron-hole pairs. The photocarriers are separated by the electric field before recombination can occur. The photocurrent is then produced in the external circuit by appropriately biasing the device. For collecting the electrons, a positive bias is applied to both the source and drain contacts, which act as dual drain contacts. The holes are removed via the collector which is maintained at ground. To maximize the responsivity (i.e.

Abstract: A field effect transistor and a ballistic transistor using semiconductor whiskers each having a desired diameter and formed at s desired location, a semiconductor vacuum microelectronic device using the same as electron emitting materials, a light emitting device using the same as quantum wires and the like are disclosed.

Abstract: A hybrid power transistor (40) includes a vertical PNP bipolar transistor (42) having a floating base (46). A junction-gate type field-effect transistor (FET) (62) has a lateral N-type channel (64,66) and a vertical electron injection path (54) from the channel (64,66) into the base (46) of the bipolar transistor (42). The FET channel current and thereby the electron injection current are controlled by the FET gate voltage. The injection current conductivity modulates the base (46) and thereby controls the collector current of the bipolar transistor (42). The FET (62) may have a high electron mobility transistor (HEMT), junction-gate field-effect transistor (JFET) or metal-semiconductor field-effect transistor (MESFET) structure. The FET (62) does not require a gate insulating layer, enabling fabrication of the hybrid transistor (40) in the group III-V material system.

Abstract: Carrier mobility in a heterojunction field effect device is increased by reducing or eliminating alloy scattering. The active channel region of the field effect device uses alternating layers of pure silicon and germanium which form a short period superlattice with the thickness of each layer in the superlattice being no greater than the critical thickness for maintaining a strained heterojunction. The gate contact of the field effect device can comprise quantum Si/Ge wires which provide quantum confinement in the growth plane, thereby allowing the field effect device to further improve the mobility by restricting phonon scattering. The structure can be used to improve device speed performance.

Abstract: A resonant electron transfer device includes a plurality of units each of which has of at least one one-dimensional quantum wire having a quantum well elongated in a direction, a zero-dimensional quantum dot having a base quantization level higher than that of the one-dimensional quantum wire an electrode for controlling respective internal levels of the quantum wire and dot wherein the quantum wire and dot forming one unit is connected via a potential barrier capable of exhibiting a tunnel effect therebetween.

Abstract: This transistor incorporates at least one first stack of semi-conductor conduction layers and at least one second stack of semiconductor layers with a single, highly doped thin film within the second stack giving it the character of a mobile electric charge donor, superimposed and supported by a substrate as well as at least two potential barriers located in the second stack on either side of the doped thin film in order to reduce the concentration of carriers in said second stack a metal gate resting on the second stack for modifying the concentration of carriers of the charges in the first stack, two ohmic contacts being placed on one of the stacks, on either side of the gate and serving as the source and drain.

Abstract: A semiconductor device comprising a semiconductor crystalline substrate having projections each thereof having an area of 0.01 .mu.m.sup.2 to 4 .mu.m.sup.2 or stripe projections each thereof having a width of 0.01 .mu.m to 1 .mu.m and semiconductor crystalline layers formed on the projections, each of the layers having lattice constants different from those of the semiconductor crystalline substrate preferably by 0.5% or more. The semiconductor device is free of dislocations and thermally stable. The semiconductor device can be fabricated by performing such processes as forming projections on the substrate and forming semiconductor crystalline layers on the projections by molecular beam epitaxy.

Abstract: A semiconductor structure comprises a first material layer of a homopolar material having a conduction band that includes an L valley and a .GAMMA. valley such that the L valley has an energy level lower than the .GAMMA. valley when in a bulk crystal state, and a second material layer of a polar compound formed with an epitaxial relationship with respect to the first material layer; wherein the first material layer has a thickness such that there is formed first and second quantum levels respectively in correspondence to the .GAMMA. valley and the L valley such that: the second quantum level has an energy level higher than the first quantum level.

Abstract: A semiconductor light wave detector which has a first layer of a highly doped n-type semiconducting substrate, a second layer of a highly doped n-type semiconducting material, a third layer of a distinct intrinsic semiconducting material and a fourth layer of a highly doped n-type semiconducting material similar to the second layer. First and second electrical connections are provided to the fourth layer and to at least one of the first and second layers. A plurality of pairs of Dirac-delta doped monoatomic layers are in the third layer, with the first monoatomic layer of each pair being a layer of donors and with the second monoatomic layer of each pair being acceptors spaced from the donor layer and positioned on the side thereof facing the fourth layer.

Abstract: An optical switch comprises a heterojunction transistor having a source electrode, a gate, a mesa, and three self-aligned waveguides, the mesa being ion implanted and having a single quantum well under the gate electrode, the single quantum well being comprises of undoped, narrow bandgap material bound on both sides by regions p-doped, wide bandgap material, both of said p-doped regions have symmetrically graded bandgaps, being most narrow next to the quantum well and increasing out to a wide and constant value away from the quantum well. A highly n-doped and totally depleted charge sheet is placed in a wide bandgap material, very near the gate side of the quantum well heterojunction. The charge sheet serves to induce a voltage controllable inversion channel within the quantum well.

Abstract: A superheterojunction Field Effect Transistor (FET) with a multi-region channel on a Silicon (Si) substrate. The FET is a Metal Semiconductor FET (MESFET) or, alternatively, a Junction FET (JFET). The multi-region channel has: A first region of Si extending from the FET's source to a point under the FET's gate, beyond the gate's midpoint; a second region extending from the first region to the FET's drain, comprised of a superlattice of alternating Si and SiGe layers; and, a third region of Si extending under the first two regions from the source to the drain. The first region has a laterally graded dopant that creates an accelerating electric field. The superlattice structure increases electron mobility and transit velocity.

Abstract: The present invention is a method for making field effect devices, such as a field effect transistors, having ultrashort gate lengths so low as five hundred angstroms or less. In accordance with the invention the gate structure is grown vertically on a substrate by thin film deposition so that the length dimension of the gate is perpendicular to a major surface of the substrate. An edge of the gate-containing substrate is exposed, and the structure comprising the source, drain and channel is grown on the edge. Using this approach, field effect devices with precisely controlled gate lengths of less than 100 angstroms are achievable. Moreover the active regions of the device can be immersed within semiconductor material so that surface properties do not deteriorate device performance.

Abstract: A HEMT type semiconductor device includes a semiconductor substrate, a buffer semiconductor layer formed on the substrate, a first semiconductor well layer formed on the buffer layer and serving as a first conductivity type channel layer, a second semiconductor well layer formed on the first well layer and serving as a second conductivity type opposite the first conductivity, a channel layer and a potential barrier layer formed on the second well layer and forming a potential barrier for carriers. The substrate is made of GaAs or InP, and the layers are successively and epitaxially grown on the substrate. A two dimensional hole gas and a two dimensional electron gas are confined in the first well layer and in the second well layer, respectively.

Abstract: A quantum interference device in the form of a variable lateral confinement resonant tunneling transistor having a quantum waveguide structure including a primary current transmission path defined by a region between source and drain electrodes and where there is a resonance region therebetween in which quantum interference of tunneling wave functions establish a resonance tunneling condition that extends beyond the primary current path. Upon the application of a voltage across the drain and source electrodes, a tunneling current can be made to flow. A gate electrode formed on the quantum well structure remote from the primary current transmission path includes a variable depletion region thereunder or an electrostatic pinch off region, the size of which is a function of the magnitude of the bias voltage applied thereto.