Superlattice Patents (Class 257/15)
  • Patent number: 11908769
    Abstract: Example superlattice structures and methods for thermoelectric devices are provided. An example structure may include a plurality of superlattice periods. Each superlattice period may include a first material layer disposed adjacent to a second material layer. For each superlattice period, the first material layer may be formed of a first material and the second material layer may be formed of a second material. The plurality of superlattice periods may include a first superlattice period and a second superlattice period. A thickness of a first material layer of the first superlattice period may be different than a thickness of a first material layer of the second superlattice period.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: February 20, 2024
    Assignee: The Johns Hopkins University
    Inventors: Rama Venkatasubramanian, Jonathan M. Pierce, Geza Dezsi
  • Patent number: 11884854
    Abstract: The present invention relates to a method for producing core-shell nanocrystals consisting of a metal-containing nanocrystal core and a shell layer comprising at least one metal oxide material having variable shell thicknesses, and use of the core-shell nanocrystals for different applications.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: January 30, 2024
    Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
    Inventors: Anna Loiudice, Raffaella Buonsanti
  • Patent number: 11869942
    Abstract: A heteroepitaxial wafer comprises, in the following order: a silicon substrate having a diameter and a thickness; an AlN nucleation layer; a first strain building layer which is an AlzGal-zN layer having a first average Al content z, wherein 0<z; a first strain preserving block comprising ?5 and ?50 units of a first sequence of layers, the first sequence comprising an AlN layer and at least two AlGaN layers, and having a second average Al content y, wherein y a second strain building layer which is an AlxGal-xN layer having a third average Al content x, wherein 0?x<y; a second strain preserving block comprising ?5 and ?50 units of a second sequence of layers, the sequence comprising an AlN layer and at least one AlGaN layer, and having a fourth average Al content w, wherein x<w<y, and a GaN layer, wherein the layers between the AlN nucleation layer and the GaN layer form an AlGaN buffer.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: January 9, 2024
    Assignee: SILTRONIC AG
    Inventors: Sarad Bahadur Thapa, Martin Vorderwestner
  • Patent number: 11869968
    Abstract: A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: January 9, 2024
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Richard Burton, Yung-Hsuan Yang
  • Patent number: 11754865
    Abstract: A photonic integrated circuit comprises a silicon nitride waveguide, an electro-optic modulator formed of a III-nitride waveguide structure disposed on the silicon nitride waveguide, a dielectric cladding covering the silicon nitride waveguide and electro-optic modulator, and electrical contacts disposed on the dielectric cladding and arranged to apply an electric field to the electro-optic modulator.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: September 12, 2023
    Assignee: Raytheon BBN Technologies Corp.
    Inventors: Moe Soltani, Thomas Kazior
  • Patent number: 11652189
    Abstract: A display device includes a substrate, a plurality of pixels provided to the substrate, a plurality of light emitting elements provided to each of the pixels, and a cathode electrode covering the light emitting elements. The light emitting elements each include a p-type cladding layer, an active layer, an n-type cladding layer, and a high-resistance layer stacked in order on the substrate, sheet resistance of the high-resistance layer is higher than sheet resistance of the n-type cladding layer, an upper surface of the n-type cladding layer has a plurality of recesses, and the cathode electrode covers the high-resistance layer and is directly coupled to the recesses and a peripheral part of the n-type cladding layer.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: May 16, 2023
    Assignee: Japan Display Inc.
    Inventor: Masanobu Ikeda
  • Patent number: 11631584
    Abstract: A method for making a semiconductor device may include forming a superlattice above a semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include selectively etching the superlattice to remove semiconductor atoms and cause non-semiconductor atoms to accumulate and define an etch stop layer.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: April 18, 2023
    Assignee: ATOMERA INCORPORATED
    Inventors: Marek Hytha, Keith Doran Weeks, Nyles Wynn Cody
  • Patent number: 11621225
    Abstract: An electrical fuse matrix includes a plurality of anti-fuse structures, a plurality of top metal plates, and a plurality of bottom metal plates. The anti-fuse structures are arranged in a matrix, and each of the anti-fuse structure includes a top conductive structure, a bottom conductive structure, and a dielectric film disposed between the top conductive structure and the bottom conductive structure. The anti-fuse structure has an hourglass shape. The top metal plates are disposed on the top conductive structures. The bottom metal plates are disposed on the bottom conductive structures.
    Type: Grant
    Filed: September 6, 2020
    Date of Patent: April 4, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 11591466
    Abstract: The present application relates to a polymer composition comprising from 20 wt % to 30 wt % of a polycarbonate; from 40 wt % to 60 wt % of a polybutylene terephthalate; from 5 wt % to 30 wt % of a reinforcement fiber; from 1 wt % to 10 wt % of glass bubbles, and from 0.3 wt % to 2 wt % of transesterification inhibitor, all contents are based on the total weight of the composition. The polymer composition according to the present invention has improved adhesion to the metal (especially aluminum), even after annealing and anodizing processes are applied.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: February 28, 2023
    Assignee: Covestro Intellectual Property GmbH & Co. KG
    Inventors: Leith Wang, Xiaoxiang Wang
  • Patent number: 11387356
    Abstract: A semiconductor structure includes a seed layer on a substrate and an epitaxial stack on the seed layer. The epitaxial stack includes a first superlattice part and a second superlattice part on the first superlattice part. The first superlattice part includes first units repetitively stacked M1 times on the seed layer. Each first unit includes a first sub-layer that is an Aly1Ga1-y1N layer, and a second sub-layer that is an Alx1Ga1-x1N layer, wherein y1<x1. The second superlattice part includes second units repetitively stacked M2 times on the first superlattice part. Each second unit includes a third sub-layer that is an Aly2Ga1-y2N layer, and a fourth sub-layer that is an Alx2Ga1-x2N layer, wherein y2<x2. M1 and M2 are positive integers, 0?x1, y1 and y2<1, 0<x2?1, and x1<x2, or x1=x2 and y1<y2.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: July 12, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Yen Chen, Franky Juanda Lumbantoruan
  • Patent number: 11329154
    Abstract: A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: May 10, 2022
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Richard Burton, Yung-Hsuan Yang
  • Patent number: 11276796
    Abstract: Photovoltaic structures having multiple absorber layers separated by a diffusion barrier are provided. In one aspect, a method of forming an absorber on a substrate includes: depositing a first layer of light absorbing material on the substrate; depositing a diffusion barrier; depositing a second layer of light absorbing material on the diffusion barrier, wherein the first layer of light absorbing material has a different band gap from the second layer of light absorbing material; and annealing the absorber, wherein the diffusion barrier prevents diffusion of elements between the first layer of light absorbing material and the second layer of light absorbing material during the annealing. A solar cell and method for formation thereof are also provided.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: March 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Priscilla D. Antunez, Arthur W. Ellis, Richard A. Haight, James B. Hannon, Satoshi Oida
  • Patent number: 11257909
    Abstract: A stacked, high-blocking III-V semiconductor power diode having a first metallic terminal contact layer, formed at least in regions, and a highly doped semiconductor contact region of a first conductivity type and a first lattice constant. A drift layer of a second conductivity type and having a first lattice constant is furthermore provided. A semiconductor contact layer of a second conductivity, which includes an upper side and an underside, and a second metallic terminal contact layer are formed, and the second metallic terminal contact layer being integrally connected to the underside of the semiconductor contact layer, and the semiconductor contact layer having a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP, and the drift layer and the highly doped semiconductor contact region each comprising an InGaAs compound or being made up of InGaAs.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: February 22, 2022
    Assignees: AZUR SPACE Solar Power GmbH, 3-5 Power Electronics GmbH
    Inventors: Daniel Fuhrmann, Gregor Keller, Clemens Waechter, Volker Dudek
  • Patent number: 11031526
    Abstract: A semiconductor chip may include a semiconductor body, a current spreading layer, and a contact structure. The semiconductor body may include a first semiconductor layer, a second semiconductor layer, and an intervening active layer, and a current spreading layer arranged in a vertical direction between the contact structure and the semiconductor body. The semiconductor boy has a plurality of internal step configured in a terrace-like manner where the contact structure may include a plurality of conductor tracks arranged with regard to the lateral orientations of the internal step in such a way that current spreading along the internal steps is promoted vis-à-vis current spreading transversely with respect to the internal steps. A method for producing the semiconductor chip is also included.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: June 8, 2021
    Assignee: OSRAM OLED GmbH
    Inventor: Alexander Tonkikh
  • Patent number: 10910078
    Abstract: In a method of forming a one-time-programming (OTP) bit, a thin-film memory device is provided, which includes at least one memory element and a transistor, and the memory element is coupled to the transistor in series. Then, an alternating current is applied to the memory element and the transistor, the power applied to the memory element is constrained, and the transistor is turned on to change the resistance of the memory element for a plurality of cycles of the alternating current until the resistance of the memory element is irreversibly changed.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: February 2, 2021
    Assignee: NS Poles Technology Corp.
    Inventor: Yu Chou Ke
  • Patent number: 10873017
    Abstract: A thermoelectric generator includes a perovskite dielectric substrate containing Sr and Ti and having electric conductivity by being doped to n-type; an energy filter formed on a top surface of the perovskite dielectric substrate, the energy filter including a first perovskite dielectric film, which contains Sr and Ti, has electric conductivity by being doped to n-type, and has a conduction band at an energy level higher than that of the perovskite dielectric substrate; a first electrode formed in electrical contact with a bottom surface of the perovskite dielectric substrate; and a second electrode formed in electrical contact with a top surface of the energy filter. The thermoelectric generator produces a voltage between the first and second electrodes by the top surface of the energy filter being exposed to a first temperature and the bottom surface of the perovskite dielectric substrate being exposed to a second temperature.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: December 22, 2020
    Assignee: FUJITSU LIMITED
    Inventors: John David Baniecki, Masatoshi Ishii, Kazuaki Kurihara
  • Patent number: 10847619
    Abstract: An embodiment includes an apparatus comprising: a trench included in an insulation layer that is formed on a substrate, the trench having a top portion and a bottom portion between the top portion and the substrate; a first layer which comprises a first material and is included in the bottom portion; and a superlattice, in the trench and on the first layer, including second and third layers that directly contact each other; wherein: (a) the second and third layers respectively include second and third materials, (b) the second and third materials have different chemical compositions from each other, and (c) the first layer is thicker than each of the second and third. Other embodiments are described herein.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Cheng-Ying Huang, Matthew V. Metz, Willy Rachmady, Gilbert Dewey, Jack T. Kavalieros
  • Patent number: 10816703
    Abstract: A coating composition comprising 6 to 20 alternating layers of SiO2 and one of ZrO2 or Nb2O5 wherein the thickness of each individual layer is about 70 nm to 200 nm is described. Also described is a substrate comprising a coating on at least a first major side thereof, the coating comprising 6 to 20 alternating layers of SiO2 and one of ZrO2 or Nb2O5 wherein the thickness of each individual layer is about 70 nm to 200 nm. The substrate can be glass, plastic, or metal. Also disclosed herein are methods of making the coated substrate. The coatings have good optical transparency and NIR reflectivity.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: October 27, 2020
    Assignee: Tru Vue, Inc.
    Inventor: James C. DeCoux
  • Patent number: 10741994
    Abstract: A light emitter includes a substrate, a first mirror layer provided on the substrate, a columnar section including an active layer provided on a side of the first mirror layer that is the side opposite the substrate and a second mirror layer provided on a side of the active layer that is the side opposite the first mirror layer, a semi-insulating member provided on the side surface of the columnar section and having thermal conductivity higher than the thermal conductivity of the first mirror layer and the thermal conductivity of the second mirror layer, and a sub-mount which has a first surface bonded to the semi-insulating member and through which light produced in the active layer passes, and a second surface of the sub-mount that is the surface opposite the first surface is oriented in the direction in which the light produced in the active layer exits.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: August 11, 2020
    Assignee: Seiko Epson Corporation
    Inventor: Masamitsu Mochizuki
  • Patent number: 10700497
    Abstract: Provided is an optical semiconductor device including a laminate structural body 20 in which an n-type compound semiconductor layer 21, an active layer 23, and a p-type compound semiconductor layer 22 are laminated in this order. The active layer 23 includes a multiquantum well structure including a tunnel barrier layer 33, and a compositional variation of a well layer 312 adjacent to the p-type compound semiconductor layer 22 is greater than a compositional variation of another well layer 311. Band gap energy of the well layer 312 adjacent to the p-type compound semiconductor layer 22 is smaller than band gap energy of the other well layer 311. A thickness of the well layer 312 adjacent to the p-type compound semiconductor layer 22 is greater than a thickness of the other well layer 311.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: June 30, 2020
    Assignee: SONY CORPORATION
    Inventors: Masaru Kuramoto, Noriyuki Futagawa, Tatsushi Hamaguchi, Shoichiro Izumi
  • Patent number: 10586701
    Abstract: Semiconductor base including: silicon-based substrate; buffer layer including first and second layers alternately on silicon-based substrate, first layer made of nitride-based compound semiconductor containing first material, second layer made of nitride-based compound semiconductor containing second material having larger lattice constant than first material; channel layer on buffer layer and made of nitride-based compound semiconductor containing second material, buffer layer has: first composition graded layer between at least one of first layers and second layer immediately thereabove, made of nitride-based compound semiconductor whose composition ratio of second material is increased gradually upward, whose composition ratio of first material is decreased gradually upward; second composition graded layer between at least one of second layers and first layer immediately thereabove, made of nitride-based compound semiconductor whose first material is increased gradually upward, whose composition ratio of s
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: March 10, 2020
    Assignees: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroshi Shikauchi, Ken Sato, Masaru Shinomiya, Keitaro Tsuchiya, Kazunori Hagimoto
  • Patent number: 10580927
    Abstract: A process of forming a light-receiving device type of avalanche photodiode (APD) is disclosed. The process includes steps of: (1) growing semiconductor layers on a semiconductor substrate, the semiconductor layers providing a first area on a top thereof; (2) thermally diffusing impurities within the semiconductor layers in a second area outside of the first area so as to leave a roughed surface in a top of the second area, the impurities laterally diffusing to form an diffusion edge locating inside of the first area; and (3) removing the semiconductor layers including the roughed surface thereof in the second area to form a mesa in the first area, the mesa including the diffusion edge in a periphery thereof but excluding the roughed surface.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: March 3, 2020
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventors: Shin-ichi Domoto, Takumi Endo
  • Patent number: 10505087
    Abstract: A nitride semiconductor ultraviolet light-emitting element 1 comprises a sapphire substrate 10 and an element structure part 20 formed on a main surface 101 of the substrate 10. In the substrate 10, in a first portion 110 extending from the main surface 101 by a first distance, a sectional area of a cross section parallel to the main surface 101 continuously increases with distance from the main surface 101, and in a second portion 120 extending from a side opposite to the main surface 101 by a second distance, a sectional area of a cross section parallel to the main surface 101 continuously increases with distance from the side opposite to the main surface 101. The sum of the first distance and the second distance is equal to or less than the thickness of the substrate 10.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: December 10, 2019
    Assignee: SOKO KAGAKU CO., LTD.
    Inventors: Akira Hirano, Yosuke Nagasawa
  • Patent number: 10454006
    Abstract: A semiconductor structure including an anodic aluminum oxide layer is described. The anodic aluminum oxide layer can include a plurality of pores extending to an adjacent surface of the semiconductor structure. A filler material can penetrate at least some of the plurality of pores and directly contact the surface of the semiconductor structure. In an illustrative embodiment, multiple types of filler material at least partially fill the pores of the aluminum oxide layer.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: October 22, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Maxim S. Shatalov, Alexander Dobrinsky
  • Patent number: 10367332
    Abstract: An edge emitting laser light source and a three-dimensional (3D) image obtaining apparatus including the edge emitting laser light source are provided. The edge emitting laser light source includes a substrate; an active layer disposed on the substrate; a wavelength selection section comprising grating regions configured to select wavelengths of light emitted from the active layer; and a gain section configured to resonate the light having the selected wavelengths in a direction parallel with the active layer.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: July 30, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changyoung Park, Byunghoon Na, Yonghwa Park
  • Patent number: 10366918
    Abstract: After forming source/drain contact openings to expose portions of source/drain regions composed of an n-doped III-V compound semiconductor material, surfaces of the exposed portions of the source/drain regions are cleaned to remove native oxides and doped with plasma-generated n-type dopant radicals. Semiconductor caps are formed in-situ on the cleaned surfaces of the source/drain regions, and subsequently converted into metal semiconductor alloy regions. Source/drain contacts are then formed on the metal semiconductor alloy regions and within the source/drain contact openings.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Sebastian U. Engelmann, Marinus Johannes Petrus Hopstaken, Christopher Scerbo, Hongwen Yan, Yu Zhu
  • Patent number: 10361130
    Abstract: A method of forming fin structures that includes providing at least one silicon germanium containing fin structure, and forming a fin liner on the at least one silicon germanium containing fin structure. The fin liner includes a silicon germanium and oxygen containing layer. The method continues with annealing the at least on silicon germanium containing fin structure having the fin liner present thereon. During the annealing, the silicon germanium oxygen containing layer reacts with the silicon germanium containing fin structure to provide surface formation of a silicon rich layer on the silicon germanium containing fin structure.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee, Richard G. Southwick
  • Patent number: 10312390
    Abstract: A light receiving device includes a substrate having a principal surface and a back surface including a light receiving surface; a metal wire disposed on the principal surface, the metal wire including a bonding portion having an opening; and photodiodes that is arranged in an array on the substrate, each of the photodiodes including an electrode connected to the bonding portion of the metal wire and a semiconductor mesa including a stacked semiconductor layer, the stacked semiconductor layer including a first semiconductor layer disposed on the substrate, an optical absorption layer including a type-II superlattice structure, and a second semiconductor layer. Each of the electrodes of the photodiodes is disposed on a side surface of the semiconductor mesa in contact with the first semiconductor layer. The first semiconductor layer faces to the light receiving surface through the opening of the bonding portion.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: June 4, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Sundararajan Balasekaran, Daisuke Kimura
  • Patent number: 10297691
    Abstract: A semiconductor device is provided and includes a semiconductor fin protruding from a semiconductor substrate. The semiconductor fin includes plural pairs of semiconductor layers on the semiconductor substrate, each pair of semiconductor layers consists of a first semiconductor layer of a first conductivity type, and a second semiconductor layer of a second conductivity type. The second semiconductor layer is stacked on and contacts the first semiconductor layer.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: May 21, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Pin Chen, Chi-Cherng Jeng, Ru-Shang Hsiao, Li-Yi Chen
  • Patent number: 10276746
    Abstract: A hole supplier and p-contact structure for a light emitting device or a photodetector includes a p-type group III nitride structure and a hole supplier and p-contact layer made of Al-containing group III nitride formed on the p-type group III nitride structure and being under a biaxial in-plane tensile strain, the hole supplier and p-contact layer has a thickness in the range of 0.6-10 nm, and the p-type group III nitride structure is formed over an active region of the light emitting device or photodetector. A light emitting device and a photodetector with a hole supplier and p-contact structure.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: April 30, 2019
    Assignee: BOLB INC.
    Inventors: Jianping Zhang, Ying Gao, Ling Zhou
  • Patent number: 10204988
    Abstract: An apparatus comprising: a fermion source nanolayer (90); a first insulating nanolayer (92); a fermion transport nanolayer (94); a second insulating nanolayer (96); a fermion sink nanolayer (98); a first contact for applying a first voltage to the fermion source nanolayer; a second contact for applying a second voltage to the fermion sink nanolayer; and a transport contact for enabling an electric current via the fermion transport nanolayer. In a particular example, the apparatus comprises three graphene sheets (90, 94, 98) interleaved with two-dimensional Boron-Nitride (hBN) layers (92, 96).
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: February 12, 2019
    Assignee: Nokia Technologies Oy
    Inventor: Michael Astley
  • Patent number: 10170302
    Abstract: A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material. A collector and emitter are formed adjacent to the intrinsic base on opposite sides of the base. An extrinsic base structure is formed on the intrinsic base.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • Patent number: 10109984
    Abstract: Provided is an optical semiconductor device including a laminate structural body 20 in which an n-type compound semiconductor layer 21, an active layer 23, and a p-type compound semiconductor layer 22 are laminated in this order. The active layer 23 includes a multiquantum well structure including a tunnel barrier layer 33, and a compositional variation of a well layer 312 adjacent to the p-type compound semiconductor layer 22 is greater than a compositional variation of another well layer 311. Band gap energy of the well layer 312 adjacent to the p-type compound semiconductor layer 22 is smaller than band gap energy of the other well layer 311. A thickness of the well layer 312 adjacent to the p-type compound semiconductor layer 22 is greater than a thickness of the other well layer 311.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: October 23, 2018
    Assignee: SONY CORPORATION
    Inventors: Masaru Kuramoto, Noriyuki Futagawa, Tatsushi Hamaguchi, Shoichiro Izumi
  • Patent number: 10026868
    Abstract: A method is specified for producing an optoelectronic semiconductor component, comprising the following steps: A) providing a structured semiconductor layer sequence (21, 22, 23) having —a first semiconductor layer (21) with a base region (21c), at least one well (211), and a first cover region (21a) in the region of the well (211) facing away from the base surface (21c), —an active layer (23), and —a second semiconductor layer (22) on a side of the active layer (23) facing away from the first semiconductor layer (21), wherein —the active layer (23) and the second semiconductor layer (22) are structured jointly in a plurality of regions (221, 231) and each region (221, 231) forms, together with the first semiconductor layer (21), an emission region (3), B) simultaneous application of a first contact layer (41) on the first cover surface (21a) and a second contact layer (42) on a second cover surface (3a) of the emission regions (3) facing away from the first semiconductor layer (21) in such a way that —the fi
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: July 17, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Isabel Otto, Alexander F. Pfeuffer, Dominik Scholz
  • Patent number: 9984871
    Abstract: A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material. A collector and emitter are formed adjacent to the intrinsic base on opposite sides of the base. An extrinsic base structure is formed on the intrinsic base.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • Patent number: 9959947
    Abstract: A composite including: silicon (Si); a silicon oxide of the formula SiOx, wherein 0<x<2; and a graphene disposed on the silicon oxide.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: May 1, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Inhyuk Son, Hyunjae Song, Inyong Song, Jaeman Choi, Seungsik Hwang, Junhwan Ku, Jonghwan Park, Yeonji Chung
  • Patent number: 9946021
    Abstract: A method for fabricating a waveguide construction is described and has steps of: providing a layered structure by: forming a first-type InGaAsP layer on a substrate, forming a first-type InP layer on the first-type InGaAsP layer, forming an active layer containing gallium on the first-type InP layer, forming a second-type InP layer on the active layer, and forming a second-type InGaAsP layer on the second-type InP layer; forming an SiO2 patterned layer having SiO2 regions and at least one channel facing toward a desired direction and formed between the SiO2 regions on the second-type InGaAsP layer; and performing a rapid thermal annealing treatment on the layered structure formed with the SiO2 patterned layer. The rapid thermal annealing treatment has a treating temperature between 720° C. and 760° C. and a treating time between 60 and 240 seconds.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: April 17, 2018
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Yi-Jen Chiu, Po-Yun Wang, Wei Lin, Yang-Jeng Chen
  • Patent number: 9935202
    Abstract: To provide a transistor having a favorable electric characteristics and high reliability and a display device including the transistor. The transistor is a bottom-gate transistor formed using an oxide semiconductor for a channel region. An oxide semiconductor layer subjected to dehydration or dehydrogenation through heat treatment is used as an active layer. The active layer includes a first region of a superficial portion microcrystallized and a second region of the rest portion. By using the oxide semiconductor layer having such a structure, a change to an n-type, which is attributed to entry of moisture to the superficial portion or elimination of oxygen from the superficial portion, and generation of a parasitic channel can be suppressed. In addition, contact resistance between the oxide semiconductor layer and source and drain electrodes can be reduced.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: April 3, 2018
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Ryosuke Watanabe, Junichiro Sakata, Kengo Akimoto, Akiharu Miyanaga, Takuya Hirohashi, Hideyuki Kishida
  • Patent number: 9935185
    Abstract: A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material. A collector and emitter are formed adjacent to the intrinsic base on opposite sides of the base. An extrinsic base structure is formed on the intrinsic base.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • Patent number: 9911868
    Abstract: A nitride semiconductor device includes: a conductive substrate; a first nitride semiconductor layer which is formed on the substrate and contains Ga or Al; an electron supply layer which is formed in contact with the first nitride semiconductor layer and is made of a second nitride semiconductor having a different composition from that of the first nitride semiconductor layer in an interface between the electron supply layer and the first nitride semiconductor layer; and a source, a gate and a drain or an anode and a cathode which are formed on a front surface of the substrate, wherein the first nitride semiconductor layer has a thickness of w or more, a deep acceptor concentration distribution NDA(z) and a shallow acceptor concentration distribution NA(z), which satisfy the following equations (1) to (3): ? 0 w ? { E c ? ( x ) - ? 0 w ? q ? ( N DA ? ( z ) + N A ? ( z ) ) ? 0 ? ? ? dz } ? ? dz ? ? V b ( 1 ) E c ? ( x ) = 3.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: March 6, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Taketoshi Tanaka
  • Patent number: 9910220
    Abstract: Photonic integrated circuits on silicon are disclosed. By bonding a wafer of HI-V material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. The coupling between the silicon waveguide and the III-V gain region allows for integration of low threshold lasers, tunable lasers, and other photonic integrated circuits with Complimentary Metal Oxide Semiconductor (CMOS) integrated circuits.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: March 6, 2018
    Assignee: The Regents of the University of California
    Inventor: John E. Bowers
  • Patent number: 9899479
    Abstract: A semiconductor device may include a semiconductor substrate, and a plurality of field effect transistors (FETs) on the semiconductor substrate. Each FET may include a gate, spaced apart source and drain regions on opposite sides of the gate, upper and lower vertically stacked superlattice layers and a bulk semiconductor layer therebetween between the source and drain regions, and a halo implant having a peak concentration vertically confined in the bulk semiconductor layer between the upper and lower superlattices.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: February 20, 2018
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert J. Mears, Hideki Takeuchi
  • Patent number: 9859457
    Abstract: A template for a semiconductor device is made by providing an AGN substrate, growing a first layer of Group III nitrides on the substrate, depositing a thin metal layer on the first layer, annealing the metal such as gold so that it agglomerates to form a pattern of islands on the first layer; transferring the pattern into the first layer by etching then removing excess metal; and then depositing a second Group III nitride layer on the first layer. The second layer, through lateral overgrowth, coalesces over the gaps in the island pattern leaving a smooth surface with low defect density. A Group III semiconductor device may then be grown on the template, which may then be removed. Chlorine gas may be used for etching the pattern in the first layer and the remaining gold removed with aqua regia.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: January 2, 2018
    Assignee: Nitek, Inc.
    Inventors: Vinod Adivarahan, Asif Khan, Iftikhar Ahmad, Bin Zhang, Alexander Lunev
  • Patent number: 9831397
    Abstract: Fabricating a semiconductor structure including forming a nanocrystalline core from a first semiconductor material, forming a nanocrystalline shell from a second, different, semiconductor material that at least partially surrounds the nanocrystalline core, wherein the nanocrystalline core and the nanocrystalline shell form a quantum dot. Fabrication further involves forming an insulator layer encapsulating the quantum dot to create a coated quantum dot, and forming an additional insulator layer on the coated quantum dot using an Atomic Layer Deposition (ALD) process.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: November 28, 2017
    Assignee: Pacific Light Technologies Corp.
    Inventors: Brian Theobald, Matthew Bertram, Weiwen Zhao, Juanita N. Kurtin, Norbert Puetz
  • Patent number: 9773909
    Abstract: Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: September 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anirban Basu, Bahman Hekmatshoartabari, Davood Shahrjerdi
  • Patent number: 9607987
    Abstract: Methods are disclosed for forming fins in transistors. In one embodiment, a method of fabricating a device includes forming silicon fins on a substrate and forming a dielectric layer on the substrate and adjacent to the silicon fins such that an upper region of each silicon fin is exposed. Germanium may then be epitaxially grown germanium on the upper regions of the silicon fins to form germanium fins.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventors: Martin D. Giles, Tahir Ghani
  • Patent number: 9595810
    Abstract: Light emitting elements, and methods of producing the same, the light emitting elements including: a laminated structure, the laminated structure including a first compound semiconductor layer that includes a first surface and a second surface facing the first surface, an active layer that is in contact with the second surface of the first compound semiconductor layer, and a second compound semiconductor layer; where the first surface of the first compound semiconductor layer has a first surface area and a second surface area, the first and second surface areas being different in at least one of a height or a roughness, a first light reflection layer is formed on at least a portion of the first surface area, and a first electrode is formed on at least a portion of the second surface area.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: March 14, 2017
    Assignee: Sony Corporation
    Inventors: Tatsushi Hamaguchi, Masaru Kuramoto, Noriyuki Futagawa
  • Patent number: 9583566
    Abstract: An embodiment includes a heterojunction tunneling field effect transistor including a source, a channel, and a drain; wherein (a) the channel includes a major axis, corresponding to channel length, and a minor axis that corresponds to channel width and is orthogonal to the major axis; (b) the channel length is less than 10 nm long; (c) the source is doped with a first polarity and has a first conduction band; (d) the drain is doped with a second polarity, which is opposite the first polarity, and the drain has a second conduction band with higher energy than the first conduction band. Other embodiments are described herein.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: February 28, 2017
    Assignee: Intel Corporation
    Inventors: Uygar E. Avci, Dmitri E. Nikonov, Ian A. Young
  • Patent number: 9559196
    Abstract: A semiconductor wafer includes a base wafer, a first semiconductor portion that is formed on the base wafer and includes a first channel layer containing a majority carrier of a first conductivity type, a separation layer that is formed over the first semiconductor portion and contains an impurity to create an impurity level deeper than the impurity level of the first semiconductor portion, and a second semiconductor portion that is formed over the separation layer and includes a second channel layer containing a majority carrier of a second conductivity type opposite to the first conductivity type.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: January 31, 2017
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Naohiro Nishikawa, Tsuyoshi Nakano, Takayuki Inoue
  • Patent number: 9548377
    Abstract: Thermal treatment of a semiconductor wafer in the fabrication of integrated circuits including MOS transistors and ferroelectric capacitors, including those using lead-zirconium-titanate (PZT) ferroelectric material, to reduce variation in the electrical characteristics of the transistors. Thermal treatment of the wafer in a nitrogen-bearing atmosphere in which hydrogen is essentially absent is performed after formation of the transistors and capacitor. An optional thermal treatment of the wafer in a hydrogen-bearing atmosphere prior to deposition of the ferroelectric treatment may be performed.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: January 17, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kezhakkedath R. Udayakumar, Kemal Tamer San