Abstract: After forming source/drain contact openings to expose portions of source/drain regions composed of an n-doped III-V compound semiconductor material, surfaces of the exposed portions of the source/drain regions are cleaned to remove native oxides and doped with plasma-generated n-type dopant radicals. Semiconductor caps are formed in-situ on the cleaned surfaces of the source/drain regions, and subsequently converted into metal semiconductor alloy regions. Source/drain contacts are then formed on the metal semiconductor alloy regions and within the source/drain contact openings.

Abstract: An edge emitting laser light source and a three-dimensional (3D) image obtaining apparatus including the edge emitting laser light source are provided. The edge emitting laser light source includes a substrate; an active layer disposed on the substrate; a wavelength selection section comprising grating regions configured to select wavelengths of light emitted from the active layer; and a gain section configured to resonate the light having the selected wavelengths in a direction parallel with the active layer.

Abstract: A method of forming fin structures that includes providing at least one silicon germanium containing fin structure, and forming a fin liner on the at least one silicon germanium containing fin structure. The fin liner includes a silicon germanium and oxygen containing layer. The method continues with annealing the at least on silicon germanium containing fin structure having the fin liner present thereon. During the annealing, the silicon germanium oxygen containing layer reacts with the silicon germanium containing fin structure to provide surface formation of a silicon rich layer on the silicon germanium containing fin structure.

Abstract: A light receiving device includes a substrate having a principal surface and a back surface including a light receiving surface; a metal wire disposed on the principal surface, the metal wire including a bonding portion having an opening; and photodiodes that is arranged in an array on the substrate, each of the photodiodes including an electrode connected to the bonding portion of the metal wire and a semiconductor mesa including a stacked semiconductor layer, the stacked semiconductor layer including a first semiconductor layer disposed on the substrate, an optical absorption layer including a type-II superlattice structure, and a second semiconductor layer. Each of the electrodes of the photodiodes is disposed on a side surface of the semiconductor mesa in contact with the first semiconductor layer. The first semiconductor layer faces to the light receiving surface through the opening of the bonding portion.

Abstract: A semiconductor device is provided and includes a semiconductor fin protruding from a semiconductor substrate. The semiconductor fin includes plural pairs of semiconductor layers on the semiconductor substrate, each pair of semiconductor layers consists of a first semiconductor layer of a first conductivity type, and a second semiconductor layer of a second conductivity type. The second semiconductor layer is stacked on and contacts the first semiconductor layer.

Abstract: A hole supplier and p-contact structure for a light emitting device or a photodetector includes a p-type group III nitride structure and a hole supplier and p-contact layer made of Al-containing group III nitride formed on the p-type group III nitride structure and being under a biaxial in-plane tensile strain, the hole supplier and p-contact layer has a thickness in the range of 0.6-10 nm, and the p-type group III nitride structure is formed over an active region of the light emitting device or photodetector. A light emitting device and a photodetector with a hole supplier and p-contact structure.

Abstract: An apparatus comprising: a fermion source nanolayer (90); a first insulating nanolayer (92); a fermion transport nanolayer (94); a second insulating nanolayer (96); a fermion sink nanolayer (98); a first contact for applying a first voltage to the fermion source nanolayer; a second contact for applying a second voltage to the fermion sink nanolayer; and a transport contact for enabling an electric current via the fermion transport nanolayer. In a particular example, the apparatus comprises three graphene sheets (90, 94, 98) interleaved with two-dimensional Boron-Nitride (hBN) layers (92, 96).

Abstract: A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material. A collector and emitter are formed adjacent to the intrinsic base on opposite sides of the base. An extrinsic base structure is formed on the intrinsic base.

Abstract: Provided is an optical semiconductor device including a laminate structural body 20 in which an n-type compound semiconductor layer 21, an active layer 23, and a p-type compound semiconductor layer 22 are laminated in this order. The active layer 23 includes a multiquantum well structure including a tunnel barrier layer 33, and a compositional variation of a well layer 312 adjacent to the p-type compound semiconductor layer 22 is greater than a compositional variation of another well layer 311. Band gap energy of the well layer 312 adjacent to the p-type compound semiconductor layer 22 is smaller than band gap energy of the other well layer 311. A thickness of the well layer 312 adjacent to the p-type compound semiconductor layer 22 is greater than a thickness of the other well layer 311.

Abstract: A method is specified for producing an optoelectronic semiconductor component, comprising the following steps: A) providing a structured semiconductor layer sequence (21, 22, 23) having —a first semiconductor layer (21) with a base region (21c), at least one well (211), and a first cover region (21a) in the region of the well (211) facing away from the base surface (21c), —an active layer (23), and —a second semiconductor layer (22) on a side of the active layer (23) facing away from the first semiconductor layer (21), wherein —the active layer (23) and the second semiconductor layer (22) are structured jointly in a plurality of regions (221, 231) and each region (221, 231) forms, together with the first semiconductor layer (21), an emission region (3), B) simultaneous application of a first contact layer (41) on the first cover surface (21a) and a second contact layer (42) on a second cover surface (3a) of the emission regions (3) facing away from the first semiconductor layer (21) in such a way that —the fi

Abstract: A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material. A collector and emitter are formed adjacent to the intrinsic base on opposite sides of the base. An extrinsic base structure is formed on the intrinsic base.

Abstract: A composite including: silicon (Si); a silicon oxide of the formula SiOx, wherein 0<x<2; and a graphene disposed on the silicon oxide.

Abstract: A method for fabricating a waveguide construction is described and has steps of: providing a layered structure by: forming a first-type InGaAsP layer on a substrate, forming a first-type InP layer on the first-type InGaAsP layer, forming an active layer containing gallium on the first-type InP layer, forming a second-type InP layer on the active layer, and forming a second-type InGaAsP layer on the second-type InP layer; forming an SiO2 patterned layer having SiO2 regions and at least one channel facing toward a desired direction and formed between the SiO2 regions on the second-type InGaAsP layer; and performing a rapid thermal annealing treatment on the layered structure formed with the SiO2 patterned layer. The rapid thermal annealing treatment has a treating temperature between 720° C. and 760° C. and a treating time between 60 and 240 seconds.

Abstract: A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material. A collector and emitter are formed adjacent to the intrinsic base on opposite sides of the base. An extrinsic base structure is formed on the intrinsic base.

Abstract: To provide a transistor having a favorable electric characteristics and high reliability and a display device including the transistor. The transistor is a bottom-gate transistor formed using an oxide semiconductor for a channel region. An oxide semiconductor layer subjected to dehydration or dehydrogenation through heat treatment is used as an active layer. The active layer includes a first region of a superficial portion microcrystallized and a second region of the rest portion. By using the oxide semiconductor layer having such a structure, a change to an n-type, which is attributed to entry of moisture to the superficial portion or elimination of oxygen from the superficial portion, and generation of a parasitic channel can be suppressed. In addition, contact resistance between the oxide semiconductor layer and source and drain electrodes can be reduced.

Abstract: A nitride semiconductor device includes: a conductive substrate; a first nitride semiconductor layer which is formed on the substrate and contains Ga or Al; an electron supply layer which is formed in contact with the first nitride semiconductor layer and is made of a second nitride semiconductor having a different composition from that of the first nitride semiconductor layer in an interface between the electron supply layer and the first nitride semiconductor layer; and a source, a gate and a drain or an anode and a cathode which are formed on a front surface of the substrate, wherein the first nitride semiconductor layer has a thickness of w or more, a deep acceptor concentration distribution NDA(z) and a shallow acceptor concentration distribution NA(z), which satisfy the following equations (1) to (3): ? 0 w ? { E c ? ( x ) - ? 0 w ? q ? ( N DA ? ( z ) + N A ? ( z ) ) ? 0 ? ? ? dz } ? ? dz ? ? V b ( 1 ) E c ? ( x ) = 3.

Abstract: Photonic integrated circuits on silicon are disclosed. By bonding a wafer of HI-V material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. The coupling between the silicon waveguide and the III-V gain region allows for integration of low threshold lasers, tunable lasers, and other photonic integrated circuits with Complimentary Metal Oxide Semiconductor (CMOS) integrated circuits.

Abstract: A semiconductor device may include a semiconductor substrate, and a plurality of field effect transistors (FETs) on the semiconductor substrate. Each FET may include a gate, spaced apart source and drain regions on opposite sides of the gate, upper and lower vertically stacked superlattice layers and a bulk semiconductor layer therebetween between the source and drain regions, and a halo implant having a peak concentration vertically confined in the bulk semiconductor layer between the upper and lower superlattices.

Abstract: A template for a semiconductor device is made by providing an AGN substrate, growing a first layer of Group III nitrides on the substrate, depositing a thin metal layer on the first layer, annealing the metal such as gold so that it agglomerates to form a pattern of islands on the first layer; transferring the pattern into the first layer by etching then removing excess metal; and then depositing a second Group III nitride layer on the first layer. The second layer, through lateral overgrowth, coalesces over the gaps in the island pattern leaving a smooth surface with low defect density. A Group III semiconductor device may then be grown on the template, which may then be removed. Chlorine gas may be used for etching the pattern in the first layer and the remaining gold removed with aqua regia.

Abstract: Fabricating a semiconductor structure including forming a nanocrystalline core from a first semiconductor material, forming a nanocrystalline shell from a second, different, semiconductor material that at least partially surrounds the nanocrystalline core, wherein the nanocrystalline core and the nanocrystalline shell form a quantum dot. Fabrication further involves forming an insulator layer encapsulating the quantum dot to create a coated quantum dot, and forming an additional insulator layer on the coated quantum dot using an Atomic Layer Deposition (ALD) process.

Abstract: Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material.

Abstract: Methods are disclosed for forming fins in transistors. In one embodiment, a method of fabricating a device includes forming silicon fins on a substrate and forming a dielectric layer on the substrate and adjacent to the silicon fins such that an upper region of each silicon fin is exposed. Germanium may then be epitaxially grown germanium on the upper regions of the silicon fins to form germanium fins.

Abstract: Light emitting elements, and methods of producing the same, the light emitting elements including: a laminated structure, the laminated structure including a first compound semiconductor layer that includes a first surface and a second surface facing the first surface, an active layer that is in contact with the second surface of the first compound semiconductor layer, and a second compound semiconductor layer; where the first surface of the first compound semiconductor layer has a first surface area and a second surface area, the first and second surface areas being different in at least one of a height or a roughness, a first light reflection layer is formed on at least a portion of the first surface area, and a first electrode is formed on at least a portion of the second surface area.

Abstract: An embodiment includes a heterojunction tunneling field effect transistor including a source, a channel, and a drain; wherein (a) the channel includes a major axis, corresponding to channel length, and a minor axis that corresponds to channel width and is orthogonal to the major axis; (b) the channel length is less than 10 nm long; (c) the source is doped with a first polarity and has a first conduction band; (d) the drain is doped with a second polarity, which is opposite the first polarity, and the drain has a second conduction band with higher energy than the first conduction band. Other embodiments are described herein.

Abstract: A semiconductor wafer includes a base wafer, a first semiconductor portion that is formed on the base wafer and includes a first channel layer containing a majority carrier of a first conductivity type, a separation layer that is formed over the first semiconductor portion and contains an impurity to create an impurity level deeper than the impurity level of the first semiconductor portion, and a second semiconductor portion that is formed over the separation layer and includes a second channel layer containing a majority carrier of a second conductivity type opposite to the first conductivity type.

Abstract: Thermal treatment of a semiconductor wafer in the fabrication of integrated circuits including MOS transistors and ferroelectric capacitors, including those using lead-zirconium-titanate (PZT) ferroelectric material, to reduce variation in the electrical characteristics of the transistors. Thermal treatment of the wafer in a nitrogen-bearing atmosphere in which hydrogen is essentially absent is performed after formation of the transistors and capacitor. An optional thermal treatment of the wafer in a hydrogen-bearing atmosphere prior to deposition of the ferroelectric treatment may be performed.

Abstract: Provided is a field-effect transistor (FET) having small off-state current, which is used in a miniaturized semiconductor integrated circuit. The field-effect transistor includes a thin oxide semiconductor which is formed substantially perpendicular to an insulating surface, a gate insulating film formed to cover the oxide semiconductor, and a gate electrode which is formed to cover the gate insulating film. The gate electrode partly overlaps a source electrode and a drain electrode. The source electrode and the drain electrode are in contact with at least a top surface of the oxide semiconductor. In this structure, three surfaces of the thin oxide semiconductor are covered with the gate electrode, so that electrons injected from the source electrode or the drain electrode can be effectively removed, and most of the space between the source electrode and the drain electrode can be a depletion region; thus, off-state current can be reduced.

Abstract: A light-emitting device comprises a substrate comprising a top surface; a light-emitting stack formed on a portion of the top surface of the substrate; and a plurality of pores formed in an area of the substrate, wherein the area is under another portion of the top surface where the light-emitting stack is not formed thereon.

Abstract: In the present invention, a copper electrode having a nanohole structure is prepared by using a polymer substrate in the form of nanopillars in order to avoid fatigue fracture that causes degradation of electrical and mechanical properties of a flexible electrode during repetitive bending of a typical metal electrode. The nanohole structure may annihilate dislocations to suppress the initiation of fracture and may blunt crack tips to delay the propagation of damage. Therefore, the nanohole electrode exhibits very small changes in electrical resistance during a bending fatigue test.

Abstract: The present disclosure relates to an electromagnetic energy detector. The detector can include a substrate having a first refractive index; a metal layer; an absorber layer having a second refractive index and disposed between the substrate and the metal layer; a coupling structure to convert incident radiation to a surface plasma wave; additional conducting layers to provide for electrical contact to the electromagnetic energy detector, each conducting layer characterized by a conductivity and a refractive index; and a surface plasma wave (“SPW”) mode-confining layer having a third refractive index that is higher than the second refractive index disposed between the substrate and the metal layer.

Abstract: Methods for fabricating self-aligned heterostructures and semiconductor arrangements using silicon nanowires are described.

Abstract: A nitride semiconductor light-emitting element includes a second light-emitting layer, a third barrier layer, and a first light-emitting layer from a side close to a p-type nitride semiconductor layer. The first light-emitting layer includes a plurality of first quantum well layers and a first barrier layer provided between the plurality of first quantum well layers. The second light-emitting layer includes a plurality of second quantum well layers and a second barrier layer provided between the plurality of second quantum well layers. The second quantum well layers include a multiple quantum well light-emitting layer thicker than the first quantum well layers.

Abstract: Provided is an element structure whereby it is possible to produce a silicon-germanium light-emitting element enclosing an injected carrier within a light-emitting region. Also provided is a method of manufacturing the structure. Between the light-emitting region and an electrode there is produced a narrow passage for the carrier, specifically, a one-dimensional or two-dimensional quantum confinement region. A band gap opens up in this section due to the quantum confinement, thereby forming an energy barrier for both electrons and positive holes, and affording an effect analogous to a double hetero structure in an ordinary Group III-V semiconductor laser. Because no chemical elements other than those used in ordinary silicon processes are employed, the element can be manufactured inexpensively, simply by controlling the shape of the element.

Abstract: An analyte measuring device (5) for monitoring, for example, levels of a tissue analyte (e.g., bilirubin), includes a number of narrow band light sources (10), each narrow band light source being structured to emit a spectrum of light covering a number of wavelengths, and a number of detector assemblies (15) configured to receive light reflected from the transcutaneous tissues of a subject. Each of the detector assemblies includes a filter (20) and a photodetector (25), each filter being structured to transmit a main transmission band and one or more transmission sidebands, wherein for each narrow band light source the spectrum thereof includes one or more wavelengths that fall within the transmission band of at least one of the filters, and wherein for each narrow band light source the spectrum thereof does not include any wavelengths that fall within the one or more transmission sidebands of any of the optical filters.

Abstract: The present disclosure provides a thermoelectric element comprising a flexible semiconductor substrate having exposed surfaces with a metal content that is less than about 1% as measured by x-ray photoelectron spectroscopy (XPS) and a figure of merit (ZT) that is at least about 0.25, wherein the flexible semiconductor substrate has a Young's Modulus that is less than or equal to about 1×106 pounds per square inch (psi) at 25° C.

Abstract: A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure straddling the semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask, At least one semiconductor shell layer or a semiconductor cap layer can be formed as an etch stop structure. A planarization dielectric layer is subsequently formed. A gate cavity is formed by removing the disposable gate structure. A portion of the second semiconductor material is removed selective to the first semiconductor material within the gate cavity so that a middle portion of the semiconductor fin becomes suspended over the substrate. A gate dielectric layer and a gate electrode are sequentially formed. The gate electrode laterally surrounds a body region of a fin field effect transistor.

Abstract: A light extraction substrate which can realize a superior light extraction efficiency when applied to an organic light-emitting device, and an organic light-emitting device having the same. The light extraction substrate includes a base substrate and a matrix layer. One surface of the matrix layer adjoins to the base substrate, and the other surface of the matrix layer adjoins to an organic light-emitting diode. The light extraction substrate also includes a rod array disposed inside the matrix layer. The rod array includes at least one rod which is arranged in a direction normal to the one surface of the matrix layer. The rod array and a cathode of the organic light-emitting diode form an antenna structure which guides light generated from the organic light-emitting diode to be emitted in the normal direction.

Abstract: A dual-band infrared detector is provided. The dual-band infrared detector includes a first absorption layer, a barrier layer coupled to the first absorption layer, and a second absorption layer coupled to the barrier layer. The first absorption layer is sensitive to only a first infrared wavelength band and the second absorption layer is sensitive to only a second infrared wavelength band that is different from the first infrared wavelength band. The dual-band infrared detector is capable of detecting the first wavelength band and the second wavelength band by applying a first bias voltage of a first polarity to the first absorption layer and by applying a second bias voltage of a second polarity that is opposite the first polarity to the second absorption layer, wherein the first bias voltage and the second bias voltage each have a magnitude of less than about 500 mV.

Abstract: An amorphous form of cabazitaxel is disclosed. It is preferably characterized by an X-ray powder diffraction (XRD) pattern as depicted in FIG. 1. It is prepared by (a) preparing a solution of cabazitaxel in a suitable solvent and mixture thereof; and (b) recovering the amorphous forms of cabazitaxel from the solution by removal of the solvent.

Abstract: An optical device is provided including an active layer having two outer barriers and a coupled quantum well between the two outer barriers. The coupled quantum well includes a first quantum well layer, a second quantum well layer, a third quantum well layer, a first coupling barrier between the first quantum well layer and the second quantum well layer, and a second coupling barrier between the second quantum well layer and the third quantum well layer. A thickness of the first quantum well layer and a thickness of the third quantum well layer are each different from a thickness of the second quantum well layer. Also, an energy level of the first quantum well layer and an energy level of the third quantum well layer are each different from an energy level of the second quantum well layer.

Abstract: A nitride semiconductor wafer includes a silicon substrate, a first layer, a second layer, a third layer, a fourth layer, a fifth layer, and a sixth layer. The first layer is provided on the silicon substrate. The second layer is provided on the first layer. The third layer is provided on the second layer. The fourth layer is provided on the third layer. The fifth layer is provided on the fourth layer. The sixth layer is provided on the fifth layer. A composition ratio x4 of the fourth layer decreases in a first direction from the third layer toward the fifth layer. A maximum value of the composition ratio x4 is not more than a composition ratio of the third layer. A minimum value of the composition ratio x4 is not less than a composition ratio of the fifth layer.

Abstract: According to one embodiment, a semiconductor light emitting device includes an electrode layer, a first semiconductor layer, a first elongated electrode, a second semiconductor layer, and a light emitting layer. The first semiconductor layer includes a crystal having a cleavage plane. The first semiconductor layer includes a first thin film portion and a thick film portion. The first thin film portion extends in a first direction perpendicular to a stacking direction from the electrode layer toward the first semiconductor layer. The first thin film portion has a first thickness. The thick film portion is arranged with the first thin film portion in a plane perpendicular to the stacking direction. An angle between the first direction and the cleavage plane is not less than 3 degrees and not more than 27 degrees. The first elongated electrode extends in the first direction in contact with the first thin film portion.

Abstract: A junction transistor, comprising, on a substrate an emitter layer, a collector layer, and a base layer that comprises a graphene layer, wherein an emitter barrier layer is arranged between the base layer and the emitter layer, and a collector barrier layer is arranged between the base and the collector layers and adjacent to the graphene layer, characterized in that the collector barrier layer is a compositionally graded material layer, which has an electron affinity that decreases in a direction pointing from the base layer to the collector layer.

Abstract: A semiconductor light emitting device includes a first nitride semiconductor layer, a dopant doped semiconductor layer on the first nitride semiconductor layer, an active layer on the dopant doped semiconductor layer, a delta doped layer on the active layer, a superlattice structure on the delta doped layer, an undoped layer on the superlattice layer, a second nitride semiconductor layer including a first n-type dopant, a third nitride semiconductor layer including a second n-type dopant, and a fourth nitride semiconductor layer including a third n-type dopant.

Abstract: Transistors, and methods of manufacturing the transistors, include graphene and a material converted from graphene. The transistor may include a channel layer including graphene and a gate insulating layer including a material converted from graphene. The material converted from the graphene may be fluorinated graphene. The channel layer may include a patterned graphene region. The patterned graphene region may be defined by a region converted from graphene. A gate of the transistor may include graphene.

Abstract: Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heat dissipation substrate (that is, a thermal conductive substrate); a GaN-based multi-layer arranged on the heat dissipation substrate and having N-face polarity; and a heterostructure field effect transistor (HFET) or a Schottky electrode arranged on the GaN-based multi-layer. The HFET device may include a gate having a double recess structure. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used.

Abstract: The invention provides a Group III nitride semiconductor light-emitting device in which the strain in the light-emitting layer is relaxed, thereby attaining high light emission efficiency, and a method for producing the device. The light-emitting device of the present invention has a substrate, a low-temperature buffer layer, an n-type contact layer, a first ESD layer, a second ESD layer, an n-side superlattice layer, a light-emitting layer, a p-side superlattice layer, a p-type contact layer, an n-type electrode N1, a p-type electrode P1, and a passivation film F1. The second ESD layer has pits X having a mean pit diameter D. The mean pit diameter D is 500 ? to 3,000 ?. An InGaN layer included in the n-side superlattice layer has a thickness Y satisfying the following condition: ?0.029×D+82.8?Y??0.029×D+102.8.

Abstract: A light emitting device and method for making the same is disclosed. The light-emitting device includes an active layer sandwiched between a p-type semiconductor layer and an n-type semiconductor layer. The active layer emits light when holes from the p-type semiconductor layer combine with electrons from the n-type semiconductor layer therein. The active layer includes a number of sub-layers and has a plurality of pits in which the side surfaces of a plurality of the sub-layers are in contact with the p-type semiconductor material such that holes from the p-type semiconductor material are injected into those sub-layers through the exposed side surfaces without passing through another sub-layer. The pits can be formed by utilizing dislocations in the n-type semiconductor layer and etching the active layer using an etching atmosphere in the same chamber used to deposit the semiconductor layers without removing the partially fabricated device.

Abstract: A semiconductor chip includes a semiconductor body with a semiconductor layer sequence. An active region intended for generating radiation is arranged between an n-conductive multilayer structure and a p-conductive semiconductor layer. A doping profile is formed in the n-conductive multilayer structure which includes at least one doping peak.

Abstract: According to one embodiment, a semiconductor light emitting device includes: a first semiconductor layer; a second semiconductor layer; and a light emitting layer provided between the first and the second semiconductor layers. The first semiconductor layer includes a nitride semiconductor, and is of an n-type. The second semiconductor layer includes a nitride semiconductor, and is of a p-type. The light emitting layer includes: a first well layer; a second well layer provided between the first well layer and the second semiconductor layer; a first barrier layer provided between the first and the second well layers; and a first Al containing layer contacting the second well layer between the first barrier layer and the second well layer and containing layer containing Alx1Ga1-x1N (0.1?x1?0.35).