Abstract: A circuit element comprises an acoustic charge transport device comprising an input, a barrier element and an output. A transistor assembly comprises a source, a gate and a drain. One of the input, output and barrier elements is operably connected with one of the source, drain and gate.
Abstract: A non-linear optical device utilizes laterally asymmetrical quantum dot structures (D1-D5) that are tunable in terms of their lateral asymmetry by bias potentials (V1, V2) applied to laterally extending electrode structures (13, 14).
Abstract: A quantum well structure having a host optical phonon confinement well (11) having a characteristic phonon distribution (16), and at least one charge carrier confinement well (17) located near a minima of the phonon distribution (16). In one embodiment, a wide bandgap layer (13) is formed in a central portion of the host optical phonon confinement well (11), wherein the wide bandgap layer (13) has phonon properties closely matching that of the host phonon confinement well (11).
Abstract: A photo-detector for detecting a light having a predetermined photon energy, comprises: a semiconductor member having a source region, a gate region and a drain region; a first path for propagating an electron wave from the source region to the drain region through the gate region; a second path for propagating an electron wave from the source region to the drain region through the gate region; the second path being of quantum well structure or a quantum line structure and having a plurality of electron levels having an energy difference therebetween slightly smaller or slightly larger than the photon energy of the light to be detected; a wave function of the electron wave propagating through the second path being coupled with a wave function of the electron wave propagating through the first path in the source region and the drain region and separated from the wave function of the electron wave propagating through the first path in the gate region; means for applying a voltage across the source region and th
Abstract: A quantum semiconductor device has a semiconductor substrate, a plurality of quantum boxes formed adjacent to one another in the semiconductor substrate, and a quantum level control unit for changing the effective size of at least one of the quantum boxes, to thereby change the quantum level of each of the quantum boxes. Consequently, according to the present invention, an influence of charges due to peripheral impurities is small, and thereby a compact quantum semiconductor device can be provided. Further, according to the present invention, a highly integrated high-speed switching circuit can be provided.
Abstract: A multiple quantum well arrangement which achieves significantly improved third order optical nonlinearity in a semiconductor device by way of spatially periodic electrodes applied to the semiconductor device. The spatial period of the applied electrodes and the resulting exciton confinement dimension is improved over that of previous multiple quantum well structures and to the Bohr radius range of dimensions for the semicondcutor material by way of avRIGHTS OF THE GOVERNMENTThe invention described herein may be manufactured and used by or for the Government of the United States for all governmental purposes without the payment of any royalty.
Type:
Grant
Filed:
May 4, 1992
Date of Patent:
December 28, 1993
Assignee:
The United States of America as represented by the Secretary of the Air Force
Inventors:
Frank K. Hopkins, Joseph T. Boyd, Howard E. Jackson
Abstract: A velocity modulation transistor has a first barrier layer, first channel layer, second barrier layer, second channel layer, third barrier layer, input/output electrode that and control electrode are laminated on a semi-insulative substrate in this order, The electron affinity of the first channel layer is larger than that of the second channel layer. The energy difference between the first level and the second level can be obtained according to the difference in the electron affinity between the first and second channel layers as well as to the control of the film thickness of the first and second channel layers, whereby the velocity modulation effect at room temperature becomes large.
Abstract: A field effect transistor comprising first and second electrodes, semiconductor layers connected to these electrodes to form a carrier channel between them and a control electrode is provided. Said semiconductor layers consisting essentially of: (a) a first semiconductor layer of a first semiconductor material having a low density of state of carrier formed on a substrate, (b) a second semiconductor layer of a second semiconductor material containing an impurity element and having a high density of state of carrier formed on the first semiconductor layer, and (c) a third semiconductor layer of a third semiconductor material having a low density of state of carrier formed on the second semiconductor layer, wherein the impurity element contained in the second semiconductor layer is of n-type when the carrier is an electron or of p-type when the carrier is a hole.
Abstract: A field effect semiconductor device having multiple vertically stacked channels (12, 14, 16) separated by independent gate electrodes (13, 15) is provided. The channels (12, 14, 16) are formed on a wide bandgap buffer layer (11) and each channel is coupled a drain electrode (21). Each channel is also coupled to a source electrode (25-26). The quantum well channels (12, 14, 16) and quantum well gates (13, 15) are separated from each other by barrier layers (18) of a wide bandgap semiconductor material.
Type:
Grant
Filed:
June 16, 1992
Date of Patent:
June 22, 1993
Assignee:
Motorola, Inc.
Inventors:
Herbert Goronkin, Jun Shen, Saied Tehrani, X. Theodore Zhu
Abstract: The present invention is a method for making field effect devices, such as a field effect transistors, having ultrashort gate lengths so low as five hundred angstroms or less. In accordance with the invention the gate structure is grown vertically on a substrate by thin film deposition so that the length dimension of the gate is perpendicular to a major surface of the substrate. An edge of the gate-containing substrate is exposed, and the structure comprising the source, drain and channel is grown on the edge. Using this approach, field effect devices with precisely controlled gate lengths of less than 100 angstroms are achievable. Moreover the active regions of the device can be immersed within semiconductor material so that surface properties do not deteriorate device performance.
Type:
Grant
Filed:
August 15, 1991
Date of Patent:
June 15, 1993
Assignee:
AT&T Bell Laboratories
Inventors:
Kirk W. Baldwin, Loren N. Pfeiffer, Horst L. Stormer, Kenneth W. West
Abstract: An optically bistable semiconductor device which has a doped or undoped gallium arsenide substrate and a series of alternating n-type and p-type Dirac-delta doped monoatomic layers formed on the substrate. Each Dirac-delta doped monoatomic layer is separated from the next adjacent Dirac-delta doped monoatomic layer by a layer of pure, undoped intrinsic semiconductor material such as gallium arsenide.
Type:
Grant
Filed:
June 27, 1991
Date of Patent:
June 1, 1993
Assignee:
Max-Planck Gesellschaft zur Foerderung der Wissenschaften e.V.
Inventors:
Erdmann Schubert, Klaus Ploog, Albrecht Fischer
Abstract: A quantum well structure useful for semiconducting devices comprises two barrier regions and a thin epitaxially grown monocrystalline semiconductor material quantum well sandwiched between said barrier regions. Each barrier region consists essentially of alternate strain layers forming a superlattice, each of said layers being thinner than said quantum well. The layers are so thin that no defects are generated as a result of the release of stored strain energy.
Abstract: A heterojunction semiconductor device utilizing a quantum-mechanical effect comprises a first compound semiconductor (e.g., AlGaAs) layer and a second compound semiconductor (e.g., GaAs) layer having an electron affinity different from that of the first semiconductor layer, and the first and second compound semiconductor layers forming a heterojunction interface therebetween, the first layer having an energy at the conduction band bottom thereof higher than that of the second layer and doped with donor impurities, wherein at least one concave or convex portion of the first semiconductor layer is formed at the heterojunction interface and both sides of the concave or convex portion serve as a potential well or potential barriers against electrons accumulated in the second semiconductor layer close to the vicinity of the heterojunction interface.