Abstract: The memory cells are arranged to all intersections of the first word line and one line of the bit-line pair and all intersections of the second word line and the other line of the bit-line pair by arranging in parallel the first word line and the second word line consisting of different layers in the row direction with the identical pitch and also alternately arranging the first word line and the second word line at an interval equal to a half of the pitch in the horizontal direction. Moreover, the selection MISFET of the memory cell is formed in the vertical construction and the bit line located at the upper side of the substrate where a channel region is formed is shielded with a conductive film, a part of which forms the gate electrode.

Abstract: The present invention relates to chip assembly with a ball array capacitance minimizing layout that includes a ball array disposed upon a substrate with trace routing laid out between each ball pad and a respective bond wire pad. After routing of both signal and ground traces between the ball pads and their respective bond wire pads, at least one buffer trace is also disposed upon the substrate as a closed loop. The buffer trace may or may not be connected to ground. Preferably, buffer traces are configured to reduce the capacitance of the highest capacitance ball pads. This is accomplished by placing more of a give buffer trace around the perimeter of a higher capacitance ball pad, than around the perimeter of a lower capacitance ball pad. Accordingly, a capacitance difference between a higher capacitance ball pad and signal trace and a lower capacitance ball pad and signal trace can be minimized according to the present invention.

Abstract: The present invention relates to metallization line layouts that minimize focus offset sensitivity by a substantial elimination of thin isolated metallization line segments that are inadequately patterned during formation of a mask. The present invention also relates to a metallization line layout that staggers unavoidable exposures. Embodiments of these metallization line layouts include enhanced terminal ends of isolated metallization lines, filled inter-metallization line spaces, and additional “dummy” metal shapes in open areas.

Abstract: A semiconductor integrated circuit disclosed herein are characterized in that: (a) each chip is reduced in size by having electrode pads formed in a plurality of rows, the small-size chip being used to form a small ordinary package; (b) frame wires inside the package are used to interconnect electrode pads and electrode bumps in different manners so that chips are furnished in common, whereby a small-size mirror package is formed; (c) frame wires on one side are arranged to pass alternately between contiguous electrode pads and/or between contiguous frame wires on the other side in order to further reduce common chips in size, whereby electrode pads are formed in a larger number of rows; (d) a substrate is sandwiched by the CSPs thus obtained so as to at least double packaging density; and (e) switches or fuses are provided in layered connection wires inside the chip so that after package fabrication, the manner of interconnecting the internal circuits of the chip and the electrode pads thereof may be changed

Abstract: A structure is disclosed for a multi-finger transistor with improved high frequency performance. An array of isolated active regions is formed in a semiconductor substrate. A source region and a drain region are formed in each of the active regions and are disposed on either side of a central channel region. A gate oxide layer is formed over each channel region. Conductive gate fingers that extend over the gate oxide layers and also beyond the active areas are formed so that each gate finger constitutes a continuous conductive line providing and connecting the gates of the plurality of active regions. A dielectric layer is formed over the active regions and over the surrounding isolation regions. A conductive via is formed through the dielectric layer to each source region and to each drain region. For each gate finger or conductive via is opened between the active region and at both ends of the finger contact region is formed over each conductive via.

Abstract: An integrated circuit comprises an array of standard cell logic having spare gate logic dispersed therein. The spare gate logic is connectable to the standard cell logic through upper level conductors. This allows the design of an integrated circuit to be changed by changing the pattern of the upper level conductors, thereby lowering the cost of making a design change and reducing the disturbance of the original wiring. In an illustrative embodiment, the top two or three metal levels and associated vias are mask-programmable for this purpose. The interconnections from the mask-programmable upper levels to the underlying standard cell logic is accomplished using a regular array of conductor vias interspersed throughout the standard cell array, plus elevated output terminal which create a loop structure completed by the program levels. This allows output terminal loops of the standard cells to be brought up to the mask-programmable metal levels for removal of any standard cell logic.

Abstract: A semiconductor read-only memory configuration in which two intermediate cell halves are directly adjacent to one another perpendicularly to the longitudinal direction of a word line and are periodically repeated in the longitudinal direction of the word line. In a first intermediate cell half, the polycrystalline silicon of the word lines is ruptured and a substrate contact is set, and in a second intermediate cell half, the polycrystalline silicon is refreshed. These intermediate cell halves are adjacent to one another, and the first and the second intermediate cell halves are alternately interchanged. Instead of requiring two intermediate cells, the semiconductor read-only memory configuration requires just one intermediate cell that includes the two intermediate cell halves which are used in an alternately mirrored manner.

Abstract: A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6F2 or smaller memory cells in a type of cross point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.

Abstract: The present invention discloses a semiconductor memory device having a bit line and a metal contact stud, wherein the metal contact stud is formed on a different layer from a layer on which the bit lines are formed.

Abstract: A hybrid HardWire device is provided that comprises a gate array core and a set of mask programmable I/O cells having I/O characteristics similar to those of an FPGA, i.e., sufficiently the same so the HardWire device can be used as a drop-in replacement for the FPGA with no redesign of the original system. Using this HardWire device, a user's design originally implemented in an FPGA can be emulated in the HardWire device, which then replaces the FPGA in the same board at a lower cost. In another embodiment, the I/O cells are mask programmable such that they can emulate the I/O characteristics of FPGAs from any of two or more FPGA families. This ability reduces the number of separate HardWire devices that must be designed, manufactured, tested, stored, and sold, and also simplifies the software required to convert designs to the new device. Some embodiments of the invention can also emulate other programmable devices such as PLDs.

Abstract: An integrated circuit includes a substrate of semiconductor material having a periphery and a geometric center, a plurality of circuits formed on the substrate, and a power bus grid electrically coupled to the plurality of circuits. The power bus grid is formed of a plurality of power bus straps having a strap density that progressively varies with distance from the geometric center toward the periphery.

Abstract: In a semiconductor integrated circuit device comprising electrodes, loop wires, an input/output circuit, and an internal circuit arranged in order from a peripheral portion to a central portion of a substrate, and a pair of power wires each having a path from an associated one of the electrodes to the internal circuit through an associated loop wire. The pair of power wires are routed such that a connecting point of the one power wire from the associated loop wire to the internal wire corresponds to a connecting point of the other power wire from the associated loop wire to the internal wire, and the connecting point of the other power wire from the loop wire to the internal circuit corresponds to a connecting point of the one power wire from the associated electrode to the associated loop wire.

Abstract: A feedthrough cell or cap cell includes a basic pair of a gate electrode and pairs of P-type diffused regions and N-type diffused regions. With this structure, even if a design change arises after the completion of a layout plan, a logic circuit can be formed from the basic pair; hence, the design change can be flexibly handled.

Abstract: A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments (204a-204h). The lower conductive segments (204a-204h) are arranged in an “open” configuration, allowing adjacent unit circuits (202) be accessed simultaneously. The lower conductive segments (204a-204h) are coupled to higher conductive segments (208a-208f) by reconnector circuits (210a and 210b). The higher conductive segments (208a-208f) are arranged into folded pairs (208a/208d, 208b/208e and 208c/208f) between differential-type amplifiers (212a and 212b). The reconnector circuits (210a and 210b) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (210a and 210b) couple adjacent folded higher conductive segment pairs to one another.

Abstract: A semiconductor integrated circuit device has core circuits having rectangular shapes in plan view and power lines surronding the core circuit to connect the cores with an external power supply. The power lines are constructed in a plurality of interconnection layers and include interlayer connections so that they have overlapping parts. Interconnections between core circuits are commonly used so as to decrease interconnection area.

Abstract: A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.

Abstract: To form a driver circuit to be mounted to a liquid crystal display device or the like on a glass substrate, a quartz substrate, etc., and to provide a display device mounting driver circuits formed from different TFTs suited for their respective operational characteristics. A stick driver circuit on the scanning line side and a stick driver circuit on the data line side are different in structure, and have different TFTs in which the thickness of a gate insulating film, the channel length and other parameters are varied depending on required circuit characteristics. In the stick driver on the scanning line side, which is composed of a shift register circuit, a level shifter circuit, and a buffer circuit, the buffer circuit has a TFT with a thick gate insulating film because it is required to have a withstand voltage of 30 V.

Abstract: The present invention relates to chip assembly with a ball array capacitance minimizing layout that includes a ball array disposed upon a substrate with trace routing laid out between each ball pad and a respective bond wire pad. After routing of both signal and ground traces between the ball pads and their respective bond wire pads, at least one buffer trace is also disposed upon the substrate as a closed loop. The buffer trace may or may not be connected to ground. Preferably, buffer traces are configured to reduce the capacitance of the highest capacitance ball pads. This is accomplished by placing more of a give buffer trace around the perimeter of a higher capacitance ball pad, than around the perimeter of a lower capacitance ball pad. Accordingly, a capacitance difference between a higher capacitance ball pad and signal trace and a lower capacitance ball pad and signal trace can be minimized according to the present invention.

Abstract: An embodiment of the present invention discloses a memory device having an array with digit lines arranged in complementary pairs, the array comprising; a substantially planar layer having trenches therein; a first level of digit lines residing at least partially in the trenches; a second level of digit lines residing on the surface of the layer, the second level extending in generally parallel relation to the digit lines in the first level. The first level of digit lines are in alternating positions with the second level of digit lines and the alternating positions comprise a repeating pattern of a first complementary pair of digit lines at the first level adjacent a second complementary pair of digit lines at the second level.

Abstract: A semiconductor device capable of making an interstitial space between adjacent two of pads and thereby decreasing a chip size without arising the difference of accessing speeds between banks. The semiconductor device has a center bonding structure including plural memory arrays (101 in FIG. 1), first peripheral circuit element groups (102 in FIG. 1) including amplifying circuit element, driving circuit element and the like which require to be arranged in symmetry relative to center bonding pads, second peripheral circuit element groups (103 in FIG. 1) including input/output circuit element, logic circuit element and the like which do not require the symmetrical arrangement, and pads (104 in FIG. 1). The second peripheral circuit element groups are essentially positioned on one side relative to the sequence of the pads.

Abstract: An integrated circuit having a memory cell array in which the strapping of cell components is accomplished within a memory cell. In one embodiment the strapping 750, 752, 756 is placed between the moats 706,724 of transistors that compose cross-coupled inverters within a static random access memory cell.

Abstract: In a semiconductor integrated circuit device, at least one I/O cell can be disposed in a desired position within a chip. The semiconductor integrated circuit device includes an ESD protection circuit separated from the I/O cell and disposed in an ESD protection circuit region provided in a peripheral portion of the chip; the I/O cell disposed closer to the center of the chip than the ESD protection circuit region; and a wire for connecting the I/O cell to the ESD protection circuit.

Abstract: The semiconductor memory device of the present invention comprises: memory cells arranged in a matrix; word lines extending in a row direction; bit line pairs extending in a column direction; exchange blocks for exchanging the bit lines of the different neighboring bit line pairs.

Abstract: An MCP has an MCP substrate, first and second semiconductor chips mounted on the MCP substrate, MCP leads connected to perimeter of the MCP substrate. MCP terminal wires disposed on the MCP substrate connect the MCP leads to the first semiconductor chip. Interface signal wires disposed on the MCP substrate connect the first and second semiconductor chips to each other. The MCP further has first and second extra bonding pads. The first extra bonding pad electrically connects to the interface signal wires. The second extra bonding pad electrically connects to the MCP leads. The second extra bonding pad is arranged near the first extra bonding pad. The first and second extra bonding pads are designed to be electrically isolated from each other in a normal usage condition. However, the first and second extra bonding pads are electrically connected to each other when failure analysis is required.

Abstract: A layout structure of a semiconductor memory device having a memory cell array region, a word line drive region proximate the memory cell array, a bit line equalization region spaced apart from the memory cell array region, an impurity region formed between the memory cell array region and the bit line equalization region electrically coupled to the bit line equalization region, and a metal line extending over the impurity region supplying a bit line equalization voltage to the impurity region, wherein a contact connecting the metal line and the impurity region is formed lateral to the word line drive region rather than between the memory cell array region and the bit line equalization region.

Abstract: The present invention relates to a ball array capacitance minimizing layout that includes a ball array disposed upon a substrate with trace routing laid out between each ball pad and a respective bond wire pad. After routing of both signal and ground traces between the ball pads and their respective bond wire pads, at least one buffer trace is also disposed upon the substrate as a closed loop. The buffer trace may or may not be connected to ground. Preferably, buffer traces are configured to reduce the capacitance of the highest capacitance ball pads. This is accomplished by placing more of a give buffer trace around the perimeter of a higher capacitance ball pad, that around the perimeter of a lower capacitance ball pad. Accordingly, a capacitance difference between a higher capacitance ball pad and signal trace and a lower capacitance ball pad and signal trace can be minimized according to the present invention.

Abstract: A semiconductor device of a BGA (Ball-Grid-Array) package comprises a lead frame, a semiconductor chip, bonding wires, a plastic, an insulation film, and solder balls. The semiconductor chip is mounted on one side of the lead frame, and is electrically connected to the lead frame by the bonding wires. The plastic encapsulates the semiconductor chip and the bonding wires. The insulation film has openings for exposing predetermined regions of the lead frame. The insulation film is affixed onto an underside surface of the lead frame. The solder balls act as connection terminals. The solder balls are formed on the regions of the lead frame exposed through the openings in the insulation film.

Abstract: Semiconductor die pad design consisting of an I/O cell where the outside bond site is connected to the cell's active signal, the second inside bond site is discrete and connected to one of the I/O power supplies Vdd or Vss, and the third inside bond site is discrete and connected to the compliment of the second pad site. The I/O cell design is universal to traditional wire-bonding assemblies and flip-chip assemblies.

Abstract: A semiconductor memory device provided with a plurality of memory cells each including first transistors having first conductivity type and second transistors having a second conductivity type, each memory cell comprising a first active region where channels of the first transistors are formed and a second active region where channels of the second transistors are formed, the first and second active regions being arranged so that the directions of channel currents of the transistors become parallel to each other in each cell and being separated between adjoining memory cells in a direction perpendicular to the directions of channel current.

Abstract: A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6F2 or smaller memory cells in a type of cross point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.

Abstract: In order that an internal logic circuit area and an outside input/output cell group are easily connected, a plurality of input/output cell groups for performing signal transfer with an external device are each arranged in a square loop so that the internal logic circuit area is surrounded by a plurality of loops. In each of the inside and the outside input/output cell groups, bonding pads are provided, and square-loop-shaped power supply wiring having an input/output element and protecting element formed area formed therein and functioning as a guard band is disposed on the internal logic circuit area side of the bonding pad. The input/output cells of the inside input/output cell group are arranged in a condition where a first space for providing wiring between the internal logic circuit area and the outside input/output cell group is provided.

Abstract: A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.

Abstract: A method for avoiding micro-loading effect during etching is disclosed. The method comprises the steps of: providing a semiconductor substrate with a layer to be patterned and etched formed thereover; forming a masking layer over the layer to be patterned; defining a row pattern in the masking layer, the row pattern comprising a plurality of rectangles and a plurality of connecting bars, each of the connecting bars connecting two of the rectangles; and removing a portion of the layer to be patterned, to form a patterned layer with a recessed channel, by using the masking layer as a mask with the row pattern.

Abstract: A semiconductor integrated circuit device comprising a logical circuit including a MIS transistor formed on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor forming the logical circuit, an oscillation circuit including a MIS transistor formed on the semiconductor substrate, the oscillation circuit being constructed so that the frequency of an oscillation output thereof can be made variable, and a buffer circuit, in which the control circuit is supplied with a clock signal having a predetermined frequency and the oscillation output of the oscillation circuit so that the control circuit compares the frequency of the oscillation output and the frequency of the clock signal to output a first control signal, the oscillation circuit is controlled by the first control signal so that the frequency of the oscillation output corresponds to the frequency of the clock signal, the control of the frequency of the oscillation output being performed in such a manner that

Abstract: A gate array integrated circuit wafer is formed having M-N generic metal interconnection layers and having performance and/or electrical testing circuits which are operative using only the M-N generic metal interconnection layers. The performance and electrical testing circuits are located in the active chip area and/or in the scribe line area between dies on the wafer. Performance and/or electrical tests are performed after generic fabrication is completed, but before the final customization of the wafers. Wafers are sorted and assigned to performance and/or yield bins based upon the results of the performance and/or electrical tests. The contents of different bins are provided to different customers for addition of the final N application specific metal interconnection layers based upon the customer's performance and/or yield requirements.

Abstract: At least two spaced apart control lines are located between adjacent spaced apart power lines on a memory cell array of an integrated circuit memory device. The spaced apart power lines preferably are wider than the spaced apart control lines, and the space between adjacent control lines preferably is equal to the space between a power line and an adjacent control line. Accordingly, the width of the power lines can be increased without requiring an increase in the size of the integrated circuit memory.

Abstract: A method of inspecting a chip with projecting electrodes or bumps, part of which are lacking, includes arranging electrode terminals for detecting projecting electrodes along four corners of a peripheral edge of a rectangular semiconductor chip, measuring an electrical characteristic of each of the electrode terminals, and determining the semiconductor chip as a defective one in terms of projecting electrodes if the measured result does not conform to a desired characteristic. As another feature, the surface of the projecting electrode of the electrode terminal is flattened.

Abstract: Input/output terminals 10 made of a first aluminium wiring layer are provided within cells 3a to 3c in the same cell row 30. A plurality of mains 7a to 7c made of a second aluminium wiring layer, which are electrically independent of the input/output terminals 10 of the standard cells 3a to 3c, a power source wire 1 and a grounding wire 2, are arranged between the input/output terminals 10 of the standard cells 3 to be connected so that they extend in parallel with a cell row extending direction. Via holes 8 are provided in regions in which the input/output terminals 10 overlap the mains 7 two-dimensionally to make electrical connection between the input/output terminals 10 and the mains 7. Since the wirings in the same cell row are executed within the cells in the cell row, an integration degree can be improved.

Abstract: In a circuit cell band having circuit cells arranged aligned along a linear array, an on-a-cell line is arranged over a prescribed number of circuit cells, in a region different from a line region in which line band is formed on both sides of the circuit cells, for example, and the on-the-cell line is connected to a feed through in a feed through region provided between adjacent circuit cells. Restrictions on the feed through, size of the circuit cell and the lines are removed as much as possible. The circuit cell has also island-shaped impurity regions for fixing a substrate potential, so that latch up immunity is improved. Transistor forming regions having different conductivity types in a circuit cell are arranged in a sandwiched structure, and the circuit cell can be inverted horizontally and/or vertically while maintaining the transistor arrangement in the circuit cell.

Abstract: A semiconductor integrated circuit device has a semiconductor chip, on which are formed a plurality of input/output circuits and input/output pads individually connected electrically thereto. The input/output pads are connected electrically to a plurality of inner leads formed on the frame on which the semiconductor chip is mounted. The input/output circuits are arranged in two rows along each edge of the semiconductor chip, with the first row of input/output circuits arranged closer to the edge than the second row of input/output circuits. The input/output pads connected to the first-row input/output circuits are arranged in two rows in such a way that the first and second rows of input/output pads sandwich the first row of input/output circuits. The input/output pads connected to the second-row input/output circuits are arranged to form a third row of input/output pads along the second row of input/output circuits.

Abstract: Disclosed is an integrated circuit chip having an improved ESD protection structure. The integrated circuit chip includes a core logic region having a plurality of transistor devices that are interconnected to form a specific integrated circuit device. A plurality of input/output cells are defined along a periphery of the integrated circuit chip. An ESD bus die edge seal that defines a single ring around the periphery of the integrated circuit chip is provided. The ESD bus die edge seal is positioned outside of the plurality of input/output cells closest to a physical outer edge of the integrated circuit chip. Further, a plurality of (Vss) supply cells are contained in selected ones of the plurality of input/output cells. And, a plurality of ESD cross-coupled diodes are connected between the plurality of (Vss) supply cells and the ESD bus die edge seal.

Abstract: A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6 F.sup.2 or smaller memory cells in a type of cross point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.

Abstract: A semiconductor integrated circuit device capable of reducing delay of wiring as far as possible is provided. The semiconductor integrated circuit device comprises at least two sets of pairs of signal lines having first polarity and second polarity opposite thereto, wherein the signal line of the first polarity of the signal lines of the second set is disposed at the portion adjacent to the signal line of the first polarity of the signal lines of the first set, the signal line of the second polarity of the first set is disposed at the portion adjacent to the signal line of the first polarity of the second set, and the signal line of the second polarity of the second set is disposed at the portion adjacent to the signal line of the second polarity of the first set.

Abstract: A connection component for a microelectronic element includes a sheet-like support structure having top and bottom surfaces which extend in horizontal directions. The support structure includes a central region and a periphery surrounding the central region with terminals mounted on the central region of the support structure and exposed at the top surface thereof. A plurality of leads extend on the support structure with each lead having a terminal section connected to one of the terminals and attached to the bottom surface, a bond region and a horizontally curved section between the bond region and the terminal region. The bond regions of the leads are disposed side-by-side in one or more rows adjacent the periphery of the support structure. After the bond regions of the leads have been bonded to contacts of a microelectronic element, the support structure of the connection component is moveable upwardly so as to bend the curved sections of the leads.

Abstract: A semiconductor test chip including a plurality test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.

Abstract: An gate array system characterized in including, on a semiconductor chip, an internal cell region where internal cells are arranged in lattice and a cell region for input/output circuit including an array of input/output circuit cells disposed on the circumference of the internal cell region, and characterized in that a positional relationship between an internal cell at a specific position of the internal cell region and a specific input/output cell constituting the cell region for input/output circuit or a functional block formed at a specific position of the cell region for input/output circuit is constant irrespective of the size of a semiconductor chip.

Abstract: A two-terminal fuse-antifuse structure comprises a horizontal B-fuse portion and a vertical A-fuse portion disposed between two metallization layers of an integrated circuit device. The two-terminal fuse-antifuse can be programmed with a relatively high current applied across the two terminals to blow the B-fuse, or with a high voltage applied across the two terminals to program the A-fuse. Such a device, connected between two circuit nodes, initially does not provide an electrical connection between the two circuit nodes. It may then be programmed with a relatively high voltage to blow the A-fuse, causing it to conduct between the two circuit nodes. Then, upon application of a relatively high current between the two circuit nodes, the B-fuse will blow, making the device permanently non-conductive.

Abstract: Signal area efficiency in integrated circuit designs is improved by increasing the information efficiency of signal wiring on an integrated circuit. Candidate signals are selected for combination by prioritizing signals according to length of travel, travel path, and information content. Signals with low information content and with greater distance between endpoints make poor utilization of fixed wiring and provide the best candidates for improvement. Candidate signals which travel similar (substantially parallel) paths from point to point across the integrated circuit are combined to improve chip area utilization efficiency. A variety of techniques are described for combining low-information-content signals onto a small number of wires, transmitting them over the small number of wires, and re-expanding them at their destination. Assuming that the combining/expanding circuitry occupies less space than the point-to-point wiring which would otherwise be required, there is a net reduction in chip area.

Abstract: A semiconductor integrated circuit device having a memory portion and a logic circuit portion formed with a same semiconductor substrate comprising a first logic circuit block, a second logic circuit block disposed in an area different from an area in which the first logic circuit block is disposed, and a pair of memory blocks oppositely disposed so that the second logic circuit block comes in between. Data stored in the pair of memory blocks are transmitted to the second logic circuit block for processing via a memory peripheral circuit provided on the second logic circuit block. A result of the data processing is transmitted to the first logic circuit block or an external device via an input/output circuit provided in the second logic circuit block.

Abstract: Signals are routed within a routing channel between a first logic block and a second logic block. A power signal within a power conductor is routed as part of a bottom layer of the routing channel. The bottom layer is located above a substrate for the integrated circuit. A ground signal is also routed within a ground conductor as part of the bottom layer of the routing channel. Data lines are routed in a top layer of the routing channel. The data lines carry data signals within the routing channel. Connection lines are routed within a middle layer of the routing channel. The middle layer is between the bottom layer of the routing channel and the top layer of the routing channel. The connecting lines connect a subset of the data lines in the top layer, the ground conductor in the bottom layer and the power conductor in the bottom layer to the first logic block and to the second logic block.