With Specified Semiconductor Materials Patents (Class 257/22)
  • Patent number: 10297978
    Abstract: A semiconductor optical device 1 includes an active layer 4 provided on a substrate 2, a clad layer 5 provided on the active layer 4, and a contact layer 7 provided on the clad layer 5. The contact layer 7 contains a first impurity and a second impurity different from the first impurity. A semiconductor light source includes the active layer 4 provided on the substrate 2, the clad layer 5 provided on the active layer 4, and the contact layer 7 provided on the clad layer 5. The contact layer 7 contains the first impurity and the second impurity different from the first impurity.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: May 21, 2019
    Assignee: NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY
    Inventors: Atsushi Matsumoto, Kouichi Akahane, Naokatsu Yamamoto
  • Patent number: 10177267
    Abstract: An UV photodetector includes: a substrate, a template layer formed on the substrate, an intrinsic AlGaN layer formed on the template layer, a first n-type AlGaN layer and a second n-type AlGaN layer formed on the intrinsic AlGaN layer side-by-side and separated by a gap, wherein the gap exposes the intrinsic AlGaN layer. Another UV photodetector includes: an UV transparent substrate, an UV transparent template layer formed on the substrate, a first UV transparent n-type AlGaN layer formed on the UV transparent template layer, an intrinsic AlGaN layer formed on the first UV transparent n-type AlGaN layer, a second n-type AlGaN layer formed on the intrinsic AlGaN layer, and a p-type layer formed on the second n-type AlGaN layer.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: January 8, 2019
    Assignee: BOLB INC.
    Inventors: Jianping Zhang, Ling Zhou, Ying Gao
  • Patent number: 9964702
    Abstract: The disclosed embodiments provide a system that implements an optical interface. The system includes a semiconductor chip with a silicon layer, which includes a silicon waveguide, and an interface layer (which can be comprised of SiON) disposed over the silicon layer, wherein the interface layer includes an interface waveguide. The system also includes an optical coupler that couples an optical signal from the silicon waveguide in the silicon layer to the interface waveguide in the interface layer, wherein the interface waveguide channels the optical signal in a direction parallel to a top surface of the semiconductor chip. The system additionally includes a mirror, which is oriented to reflect the optical signal from the interface waveguide in a surface-normal direction so that the optical signal exits the top surface of the semiconductor chip.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: May 8, 2018
    Assignee: Oracle International Corporation
    Inventors: Ying Luo, Xuezhe Zheng, Ashok V. Krishnamoorthy
  • Patent number: 9853185
    Abstract: There is provided a method for manufacturing a nanostructure semiconductor light emitting device, including: forming a mask having a plurality of openings on a base layer; growing a first conductivity-type semiconductor layer on exposed regions of the base layer such that the plurality of openings are filled, to form a plurality of nanocores; partially removing the mask such that side surfaces of the plurality of nanocores are exposed; heat-treating the plurality of nanocores after partially removing the mask; sequentially growing an active layer and a second conductivity-type semiconductor layer on surfaces of the plurality of nanocores to form a plurality of light emitting nanostructures, after the heat treatment; and planarizing upper parts of the plurality of light emitting nanostructures such that upper surfaces of the nanocores are exposed.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: December 26, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nam-Goo Cha, Dong-Ho Kim, Geon-Wook Yoo
  • Patent number: 9837495
    Abstract: There are disclosed herein various implementations of semiconductor structures including III-Nitride interlayer modules. One exemplary implementation comprises a substrate and a first transition body over the substrate. The first transition body has a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface. The exemplary implementation further comprises a second transition body, such as a transition module, having a smaller lattice parameter at a lower surface overlying the second surface of the first transition body and a larger lattice parameter at an upper surface of the second transition body, as well as a III-Nitride semiconductor layer over the second transition body. The second transition body may consist of two or more transition modules, and each transition module may include two or more interlayers. The first and second transition bodies reduce strain for the semiconductor structure.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: December 5, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Michael A. Briere
  • Patent number: 9800020
    Abstract: A broad area laser diode is configured to include an anti-guiding layer located outside of the active region of the device. The anti-guiding layer is formed of a high refractive index material that serves to de-couple unwanted, higher-order lateral modes (attributed to thermal lensing problems) from the lower-order mode output beam of output signal from the laser diode. The anti-guiding layer is formed using a single epitaxial growth step either prior to or subsequent to the steps used to grow the epitaxial layers forming the laser diode itself, thus creating a structure that provides suppression of unwanted higher-order modes without requiring a modification of specific process steps used to fabricate the laser diode itself.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: October 24, 2017
    Assignee: II-VI Laser Enterprise GmbH
    Inventors: Jarkko Telkkälä, Jürgen Müller, Norbert Lichtenstein
  • Patent number: 9711948
    Abstract: A terahertz source implementing a {hacek over (C)}erenkov difference-frequency generation scheme in a quantum cascade laser. The laser includes an undoped or semi-insulating InP substrate with an exit facet that is polished at an angle between 10° to 40°. The laser further includes a first waveguide cladding layer(s) in contact with an active layer (arranged as a multiple quantum well structure) and a current extraction layer on top of the substrate. Furthermore, the laser includes a second waveguide cladding layer(s) on top of the active layer, where the first and second waveguide cladding layers are disposed to form a waveguide structure by which terahertz radiation generated in the active layer is guided inside the laser. The terahertz radiation is emitted into the substrate at a {hacek over (C)}erenkov angle relative to a direction of the nonlinear polarization wave in the active layer, and once in the substrate, propagates towards the exit facet.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: July 18, 2017
    Assignee: Board of Regents, The University of Texas System
    Inventors: Mikhail Belkin, Robert Adams, Markus Christian Amann, Augustinas Vizbaras
  • Patent number: 9496197
    Abstract: Apparatus and methods are provided for heat removal and spreading from a field effect transistor (FET) including a substrate, a first source, a first gate, and a drain on the substrate, and a poly-diamond dielectric thermally coupled to the first gate wherein the poly-diamond dielectric facilitates heat removal from a top of the FET.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: November 15, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Miroslav Micovic, Alexandros D. Margomenos, Keisuke Shinohara, Andrea Corrion
  • Patent number: 9472720
    Abstract: A nitride semiconductor wafer includes a silicon substrate, a first layer, a second layer, a third layer, a fourth layer, a fifth layer, and a sixth layer. The first layer is provided on the silicon substrate. The second layer is provided on the first layer. The third layer is provided on the second layer. The fourth layer is provided on the third layer. The fifth layer is provided on the fourth layer. The sixth layer is provided on the fifth layer. A composition ratio x4 of the fourth layer decreases in a first direction from the third layer toward the fifth layer. A maximum value of the composition ratio x4 is not more than a composition ratio of the third layer. A minimum value of the composition ratio x4 is not less than a composition ratio of the fifth layer.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: October 18, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kei Kaneko, Mitsuhiro Kushibe, Hiroshi Katsuno, Shinji Yamada, Jumpei Tajima, Yasuo Ohba
  • Patent number: 9450548
    Abstract: An apparatus for outputting audio signals. The apparatus for outputting audio signals includes a pulse density modulation (PDM) unit for PDM modulating an input audio signal to output a modulated audio signal, a driving signal generator for generating at least one driving signal to control switching amplification operations based on the modulated audio signal, and a power switching amplifier having at least one switch that is turned on or turned off in response to the driving signal and performs the switching amplification operations for using the at least one switch to output an amplified audio signal that corresponds to the modulated audio signal, wherein the at least one switch includes at least one from among a gallium nitride (GaN) transistor, gallium arsenide (GaAs) transistor, and a silicon carbide (SiC) transistor.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: September 20, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-yong Cho, Hae-kwang Park
  • Patent number: 9397293
    Abstract: An artificial composite object combines a quantum of sound with a matter excitation. A phonon in a confinement structure containing the matter excites it from an initial state to an excited state corresponding to a frequency of the phonon. Relaxation of the matter back to the initial state emits a phonon of the same frequency into the confinement structure. The phonon confinement structure, for example, a cavity, traps the emitted phonon thereby allowing further excitation of the matter. The coupling between the phonon and the matter results in a quantum quasi-particle referred to as a phoniton. The phoniton can find application in a wide variety of quantum systems such as signal processing and communications devices, imaging and sensing, and information processing.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: July 19, 2016
    Assignees: University of Maryland, College Park, The United States of America, as represented by the Director, National Security Agency
    Inventors: Charles George Tahan, Rousko Todorov Hristov, Oney O. Soykal
  • Patent number: 9362115
    Abstract: A nitride semiconductor wafer includes a silicon substrate, a first layer, a second layer, a third layer, a fourth layer, a fifth layer, and a sixth layer. The first layer is provided on the silicon substrate. The second layer is provided on the first layer. The third layer is provided on the second layer. The fourth layer is provided on the third layer. The fifth layer is provided on the fourth layer. The sixth layer is provided on the fifth layer. A composition ratio x4 of the fourth layer decreases in a first direction from the third layer toward the fifth layer. A maximum value of the composition ratio x4 is not more than a composition ratio of the third layer. A minimum value of the composition ratio x4 is not less than a composition ratio of the fifth layer.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: June 7, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kei Kaneko, Mitsuhiro Kushibe, Hiroshi Katsuno, Shinji Yamada, Jumpei Tajima, Yasuo Ohba
  • Patent number: 9245750
    Abstract: A method of forming nanowire devices. The method includes forming a stressor layer circumferentially surrounding a semiconductor nanowire. The method is performed such that, due to the stressor layer, the nanowire is subjected to at least one of radial and longitudinal strain to enhance carrier mobility in the nanowire. Radial and longitudinal strain components can be used separately or together and can each be made tensile or compressive, allowing formulation of desired strain characteristics for enhanced conductivity in the nanowire of a given device.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: January 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Bernd W. Gotsmann, Siegfried F. Karg, Heike E. Riel
  • Patent number: 9246308
    Abstract: A quantum cascade laser includes a semiconductor substrate including a principal surface; a mesa waveguide disposed on the principal surface of the semiconductor substrate, the mesa waveguide including a light emitting region and an upper cladding layer disposed on the light emitting region, the mesa waveguide extending in a direction orthogonal to a reference direction; and a current blocking layer formed on a side surface of the mesa waveguide. The light emitting region includes a plurality of core regions and a plurality of buried regions. The core regions and the buried regions are alternately arranged in the reference direction. The core region at a central portion of the mesa waveguide has a width smaller than a width of the core region at a peripheral portion of the mesa waveguide in the reference direction.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: January 26, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Jun-ichi Hashimoto, Michio Murata
  • Patent number: 9240675
    Abstract: A quantum cascade laser includes a semiconductor substrate including a principal surface; a mesa waveguide disposed on the principal surface of the semiconductor substrate, the mesa waveguide including a light emitting region and an upper cladding layer disposed on the light emitting region, the mesa waveguide extending in a direction orthogonal to a reference direction; and a current blocking layer formed on a side surface of the mesa waveguide. The light emitting region includes a plurality of core regions and a plurality of buried regions. The core regions and the buried regions are alternately arranged in the reference direction. The core region at a central portion of the mesa waveguide has a width larger than a width of the core region at a peripheral portion of the mesa waveguide in the reference direction.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: January 19, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Jun-ichi Hashimoto, Michio Murata
  • Patent number: 9236249
    Abstract: A method of growing III-N material on a silicon substrate includes the steps of epitaxially growing a single crystal rare earth oxide on a silicon substrate, epitaxially growing a single crystal rare earth nitride on the single crystal rare earth oxide, and epitaxially growing a layer of single crystal III-N material on the single crystal rare earth nitride.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: January 12, 2016
    Assignee: TRANSLUCENT, INC.
    Inventors: Rytis Dargis, Robin Smith, Andrew Clark, Erdem Arkun, Michael Lebby
  • Patent number: 9214518
    Abstract: Disclosed is a wafer comprising a first layer of GaSb grown on a GaSb substrate by molecular beam epitaxy (MBE), an oxide layer deposited on the surface of the first layer, and a cap layer deposited on the surface of the oxide layer. The wafer was capped with an arsenic (As) layer after the growth of the first layer. The As layer was removed from the wafer before the oxide layer was deposited on the surface of the first layer. Also disclosed is a method of forming a wafer. The method comprises growing a first layer of GaSb on a GaSb substrate by MBE, capping the wafer with an As layer after the growth of the first layer, removing the As layer from the wafer, depositing an oxide layer on the surface of the first layer, and depositing a cap layer on the surface of the oxide layer.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: December 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited and National Taiwan University
    Inventors: Jui-Lin Chu, Ming-Hwei Hong, Juei-Nai Kwo, Tun-Wen Pi, Jen-Inn Chyi
  • Patent number: 9209180
    Abstract: A uni-terminal transistor device is described. In one embodiment, an n-channel transistor comprises a first semiconductor layer having a discrete hole level H0; a second semiconductor layer having a conduction band minimum EC2; a wide bandgap semiconductor barrier layer disposed between the first and the second semiconductor layers; a gate dielectric layer disposed above the first semiconductor layer; and a gate metal layer disposed above the gate dielectric layer and having an effective workfunction selected to position the discrete hole level H0 below the conduction band minimum Ec2 for zero bias applied to the gate metal layer and to obtain n-terminal characteristics.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Matthias Passlack
  • Patent number: 9086321
    Abstract: A method of analyzing a nitride semiconductor layer in which a mixing ratio at a ternary mixed-crystal nitride semiconductor layer can be analyzed non-destructively, simply, and precisely, even its surface is covered with a cap layer is provided. The nitride semiconductor layer having an AN layer or a BN layer with a thickness of 0.5 to 10 nm that is stacked on an AxB1-xN layer (A and B: 13 group elements, 0?x?1) is subjected to reflection spectroscopy to obtain a reflection spectrum of the AxB1-xN layer. Let an energy value in a peak position of the reflection spectrum be a band gap energy Egap, and let a band gap energy value of AxB1-xN (x=1) be EA and a band gap energy value of AxB1-xN (x=0) be EB, x is calculated from Equation Egap=(1?x)EB+xEA?bx(1?x) (where b is bowing parameter corresponding to A and B).
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: July 21, 2015
    Assignee: COVALENT MATERIALS CORPORATION
    Inventors: Yoshihata Yanase, Hiroshi Shirai, Jun Komiyama, Hiroshi Oishi
  • Publication number: 20150115223
    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device includes: a first conductive type semiconductor layer including a first lower conductive type semiconductor layer and a first upper conductive type semiconductor layer; a V-pit passing through at least one portion of the first upper conductive type semiconductor layer; a second conductive type semiconductor layer placed over the first conductive type semiconductor and filling the V-pit; and an active layer interposed between the first and second conductive type semiconductor layers with the V-pit passing through the active layer. The first upper conductive type semiconductor layer has a higher defect density than the first lower conductive type semiconductor layer and includes a V-pit generation layer comprising a starting point of the V-pit.
    Type: Application
    Filed: October 28, 2014
    Publication date: April 30, 2015
    Inventors: Woo Chul Kwak, Seung Kyu Choi, Chae Hon Kim, Jung Whan Jung, Yong Hyun Baek, Sam Seok Jang, Su Youn Hong, Mi Gyeong Jeong
  • Patent number: 8993992
    Abstract: A GaN based semiconductor light-emitting device is provided. The light-emitting device includes a first GaN based compound semiconductor layer of an n-conductivity type; an active layer; a second GaN based compound semiconductor layer; an underlying layer composed of a GaN based compound semiconductor, the underlying layer being disposed between the first GaN based compound semiconductor layer and the active layer; and a superlattice layer composed of a GaN based compound semiconductor doped with a p-type dopant, the superlattice layer being disposed between the active layer and the second GaN based compound semiconductor layer.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: March 31, 2015
    Assignee: Sony Corporation
    Inventors: Goshi Biwa, Hiroyuki Okuyama
  • Publication number: 20150060765
    Abstract: A semiconductor device includes a superlattice buffer layer formed on a substrate. A first semiconductor layer is formed by a nitride semiconductor on the superlattice buffer layer. A second semiconductor layer is formed by a nitride semiconductor on the first semiconductor layer. A gate electrode, a source electrode and a drain electrode are formed on the second semiconductor layer. The superlattice buffer layer is forced by alternately and periodically laminating a first superlattice formation layer, and a second superlattice formation layer. The first super lattice formation layer is formed by AlxGa1-xN and the second superlattice formation layer is formed by AlyGa1-yN, where a relationship x>y is satisfied. A concentration of an impurity element serving as an acceptor doped into a portion or a whole of the second super lattice formation layer is higher than a concentration of the impurity element serving as an acceptor, doped into the first superlattice formation layer.
    Type: Application
    Filed: July 3, 2014
    Publication date: March 5, 2015
    Inventors: JUNJI KOTANI, NORIKAZU NAKAMURA
  • Publication number: 20150060039
    Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: HUI-YU LEE, CHI-WEN CHANG, JUI-FENG KUAN, YI-KAN CHENG
  • Patent number: 8969850
    Abstract: An electro-magnetic radiation detector is described. The electro-magnetic radiation detector includes a detector material and a voltage biasing element. The detector material includes a substantially regular array of nano-particles embedded in a matrix material. The voltage biasing element is configured to apply a bias voltage to the matrix material such that electrical current is directly generated based on a cooperative plasmon effect in the detector material when electro-magnetic radiation in a predetermined wavelength range is incident upon the detector material, where the dominant mechanism for decay in the cooperative plasmon effect is non-radiative.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: March 3, 2015
    Assignee: Rockwell Collins, Inc.
    Inventors: Robert G. Brown, James H. Stanley
  • Patent number: 8957432
    Abstract: A semiconductor device may reduce a dislocation density and tensile stress by forming a plurality of interlayers between neighboring clad layers. The semiconductor device may include a plurality of clad layers on a substrate and a plurality of interlayers between neighboring clad layers.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: February 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Young-jo Tak, Jae-won Lee
  • Publication number: 20150041762
    Abstract: A transistor device having a graphene base for the transport of electrons into a collector is provided. The transistor consists of a heterostructure comprising an electron emitter, an electron collector, and a graphene material base layer consisting of one or more sheets of graphene situated between the emitter and the collector. The transistor also can further include an emitter transition layer at the emitter interface with the base and/or a collector transition layer at the base interface with the collector. The electrons injected into the graphene material base layer can be “hot electrons” having an energy E substantially greater than EF, the Fermi energy in the graphene material base layer or can be “non-hot electrons” having an energy E approximately equal to than EF. The electrons can have the properties of ballistic transit through the base layer.
    Type: Application
    Filed: September 19, 2014
    Publication date: February 12, 2015
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventor: Francis J. Kub
  • Publication number: 20150001467
    Abstract: Disclosed herein is a semiconductor device, including: a substrate; and a superlattice thin film formed on the substrate, wherein the superlattice thin film is configured such that insulator layers and semiconductor layers are alternately laminated on the substrate. The superlattice thin film is characterized in that, since it is formed by the lamination of a semiconductor layer and an insulator layer, the semiconductor layer and insulator layer constituting the superlattice thin film may be composed of a crystalline material, an amorphous material or a mixture thereof, and thus various kinds of materials for solving the mismatch in lattice constant between conventional superlattices made of different kinds of semiconductor materials can be used without limitations.
    Type: Application
    Filed: June 17, 2014
    Publication date: January 1, 2015
    Inventors: Hyung Koun CHO, Cheol Hyoun AHN
  • Patent number: 8907320
    Abstract: An ultraviolet (UV) light-emitting diode including an n-type semiconductor layer, an active layer disposed on the n-type semiconductor layer, a p-type semiconductor layer disposed on the active layer and formed of p-type AlGaN, and a p-type graphene layer disposed on the p-type semiconductor layer and formed of graphene doped with a p-type dopant. The UV light-emitting diode has improved light emission efficiency by lowering contact resistance with the p-type semiconductor layer and maximizing UV transmittance.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: December 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Won Hwang, Geun-Woo Ko, Sung-Hyun Sim, Jung-Sub Kim, Hun-Jae Chung, Cheol-Soo Sone
  • Patent number: 8908733
    Abstract: In at least one embodiment of the optoelectronic semiconductor chip (1), the latter is based on a nitride material system and comprises at least one active quantum well (2). The at least one active quantum well (2) is designed to generate electromagnetic radiation when in operation. Furthermore, the at least one active quantum well (2) comprises N successive zones (A) in a direction parallel to a growth direction z of the semiconductor chip (1), N being a natural number greater than or equal to 2. At least two of the zones (A) of the active quantum well (2) have mutually different average indium contents c. Furthermore the at least one active quantum well (2) fulfills the condition: 40??c(z)dz?2.5N?1.5?dz?80.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: December 9, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Adrian Avramescu, Désirée Queren, Christoph Eichler, Matthias Sabathil, Stephan Lutgen, Uwe Strauss
  • Publication number: 20140353587
    Abstract: An epitaxial wafer for a heterojunction type FET includes an AlN primary layer, a stepwisely composition-graded buffer layer structure, a superlattice buffer layer structure, a GaN channel layer, and a nitride semiconductor electron supply layer, which are sequentially provided on a Si substrate, the stepwisely composition-graded buffer layer structure including a plurality of AlGaN buffer layers provided on each other such that an Al composition ratio is sequentially reduced, an uppermost layer thereof having a composition of AlxGa1—xN (0<x), a plurality of sets of an AlyGa1?yN (y?1) superlattice constituting layer and an AlzGa1?zN (0<z<y) superlattice constituting layer being provided on each other alternately starting from one of the AlyGa1?yN superlattice constituting layer and the AlzGa1?zN superlattice constituting layer in the superlattice buffer layer structure, the AlxGa1?xN buffer layer and the AlzGa1?zN superlattice constituting layer satisfying x?0.05?z?x+0.05.
    Type: Application
    Filed: January 15, 2013
    Publication date: December 4, 2014
    Inventors: Masayuki Hoteida, Nobuaki Teraguchi, Daisuke Honda, Nobuyuki Ito, Masakazu Matsubayashi, Haruhiko Matsukasa
  • Publication number: 20140353586
    Abstract: A method for producing a semiconductor element includes a step of forming a multiple quantum well in which a GaSb layer and an InAs layer are alternately stacked on a GaSb substrate by MOVPE, wherein, in the step of forming a multiple quantum well, an InSb film is formed on at least one of a lower-surface side and an upper-surface side of the InAs layer so as to be in contact with the InAs layer.
    Type: Application
    Filed: May 22, 2014
    Publication date: December 4, 2014
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Takashi KYONO, Kei FUJII, Katsushi AKITA
  • Patent number: 8900489
    Abstract: The present application provides nitride semiconductor nanoparticles, for example nanocrystals, made from a new composition of matter in the form of a novel compound semiconductor family of the type group II-III-N, for example ZnGaN, ZnInN, ZnInGaN, ZnAlN, ZnAlGaN, ZnAlInN and ZnAlGaInN. This type of compound semiconductor nanocrystal is not previously known in the prior art. The invention also discloses II-N semiconductor nanocrystals, for example ZnN nanocrystals, which are a subgroup of the group II-III-N semiconductor nanocrystals. The composition and size of the new and novel II-III-N compound semiconductor nanocrystals can be controlled in order to tailor their band-gap and light emission properties. Efficient light emission in the ultraviolet-visible-infrared wavelength range is demonstrated.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: December 2, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Peter Neil Taylor, Jonathan Heffernan, Stewart Edward Hooper, Tim Michael Smeeton
  • Patent number: 8901412
    Abstract: The disclosure relates to multiple quantum well (MQW) structures for intrinsic regions of monolithic photovoltaic junctions within solar cells which are substantially lattice matched to GaAs or Ge. The disclosed MQW structures incorporate quantum wells formed of quaternary InGaAsP, between barriers of InGaP.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: December 2, 2014
    Assignee: JDS Uniphase Corporation
    Inventor: John Roberts
  • Patent number: 8896085
    Abstract: A semiconductor light-emitting element manufacturing method including: a first step in which a first n-type semiconductor layer is laminated onto a substrate in a first organometallic chemical vapor deposition apparatus; and a second step in which a regrowth layer, a second n-type semiconductor layer, an active layer, and a p-type semiconductor layer are sequentially laminated onto the aforementioned first n-type semiconductor layer in a second organometallic chemical vapor deposition apparatus.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: November 25, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Hiromitsu Sakai
  • Patent number: 8895959
    Abstract: A superlattice layer including a plurality of periods, each of which is formed from a plurality of sub-layers is provided. Each sub-layer comprises a different composition than the adjacent sub-layer(s) and comprises a polarization that is opposite a polarization of the adjacent sub-layer(s). In this manner, the polarizations of the respective adjacent sub-layers compensate for one another. Furthermore, the superlattice layer can be configured to be at least partially transparent to radiation, such as ultraviolet radiation.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: November 25, 2014
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Remigijus Gaska, Jinwei Yang
  • Patent number: 8889439
    Abstract: The present disclosure involves a method of packaging light-emitting diodes (LEDs). According to the method, a plurality of LEDs is provided over an adhesive tape. The adhesive tape is disposed on a substrate. In some embodiments, the substrate may be a glass substrate, a silicon substrate, a ceramic substrate, and a gallium nitride substrate. A phosphor layer is coated over the plurality of LEDs. The phosphor layer is then cured. The tape and the substrate are removed after the curing of the phosphor layer. A replacement tape is then attached to the plurality of LEDs. A dicing process is then performed to the plurality of LEDs after the substrate has been removed. The removed substrate may then be reused for a future LED packaging process.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: November 18, 2014
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Chi-Xiang Tseng, Hsiao-Wen Lee, Min-Sheng Wu, Tien-Min Lin
  • Publication number: 20140332756
    Abstract: A nitride semiconductor light-emitting device is formed of an n-type nitride semiconductor layer, a trigger layer, a V-pit expanding layer, a light-emitting layer, and a p-type nitride semiconductor layer provided in this order. The light-emitting layer has a V-pit formed therein. The trigger layer is made of a nitride semiconductor material having a lattice constant different from that of a material that forms an upper surface of the n-type nitride semiconductor layer. The V-pit expanding layer is made of a nitride semiconductor material having a lattice constant substantially identical to that of the material that forms the upper surface of the n-type nitride semiconductor layer, and the V-pit expanding layer has a thickness of 5 nm or more and 5000 nm or less.
    Type: Application
    Filed: December 5, 2012
    Publication date: November 13, 2014
    Inventors: Hiroyuki Kashihara, Narihito Okada, Kazuyuki Tadatomo, Haruhisa Takiguchi
  • Patent number: 8872308
    Abstract: III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer. A cap layer of AlN is grown on the final III-N layer and a III-N layer of material with one of an LED structure and an HEMT structure is grown on the AlN cap layer.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: October 28, 2014
    Assignee: Translucent, Inc.
    Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
  • Publication number: 20140306183
    Abstract: A method for manufacturing a functional material including a porous metal complex with nanoparticles included therein, the method including a configuration of adding more than one particle constituent raw material constituting the nanoparticles and a porous metal complex to a solvent, and then synthesizing nanoparticles included in the porous metal complex by heating to a desired temperature. In addition, provided is an electronic component including an electronic component element using a functional material including a porous metal complex with nanoparticles included therein.
    Type: Application
    Filed: June 27, 2014
    Publication date: October 16, 2014
    Inventors: Takuo Wakaoka, Koji Murayama, Hiroshi Takagi, Haruya Miyata, Yoshihiko Takano, Yasuaki Kainuma
  • Patent number: 8847204
    Abstract: This invention provides a germanium electroluminescence device and a fabricating method of the same for using germanium of an indirect bandgap semiconductor without modifying a bandgap as a light-emitting layer which emits a 1550 nm-wavelength light and enabling to use not only as infrared LEDs itself but also as light sources for optical communication systems.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: September 30, 2014
    Assignees: Seoul National University R&DB Foundation, The Board of Trustees of the Leland Standford Junior University
    Inventors: Byung-Gook Park, James S. Harris, Jr., Seongjae Cho
  • Patent number: 8846441
    Abstract: There is provided an anode for an organic electronic device. The anode is a conducting inorganic material having an oxidized surface layer. The surface layer is non-conductive and hole-transporting.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: September 30, 2014
    Assignee: E I du Pont de Nemours and Company
    Inventor: Shiva Prakash
  • Patent number: 8835955
    Abstract: A silicon-on-insulator (SOI) substrate structure and method of fabrication including a single crystal silicon substrate, a layer of single crystal rare earth oxide formed on the substrate, a layer of engineered single crystal silicon formed on the layer of single crystal rare earth oxide, and a single crystal insulator layer of IIIOxNy formed on the engineered single crystal silicon layer. In some embodiments the III material in the insulator layer includes more than on III material. In a preferred embodiment the single crystal rare earth oxide includes Gd2O3 and the single crystal insulator layer of IIIOxNy includes one of AlOxNy and AlGaOxNy.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: September 16, 2014
    Assignee: Translucent, Inc.
    Inventors: Erdem Arkun, Rytis Dargis, Andrew Clark, Michael Lebby
  • Patent number: 8829491
    Abstract: According to example embodiments, a semiconductor device includes a first layer and second layer. The first layer includes a nitride semiconductor doped with a first type dopant. The second layer is below the first layer and includes a high concentration layer. The high concentration layer includes the nitride semiconductor doped with the first type dopant and has a doping concentration higher than a doping concentration of the first layer.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: September 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-won Lee, Jun-youn Kim, Young-jo Tak
  • Patent number: 8829512
    Abstract: A miniaturized semiconductor device including a transistor in which a channel formation region is formed using an oxide semiconductor film and variation in electric characteristics due to a short-channel effect is suppressed is provided. In addition, a semiconductor device whose on-state current is improved is provided. A semiconductor device is provided with an oxide semiconductor film including a pair of second oxide semiconductor regions which are amorphous regions and a first oxide semiconductor region located between the pair of second oxide semiconductor regions, a gate insulating film, and a gate electrode provided over the first oxide semiconductor region with the gate insulating film interposed therebetween. Hydrogen or a rare gas is added to the second oxide semiconductor regions.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8800130
    Abstract: A charge-coupled device (CCD) image sensor includes multiple vertical charge-coupled device (VCCD) shift registers and independently-controllable gate electrodes disposed over the VCCD shift registers and arranged into physically separate and distinct sections that are non-continuous across the plurality of VCCD shift registers. The CCD image sensor can be configured to operate in two or more operating modes, including a full resolution charge multiplication mode.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: August 12, 2014
    Assignee: Truesense Imaging, Inc.
    Inventors: Antonio S. Ciccarelli, Eric J. Meisenzahl
  • Publication number: 20140209861
    Abstract: A semiconductor device includes a drift layer having a structure wherein a plurality of quantum dot layers each including a quantum dot containing InxGa1-xN (0?x?1) and a burying layer burying the quantum dot and containing n-type Inx(GayAl1-y)1-xN (0?x?1, 0?y?1) are stacked.
    Type: Application
    Filed: April 1, 2014
    Publication date: July 31, 2014
    Applicant: FUJITSU LIMITED
    Inventor: NAOYA OKAMOTO
  • Publication number: 20140209862
    Abstract: Provided is a Group III nitride epitaxial substrate that can suppress the occurrence of breakage during a device formation process and a method for manufacturing the same. A Group III nitride epitaxial substrate according to the present invention includes a Si substrate, an initial layer in contact with the Si substrate, and a superlattice laminate, formed on the initial layer, including a plurality of sets of laminates, each of the laminates including, in order, a first layer made of AlGaN with an Al composition ratio greater than 0.5 and 1 or less and a second layer made of AlGaN with an Al composition ratio greater than 0 and 0.5 or less. The Al composition ratio of the second layer progressively decreases with distance from the substrate.
    Type: Application
    Filed: July 11, 2012
    Publication date: July 31, 2014
    Applicant: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Tetsuya Ikuta, Tomohiko Shibata
  • Patent number: 8784703
    Abstract: A method of making a colloidal solution of high confinement semiconductor nanocrystals includes: forming a first solution by combining a solvent, growth ligands, and at most one semiconductor precursor; heating the first solution to the nucleation temperature; and adding to the first solution, a second solution having a solvent, growth ligands, and at least one additional and different precursor than that in the first solution to form a crude solution of nanocrystals having a compact homogenous semiconductor region. The method further includes: waiting 0.5 to 20 seconds and adding to the crude solution a third solution having a solvent, growth ligands, and at least one additional and different precursor than those in the first and second solutions; and lowering the growth temperature to enable the formation of a gradient alloy region around the compact homogenous semiconductor region, resulting in the formation of a colloidal solution of high confinement semiconductor nanocrystals.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: July 22, 2014
    Assignee: Eastman Kodak Company
    Inventors: Keith Brian Kahen, Matthew Holland, Sudeep Pallikkara Kuttiatoor
  • Patent number: 8779437
    Abstract: According to one embodiment, a wafer includes a substrate, a base layer, a foundation layer, an intermediate layer and a functional unit. The substrate has a major surface. The base layer is provided on the major surface and includes a silicon compound. The foundation layer is provided on the base layer and includes GaN. The intermediate layer is provided on the foundation layer and includes a layer including AlN. The functional unit is provided on the intermediate layer and includes a nitride semiconductor. The foundation layer has a first region on a side of the base layer, and a second region on a side of the intermediate layer. A concentration of silicon atoms in the first region is higher than a concentration of silicon atoms in the second region. The foundation layer has a plurality of voids provided in the first region.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonari Shioda, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: RE45517
    Abstract: A vertical geometry light emitting diode is disclosed that is capable of emitting light in the red, green, blue, violet and ultraviolet portions of the electromagnetic spectrum. The light emitting diode includes a conductive silicon carbide substrate, an InGaN quantum well, a conductive buffer layer between the substrate and the quantum well, a respective undoped gallium nitride layer on each surface of the quantum well, and ohmic contacts in a vertical geometry orientation.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: May 19, 2015
    Assignee: Cree, Inc.
    Inventors: Kathleen Marie Doverspike, John Adam Edmond, Hua-shuang Kong, Heidi Marie Dieringer, David B. Slater, Jr.