With Specified Semiconductor Materials Patents (Class 257/22)
  • Patent number: 7646009
    Abstract: In the nitride semiconductor device of the present invention, an active layer 12 is sandwiched between a p-type nitride semiconductor layer 11 and an n-type nitride semiconductor layer 13. The active layer 12 has, at least, a barrier layer 2a having an n-type impurity; a well layer 1a made of a nitride semiconductor that includes In; and a barrier layer 2c that has a p-type impurity, or that has been grown without being doped. An appropriate injection of carriers into the active layer 12 becomes possible by arranging the barrier layer 2c nearest to the p-type layer side.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: January 12, 2010
    Assignee: Nichia Corporation
    Inventor: Tokuya Kozaki
  • Publication number: 20090289244
    Abstract: Nanowire devices comprising core-shell or segmented nanowires are provided. In these nanowire devices, strain can be used as a tool to form metallic portions in nanowires made from compound semiconductor materials, and/or to create nanowires in which embedded quantum dots experience negative hydrostatic pressure or high positive hydrostatic pressure, whereby a phase transitions may occur, and/or to create exciton crystals.
    Type: Application
    Filed: April 22, 2009
    Publication date: November 26, 2009
    Inventors: Craig Pryor, Mats-Erik Pistol
  • Patent number: 7619238
    Abstract: A light emitting heterostructure and/or device in which the light generating structure is contained within a potential well is provided. The potential well is configured to contain electrons, holes, and/or electron and hole pairs within the light generating structure. A phonon engineering approach can be used in which a band structure of the potential well and/or light generating structure is designed to facilitate the emission of polar optical phonons by electrons entering the light generating structure. To this extent, a difference between an energy at a top of the potential well and an energy of a quantum well in the light generating structure can be resonant with an energy of a polar optical phonon in the light generating structure material. The energy of the quantum well can comprise an energy at the top of the quantum well, an electron ground state energy, and/or the like.
    Type: Grant
    Filed: October 9, 2006
    Date of Patent: November 17, 2009
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Remigijus Gaska, Michael Shur, Jianping Zhang
  • Patent number: 7608192
    Abstract: An image sensor and a method for fabricating the same are provided. The image sensor includes a first conductive type substrate including a trench formed in a predetermined portion of the first conductive type substrate, a second conductive type impurity region for use in a photodiode, formed below a bottom surface of the trench in the first conductive type substrate, and a first conductive type epitaxial layer for use in the photodiode, buried in the trench.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: October 27, 2009
    Inventors: Hee Jeen Kim, Han Seob Cha
  • Patent number: 7605531
    Abstract: A full color display comprising a red, a green, and a blue light emitting diode, each light emitting diode including a light emitting region having at least one layer of single crystal rare earth material, the rare earth material in each of the light emitting diodes having at least one radiative transition, and the rare earth material producing a radiation wavelength of approximately 640 nm in the red light emitting diode, 540 nm in the green light emitting diode, and 460 nm in the blue light emitting diode. Generally, the color of each LED is determined by selecting a rare earth with a radiative transition producing a radiation wavelength at the selected color. In cases where the rare earth has more than one radiative transition, tuned mirrors can be used to select the desired color.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: October 20, 2009
    Assignee: Translucent, Inc.
    Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
  • Publication number: 20090256136
    Abstract: Various embodiments of the present invention are related to microresonator systems that can be used as a laser, a modulator, and a photodetector and to methods for fabricating the microresonator systems. In one embodiment, a microdisk comprises: a top layer; a bottom layer; an intermediate layer having at least one quantum well, the intermediate layer sandwiched between the top layer and the bottom layer; a peripheral annular region including at least a portion of the top, intermediate, and bottom layers; and a current isolation region configured to occupy at least a portion of a central region of the microdisk including at least a portion of the top, intermediate, and bottom layers and having relatively lower index of refraction than the peripheral annular region.
    Type: Application
    Filed: June 5, 2009
    Publication date: October 15, 2009
    Inventors: Michael Renne Ty Tan, Shih-Yuan Wang, Duncan Stewart, David A. Fattal
  • Patent number: 7589346
    Abstract: A GaN based semiconductor light-emitting device is provided. The light-emitting device includes a first GaN based compound semiconductor layer of an n-conductivity type; an active layer; a second GaN based compound semiconductor layer; an underlying layer composed of a GaN based compound semiconductor, the underlying layer being disposed between the first GaN based compound semiconductor layer and the active layer; and a superlattice layer composed of a GaN based compound semiconductor doped with a p-type dopant, the superlattice layer being disposed between the active layer and the second GaN based compound semiconductor layer.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: September 15, 2009
    Assignee: Sony Corporation
    Inventors: Goshi Biwa, Hiroyuki Okuyama
  • Patent number: 7579618
    Abstract: A resonant transistor includes a substrate, a source and a drain formed on the substrate, an input electrode and a carbon nanotube gate. A gap is formed between the source and the drain. The input electrode is formed on the substrate. The carbon nanotube gate is clamped on one end by a contact electrode and positioned, preferably cantilevered, over the gap and over the input electrode.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: August 25, 2009
    Assignee: Northrop Grumman Corporation
    Inventor: John Douglas Adam
  • Patent number: 7564096
    Abstract: A field effect transistor (FET) includes a semiconductor region of a first conductivity type and a well region of a second conductivity type extending over the semiconductor region. A gate electrode is adjacent to but insulated from the well region, and a source region of the first conductivity type is in the well region. A heavy body region is in electrical contact with the well region, and includes a material having a lower energy gap than the well region.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: July 21, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Qi Wang, Ming-Huang Huang, Joelle Sharp
  • Patent number: 7560750
    Abstract: In a photoelectric conversion device, in a contact between a p-type semiconductor 3a and an electrode 2, an n-type semiconductor 6 of a conductivity type opposite to that of the p-type semiconductor is provided between the p-type semiconductor 3a and the electrode 2. The existence of the n-type semiconductor 6 allows a recombination rate of photo-generated carriers excited by incident light to be effectively reduced, and allows a dark current component to be effectively prevented from being produced. Therefore, it is possible to improve photoelectric conversion efficiency as well as to stabilize characteristics. Further, a tunnel junction is realized by increasing the concentration of a doping element in at least one or preferably both of the p-type semiconductor 3a and the n-type semiconductor 6 in a region where they are in contact with each other, thereby keeping ohmic characteristics between the semiconductor and the electrode good.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: July 14, 2009
    Assignee: Kyocera Corporation
    Inventors: Koichiro Niira, Hirofumi Senta, Hideki Hakuma
  • Patent number: 7541610
    Abstract: A light source is provided including an LED component having an emitting surface, which may include: i) an LED capable of emitting light at a first wavelength; and ii) a re-emitting semiconductor construction which includes a second potential well not located within a pn junction having an emitting surface; or which may alternately include a first potential well located within a pn junction and a second potential well not located within a pn junction; and which additionally includes a converging optical element.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: June 2, 2009
    Assignee: 3M Innovative Properties Company
    Inventor: Michael A. Haase
  • Patent number: 7531827
    Abstract: A light emitting diode (LED) and a method for fabricating the same, capable of improving brightness by forming a InGaN layer having a low concentration of indium, and whose lattice constant is similar to that of an active layer of the LED, is provided. The LED includes: a buffer layer disposed on a sapphire substrate; a GaN layer disposed on the buffer layer; a doped GaN layer disposed on the GaN layer; a GaN layer having indium disposed on the GaN layer; an active layer disposed on the GaN layer having indium; and a P-type GaN disposed on the active layer. Here, an empirical formula of the GaN layer having indium is given by In(x)Ga(1-x)N and a range of x is given by 0<x<2, and a thickness of the GaN layer having indium is 50-200 ?.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: May 12, 2009
    Assignee: LG Innotek Co., Ltd.
    Inventor: Seong Jae Kim
  • Patent number: 7525131
    Abstract: Disclosed is a photoelectric surface including: a first group III nitride semiconductor layer that produces photoelectrons according to incidence of ultraviolet rays; and a second group III nitride semiconductor layer provided adjacent to the first group III nitride semiconductor layer and made of a thin-film crystal having c-axis orientation in a thickness direction, the second group III nitride semiconductor layer having an Al composition higher than that of the first group III nitride semiconductor layer.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: April 28, 2009
    Assignees: National University Corporation Shizuoka University, Hamamatsu Photonics K.K.
    Inventors: Masatomo Sumiya, Shunro Fuke, Tokuaki Nihashi, Minoru Hagino
  • Patent number: 7522647
    Abstract: An intrinsic GaAs waveguide layer is formed on a p-type AlGaAs cladding layer, a quantum dot active layer is formed further thereon. An n-type AlGaAs cladding layer is formed on the center portion of the quantum dot active layer. Thus-configured semiconductor laser is allowed to successfully suppress the area of the p-n junction plane to a small level, and to obtain a high level of reliability, because there is no need of processing the center portion of the quantum dot active layer, contributive to laser oscillation.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: April 21, 2009
    Assignees: Fujitsu Limited, The University of Tokyo
    Inventors: Nobuaki Hatori, Tsuyoshi Yamamoto, Koji Otsubo, Yasuhiko Arakawa
  • Patent number: 7462862
    Abstract: A semiconductor device can include a channel including an oxide comprising a combination of isovalent cations selected from within the D block and the P block of the Periodic Table.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: December 9, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Randy L. Hoffman, Gregory S. Herman
  • Patent number: 7459719
    Abstract: An optical semiconductor device includes an active layer having a quantum well structure including alternately stacked well layers and barrier layers with a larger band gap than the well layers. The band gap of each of the well layers and the barrier layers is constant, each well layer is uniformly provided with compression strain and each barrier layer is provided with large extension strain in a center portion thereof along the thickness direction and small extension strain in portions thereof in the vicinity of the well layers.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: December 2, 2008
    Assignee: Panasonic Corporation
    Inventors: Jun Shimizu, Tetsuzo Ueda, Toshikazu Onishi
  • Patent number: 7456442
    Abstract: The invention provides a device having a substrate, a buffer region positioned upon the substrate, wherein the buffer region has an upper buffer region and a lower buffer region, a heterojunction region positioned upon the buffer region, and a superlattice positioned between the lower buffer region and the upper buffer region, wherein the device is configured to function as a heterojunction field effect transistor.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: November 25, 2008
    Assignee: International Rectifier Corporation
    Inventor: Gordon Munns
  • Patent number: 7429748
    Abstract: A method and a layered heterostructure for forming high mobility Ge channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, and a channel structure of a compressively strained epitaxial Ge layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility for complementary MODFETs and MOSFETs. The invention overcomes the problem of a limited hole mobility due to alloy scattering for a p-channel device with only a single compressively strained SiGe channel layer. This invention further provides improvements in mobility and transconductance over deep submicron state-of-the art Si pMOSFETs in addition to having a broad temperature operation regime from above room temperature (425 K) down to cryogenic low temperatures (0.4 K) where at low temperatures even high device performances are achievable.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: September 30, 2008
    Assignee: International Business Machines Corporation
    Inventor: Jack O. Chu
  • Patent number: 7414260
    Abstract: The disclosed embodiments relate to a vertical tunneling transistor that may include a channel disposed on a substrate. A quantum dot may be disposed so that an axis through the channel and the quantum dot is substantially perpendicular to the substrate. A gate may be disposed so that an axis through the channel, the quantum dot and the gate is substantially perpendicular to the substrate.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: August 19, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 7408183
    Abstract: A method and structure for producing lasers having good optical wavefront characteristics, such as are needed for optical storage includes providing a laser wherein an output beam emerging from the laser front facet is essentially unobstructed by the edges of the semiconductor chip in order to prevent detrimental beam distortions. The semiconductor laser structure is epitaxially grown on a substrate with at least a lower cladding layer, an active layer, an upper cladding layer, and a contact layer. Dry etching through a lithographically defined mask produces a laser mesa of length lc and width bm. Another sequence of lithography and etching is used to form a ridge structure with width w on top of the mesa. The etching step also forming mirrors, or facets, on the ends of the laser waveguide structures. The length ls and width bs of the chip can be selected as convenient values equal to or longer than the waveguide length lc and mesa width bm, respectively.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: August 5, 2008
    Assignee: Binoptics Corporation
    Inventors: Alex A. Behfar, Wilfried Lenth
  • Patent number: 7407858
    Abstract: A method of fabricating a RRAM includes preparing a substrate and forming a bottom electrode ori the substrate. A PCMO layer is deposited on the bottom electrode using MOCVD or liquid MOCVD, followed by a post-annealing process. The deposited PCMO thin film has a crystallized PCMO structure or a nano-size and amorphous PCMO structure. A top electrode is formed on the PCMO layer.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: August 5, 2008
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Tingkai Li, Sheng Teng Hsu, David R. Evans
  • Patent number: 7402832
    Abstract: The invention relates to a quantum dot. The quantum dot comprises a core including a semiconductor material Y selected from the group consisting of Si and Ge. The quantum dot also comprises a shell surrounding the core. The quantum dot is substantially defect free such that the quantum dot exhibits photoluminescence with a quantum efficiency that is greater than 10 percent.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: July 22, 2008
    Assignee: UltraDots, Inc.
    Inventor: Howard Wing Hoon Lee
  • Patent number: 7397062
    Abstract: One aspect of the present invention is directed to a heterojunction bipolar transistor (HBT) comprising: a substrate; a buffer layer of undoped semiconductor material; a sub-collector layer; a collector layer; a base layer; an emitter layer; a emitter cap layer; and a contact layer; wherein a planar doping sheet is included between the substrate layer and the collector layer; and a collector electrode in electrical connection to said collector layer; a base electrode in electrical connection with said base layer; and an emitter electrode provided in electrical connection to said emitter layer.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: July 8, 2008
    Assignee: Sumika Electronic Materials, Inc.
    Inventors: Kenneth Lee Campman, Brian Anthony Novak
  • Patent number: 7378681
    Abstract: A method for reducing surface recombination in an area next to a mesa in devices containing active and passive sections. This is obtained by growing, by metalorganic vapor phase epitaxy (MOVPE), a thin epitaxial layer of material with larger bandgap than a waveguide material and preferably smaller surface recombination rate than the waveguide material. This thin layer is preferably non-intentionally doped to avoid creating a surface leakage path, thin enough to allow for carrier to diffuse to and thermalize in the waveguide layer and thick enough to prevent carriers to tunnel through it.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: May 27, 2008
    Assignee: Agility Communications, Inc.
    Inventor: Patrick Abraham
  • Patent number: 7375367
    Abstract: A semiconductor light-emitting device fabricated in a nitride material system has an active region disposed over a substrate. The active region comprises a first aluminium-containing layer forming the lowermost layer of the active region, a second aluminium-containing layer forming the uppermost layer of the active region, and at least one InGaN quantum well layer disposed between the first aluminium-containing layer and the second aluminum-containing layer. The aluminium-containing layers provide improved carrier confinement in the active region, and so increase the output optical power of the device.
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: May 20, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Stewart Hooper, Valerie Bousquet, Katherine L. Johnson, Jonathan Heffernan
  • Patent number: 7358525
    Abstract: The invention relates to a quantum dot. The quantum dot comprises a core including a semiconductor material Y selected from the group consisting of Si and Ge. The quantum dot also comprises a shell surrounding the core. The quantum dot is substantially defect free such that the quantum dot exhibits photoluminescence with a quantum efficiency that is greater than 10 percent.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: April 15, 2008
    Assignee: UltraDots, Inc.
    Inventor: Howard Wing Hoon Lee
  • Patent number: 7351993
    Abstract: Atomic layer epitaxy (ALE) is applied to the fabrication of new forms of rare-earth oxides, rare-earth nitrides and rare-earth phosphides. Further, ternary compounds composed of binary (rare-earth oxides, rare-earth nitrides and rare-earth phosphides) mixed with silicon and or germanium to form compound semiconductors of the formula RE-(O, N, P)-(Si,Ge) are also disclosed, where RE=at least one selection from group of rare-earth metals, O=oxygen, N=nitrogen, P=phosphorus, Si=silicon and Ge=germanium. The presented ALE growth technique and material system can be applied to silicon electronics, opto-electronic, magneto-electronics and magneto-optics devices.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: April 1, 2008
    Assignee: Translucent Photonics, Inc.
    Inventor: Petar B. Atanackovic
  • Publication number: 20080048176
    Abstract: A semiconductor device includes a semiconductor superlattice layer and a semiconductor multilayer. The semiconductor superlattice layer has periodic concave-convex shapes, and a plurality of semiconductor films each having bent portions in accordance with the concave-convex shapes are stacked in the semiconductor superlattice layer. The semiconductor multilayer is formed so as to cover the concave-convex shapes and includes an active layer.
    Type: Application
    Filed: August 27, 2007
    Publication date: February 28, 2008
    Inventors: Kenji Orita, Yasuyuki Fukushima
  • Patent number: 7335908
    Abstract: A resonant tunneling diode, and other one dimensional electronic, photonic structures, and electromechanical MEMS devices, are formed as a heterostructure in a nanowhisker by forming length segments of the whisker with different materials having different band gaps.
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: February 26, 2008
    Assignee: QuNano AB
    Inventors: Lars Ivar Samuelson, Bjorn Jonas Ohlsson
  • Patent number: 7329895
    Abstract: A sensor comprises two photodiodes sensitive to different wavelengths. The photodiodes or detectors are stacked in a vertical relationship to each other. A bandpass filter is provided to limit the wavelengths of light reaching the detectors. The photodiodes are formed of various combinations of materials such as AlGaN or InGaN, or different compositions of the same material. Charge detectors are coupled to each detector to provide a signal representative of the amount of radiation detected in their corresponding bandwidths. A biological sample is provided proximate the filter. A laser is used to illuminate the biological sample to create biofluorescence corresponding to intrinsic tryptophan of bacteria.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: February 12, 2008
    Assignee: Honeywell International Inc.
    Inventors: Barrett E. Cole, Wei Yang, Thomas E. Nohava
  • Publication number: 20080019410
    Abstract: A surface emitting semiconductor device comprises: a semiconductor region including an active layer; a first DBR having first layers and second layers; and a second DBR. The first and second layers are alternately arranged, and the first layers are made of dielectric material. The first DBR, semiconductor region and second DBR are sequentially arranged along a predetermined axis, and the semiconductor region is provided between the first DBR and the second DBR. The cross section of the first DBR is taken along a reference plane perpendicular to the predetermined axis. The distance between two points on an edge of the cross section takes a first value in a direction of an X-axis of a two-dimensional XY orthogonal coordinate system defined on the reference plane, and the distance between two points on the edge takes a second value in a direction of a Y-axis of the above coordinate system. The first value is different from the second value.
    Type: Application
    Filed: July 19, 2007
    Publication date: January 24, 2008
    Inventor: Yutaka Onishi
  • Patent number: 7276724
    Abstract: Series interconnection of optoelectronic device modules is disclosed. Each device module includes an active layer disposed between a bottom electrode and a transparent conducting layer. An insulating layer is disposed between the bottom electrode of a first device module and a backside top electrode of the first device module. One or more vias are formed through the active layer, transparent conducting layer and insulating layer of the first device module. Sidewalls of the vias are coated with an insulating material such that a channel is formed through the insulating material to the backside top electrode of the first device module. The channel is at least partially filled with an electrically conductive material to form a plug that makes electrical contact between the transparent conducting layer and the backside top electrode of the first device module.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: October 2, 2007
    Assignee: Nanosolar, Inc.
    Inventors: James R. Sheats, Sam Kao, Gregory A. Miller, Martin R. Roscheisen
  • Patent number: 7259406
    Abstract: A semiconductor optical element having a includes an n-type GaAs buffer layer, an n-type AlGaInP cladding layer, a first InGaAsP (including zero As content)guide layer without added dopant impurities, an InGaAsP (including zero In content) active layer, a second InGaAsP (including zero As content)guide layer without added dopant impurities, a p-type AlGaInP cladding layer, a p-type band discontinuity reduction layer, and a p-type GaAs contact layer sequentially laminated on an n-type GaAs substrate C or Mg is the dopant impurity in the p-type GaAs contact layer, the p-type band discontinuity reduction layer, and the p-type AlGaInP cladding layer.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: August 21, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshihiko Hanamaki, Kenichi Ono, Kimio Shigihara, Kazushige Kawasaki, Kimitaka Shibata, Naoyuki Shimada
  • Patent number: 7253431
    Abstract: A method is provided for doping a carbon nanotube. The method comprises exposing the nanotube to a one-electron oxidant in a solution phase. A method is also provided for forming a carbon nanotube FET device.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: August 7, 2007
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Phaedon Avouris, Jia Chen, Christian Klinke, Paul M. Solomon
  • Patent number: 7244959
    Abstract: An apparatus and method for detecting electromagnetic radiation employs a deflectable micromechanical apparatus incorporating multiple quantum wells structures. When photons strike the quantum-well structure, physical stresses are created within the sensor, similar to a “bimetallic effect.” The stresses cause the sensor to bend. The extent of deflection of the sensor can be measured through any of a variety of conventional means to provide a measurement of the photons striking the sensor. A large number of such sensors can be arranged in a two-dimensional array to provide imaging capability.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: July 17, 2007
    Assignee: UT-Battelle, LLC
    Inventors: Panagiotis G. Datskos, Slobodan Rajic, Irene Datskou
  • Patent number: 7235475
    Abstract: Nanowire fluid sensors are provided. The fluid sensors comprise a first electrode, a second electrode, and at least one nanowire between the first electrode and the second electrode. Each nanowire is connected at a first end to the first electrode and at a second end to the second electrode. Methods of fabricating and operating the fluid sensor are also provided.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: June 26, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Theodore I. Kamins
  • Patent number: 7235809
    Abstract: A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: June 26, 2007
    Assignee: Intel Corporation
    Inventors: Been-Yih Jin, Brian S. Doyle, Scott A. Hareland, Mark L. Doczy, Matthew V. Metz, Boyan I. Boyanov, Suman Datta, Jack T. Kavalieros, Robert S. Chau
  • Patent number: 7233018
    Abstract: Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a substrate on which a Si layer having a well region, a SiGe epitaxial layer, and a Si epitaxial layer are stacked is formed. For the device having the heterojunction structure, the number of conduction carriers through a potential well and the mobility of the carriers increase to reduce an on resistance, thus increasing saturation current. Also, an intensity of vertical electric field decreases so that a breakdown voltage can be maintained at a very high level. Further, a reduction in vertical electric field due to the heterojunction structure leads to a gain in transconductance (Gm), with the results that a hot electron effect is inhibited and the reliability of the device is enhanced.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: June 19, 2007
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Young Kyun Cho, Sung Ku Kwon, Tae Moon Roh, Dae Woo Lee, Jong Dae Kim
  • Patent number: 7227177
    Abstract: A particle, includes a semiconductor nanocrystal. The nanocrystal is doped.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: June 5, 2007
    Assignee: Arch Development Corporation
    Inventors: Philippe Guyot-Sionnest, Moonsub Shim, Conjun Wang
  • Patent number: 7224041
    Abstract: For the first time, an aluminum antimonide (AlSb) single crystal substrate is utilized to lattice-match to overlying semiconductor layers. The AlSb substrate establishes a new design and fabrication approach to construct high-speed, low-power electronic devices while establishing inter-device isolation. Such lattice matching between the substrate and overlying semiconductor layers minimizes the formation of defects, such as threaded dislocations, which can decrease the production yield and operational life-time of 6.1-? family heterostructure devices.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: May 29, 2007
    Assignee: The Regents of the University of California
    Inventors: John W. Sherohman, Arthur W. Coombs, III, Jick Hong Yee, Kuang Jen J. Wu
  • Patent number: 7217948
    Abstract: The present invention relates to a preferred semiconductor substrate for the production of devices. The semiconductor substrate is comprised of GaAs. Then, a plurality of quantum rings, which are composed of GaSb and have a substantially elliptical shape with an aspect ratio of 2 or more but 5 or less, are formed on a surface of the semiconductor substrate. These quantum rings extend along in the substantially same direction. In a case where a light beam is irradiated onto the surface of the semiconductor substrate, among the polarized components of the irradiated light, one polarized component parallel to the long-axis direction of the ellipse that is an extending direction of each quantum ring is reflected, while another polarized component parallel to the short-axis direction thereof is transmitted. That is, the semiconductor substrate reflects one polarized component, and transmits the other polarized component.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: May 15, 2007
    Assignee: Hamamatsu Photonics K.K.
    Inventor: Tadataka Edamura
  • Patent number: 7211822
    Abstract: A nitride semiconductor device including a light emitting device comprises a n-type region of one or more nitride semiconductor layers having n-type conductivity, a p-type region of one or more nitride semiconductor layers having p-type conductivity and an active layer between the n-type region and the p-type region. In such devices, there is provided with a super lattice layer comprising first layers and second layers which are nitride semiconductors having a different composition respectively. The super lattice structure makes working current and voltage of the device lowered, resulting in realization of more efficient devices.
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: May 1, 2007
    Assignee: Nichia Chemical Industries, Ltd.
    Inventors: Shinichi Nagahama, Masayuki Senoh, Shuji Nakamura
  • Patent number: 7211821
    Abstract: A photonic device includes a silicon semiconductor based superlattice. The superlattice has a plurality of layers that form a plurality of repeating units. At least one of the layers in the repeating unit is an optically active layer with at least one species of rare earth ion.
    Type: Grant
    Filed: April 16, 2004
    Date of Patent: May 1, 2007
    Assignee: Translucent Photonics, Inc.
    Inventors: Petar B. Atanackovic, Larry R. Marshall
  • Patent number: 7208755
    Abstract: A light emitting device 1 has formed therein a light emitting layer section 24 based on a double heterostructure in which a p-type cladding layer 34, an active layer 33 and an n-type cladding layer 32, individually composed of a MgaZn1-aO (0?a?1) type oxide, are stacked in this order, and uses a face on the n-type cladding layer side as a light extraction surface. The device also has, as being provided on the main surface on the light extraction surface side of the n-type cladding layer 32, an n-type low resistivity layer 35 composed of a MgaZn1-aO type oxide, and having a content of an n-type dopant larger than that in the n-type cladding layer 32. There is thus provided a light emitting device of MgaZn1-aO-type oxide base, excellent in the light extraction efficiency, having the light emitting layer section composed of a MgaZn1-aO-type oxide, and a high conductivity MgZnO-base compound semiconductor layer disposed on the light extraction surface side.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: April 24, 2007
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Jun-ya Ishizaki
  • Patent number: 7193236
    Abstract: A nitride based 3-5 group compound semiconductor light emitting device comprising: a substrate; a buffer layer formed above the substrate; a first In-doped GaN layer formed above the buffer layer; an InxGa1—xN/InyGa1?yN super lattice structure layer formed above the first In-doped GaN layer; a first electrode contact layer formed above the InxGa1—xN/InyGa1?yN super lattice structure layer; an active layer formed above the first electrode contact layer and functioning to emit light; a second In-doped GaN layer; a GaN layer formed above the second In-doped GaN layer; and a second electrode contact layer formed above the GaN layer. The present invention can reduce crystal defects of the nitride based 3-5 group compound semiconductor light emitting device and improve the crystallinity of a GaN GaN based single crystal layer in order to improve the performance of the light emitting device and ensure the reliability thereof.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: March 20, 2007
    Assignee: LG Innotek Co., Ltd
    Inventor: Suk Hun Lee
  • Patent number: 7180066
    Abstract: A quantum-well infrared photodetector (QWIP) is presented. The photodetector includes a substrate, a buffer layer, a first conductive layer, a multiple quantum well, an optional blocking layer, and a second conductive layer. Substrate is composed of a monocrystal which may be removed after fabrication. Remaining layers are composed of group III-V nitrides, including binary, ternary, and quaternary compositions. Alternate embodiments of the present invention include a doped binary alloy along first and second conductive layers, a binary alloy along buffer and blocking layers, and alternating alloys of binary, ternary and quaternary compositions within the multiple quantum well. The present invention responds to infrared light at normal and oblique incidences, from near infrared to very far infrared.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: February 20, 2007
    Inventor: Chang-Hua Qiu
  • Patent number: 7166874
    Abstract: A nitride semiconductor device has a nitride semiconductor layer structure. The structure includes an active layer of a quantum well structure containing an indium-containing nitride semiconductor. A first nitride semiconductor layer having a band gap energy larger than that of the active layer is provided in contact with the active layer. A second nitride semiconductor layer having a band gap energy smaller than that of the first layer is provided over the first layer. Further, a third nitride semiconductor layer having a band gap energy larger than that of the second layer is provided over the second layer.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: January 23, 2007
    Assignee: Nichia Corporation
    Inventors: Shuji Nakamura, Shinichi Nagahama, Naruhito Iwasa
  • Patent number: 7157730
    Abstract: Ion implantation by mounting a semiconductor wafer on a rotating plate that is tilted at an angle relative to an ion implantation flux. The tilt angle and the ion implantation energy are adjusted to produce a desired implantation profile. Ion implantation of mesa structures, either through the semiconductor wafer's surface or through the mesa structure's wall is possible. Angled ion implantation can reduce or eliminate ion damage to the lattice structure along an aperture region. This enables beneficial ion implantation profiles in vertical cavity semiconductor lasers. Mask materials, beneficially that can be lithographically formed, can selectively protect the wafer during implantation. Multiple ion implantations can be used to form novel structures.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: January 2, 2007
    Assignee: Finisar Corporation
    Inventor: Tzu-Yu Wang
  • Patent number: 7145167
    Abstract: A method and a layered heterostructure for forming high mobility Ge channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, and a channel structure of a compressively strained epitaxial Ge layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility for complementary MODFETs and MOSFETs. The invention overcomes the problem of a limited hole mobility due to alloy scattering for a p-channel device with only a single compressively strained SiGe channel layer. This invention further provides improvements in mobility and transconductance over deep submicron state-of-the art Si pMOSFETs in addition to having a broad temperature operation regime from above room temperature (425 K) down to cryogenic low temperatures (0.4 K) where at low temperatures even high device performances are achievable.
    Type: Grant
    Filed: March 11, 2000
    Date of Patent: December 5, 2006
    Assignee: International Business Machines Corporation
    Inventor: Jack Oon Chu
  • Patent number: 7135699
    Abstract: Structure and method for growing crystalline superlattice rare earth oxides, rare earth nitrides and rare earth phosphides and ternary rare-earth compounds are disclosed. The structure includes a superlattice having a plurality of layers that forming a plurality of repeating units. At least one the layers in the repeating unit is an active layer with at least one species of rare earth ion.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: November 14, 2006
    Assignee: Translucent Photonics, Inc.
    Inventor: Petar B. Atanackovic