Abstract: An electronic package is provided, which includes: an insulating layer; an electronic element embedded in the insulating layer and having a sensing area exposed from the insulating layer; and a circuit layer formed on the insulating layer and electrically connected to the electronic element, thereby reducing the thickness of the overall package structure.

Abstract: An imaging device includes: a container including a bottom plate and a side wall provided on an outer circumferential portion of the bottom plate; a step portion which is formed in a top outer circumferential portion of the side wall and includes: a horizontal surface that is located at a lower position than a top surface of the side wall; and a side surface that connects the top surface of the side wall to the horizontal surface; an imaging element mounted on the bottom plate; a glass lid which is bonded to the top surface of the side wall with a first adhesive layer; and a cover frame which is disposed on the step portion and bonded to the side surface of the step portion and an outer circumferential surface of the glass lid with a second adhesive layer.

Abstract: An array imaging module includes a molded photosensitive assembly which includes a supporting member, at least a circuit board, at least two photosensitive units coupled at the chip coupling area of the circuit board, at least two lead wires electrically connected the photosensitive units at the chip coupling area of the circuit board, and a mold sealer which includes a main mold body and has two optical windows. When the main mold body is formed, the lead wires, the circuit board and the photosensitive units are sealed and molded by the main mold body of the mold sealer, such that at least a portion of the circuit board are integrally formed together at a position that the photosensitive units are aligned with the optical windows respectively.

Abstract: An image sensor may include pixels having nested sub-pixels. A pixel with nested sub-pixels may include an inner sub-pixel that has either an elliptical or a rectangular light collecting area. The inner sub-pixel may be formed in a substrate and may be immediately surrounded by a sub-pixel group that includes one or more sub-pixels. The inner sub-pixel may have a light collecting area at a surface that is less sensitive than the light collecting area of the one or more outer sub-pixel groups. Microlenses may be formed over the nested sub-pixels, to direct light away from the inner sub-pixel group to the outer sub-pixel groups in nested sub-pixels. A color filter of a single color may be formed over the nested sub-pixels. Hybrid color filters having a single color filter region over the inner sub-pixel and a portion of the one or more outer sub-pixel groups may also be used.

Abstract: A camera module which collects incoming dirt and dust so as to prevent the accumulation of same on an optical element of the image-capturing process includes a microscope base and an optical filter unit. The microscope base includes a supporting portion. A first gap is formed in the supporting portion. The optical filter unit filter and adhesive layer formed on the optical filter. The optical filter is bonded on the supporting portion by the adhesive layer. The optical filter comprises a filter area in the optical filter. A surface of the adhesive layer facing away from the optical filter is adhesive. A second gap is formed in the adhesive layer. The filter area is exposed from the second gap. Parts of the adhesive layer and the filter area are exposed from the first gap.

Abstract: A stack type sensor package structure includes a substrate, a semiconductor chip disposed on the substrate, a frame disposed on the substrate and aside the semiconductor chip, a sensor chip disposed on the frame, a plurality of wires electrically connecting the sensor chip and the substrate, a transparent layer being of its position corresponding to the sensor chip, a support maintaining the relative position between the sensor chip and the transparent layer, and a package compound disposed on the substrate and partially covering the frame, the support, and the transparent layer. Thus, through disposing a frame within the stack type sensor package structure, the structural strength of the overall sensor package structure is reinforced, and the stability of the wiring of the sensor chip is effectively increased.

Abstract: A manufacturing method of a metal gate structure includes the following steps. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. The silicon-containing work function layer includes a vertical portion and a horizontal portion. Finally, the gate trench is filled up with a conductive metal layer.

Abstract: A semiconductor device includes a substrate, a stacked structure on the substrate, and a vertical structure in a hole passing through the stacked structure. The stacked structure includes units stacked on top of each other in a direction perpendicular to a top surface of the substrate. The units include first units and second units between the first units. Each of the first units includes a first interlayer insulating layer on a first gate, and each of the second units includes a second interlayer insulating layer on a second gate. A ratio of a thickness of the second interlayer insulating layer with respect to a thickness of the second gate is different from a ratio of a thickness of the first interlayer insulating layer with respect to a thickness of the first gate.

Abstract: A camera module and array camera module with circuit board unit and photosensitive unit and manufacturing method thereof is provided. The array camera module comprises two or more camera lenses and a circuit unit. The circuit unit comprises a circuit board portion for electrically connecting two or more photosensitive sensors of the array camera module, and a conjoined encapsulation portion integrally encapsulated on the circuit board portion. The camera lenses are respectively arranged along the photosensitive paths of the photosensitive sensors.

Abstract: A camera module, a molded circuit board assembly, a molded photosensitive assembly and manufacturing method thereof are disclosed. The camera module includes a molded base which is integrally formed with a circuit board through a molding process, wherein a photosensitive element may be electrically connected on the circuit board and at least a portion of a non-photosensitive area portion of the photosensitive element is also connected by the molded base through the molding process. A light window is formed in a central portion of the molded base to provide a light path for the photosensitive element, wherein a cross section of the light window is configured to have a trapezoidal or multi-step trapezoidal shape which has a size increasing from bottom to top to facilitate demolding and avoiding stray lights.

Abstract: A linear image scanner capable of digitizing three-dimensional surfaces according to the photometric stereo technique has a linear type imaging sensor, a scanning plane, an optical system, an optical axis, a scan line, a lighting system with at least four independently controllable light sources arranged so that each light source enlighten the scan line from a different direction. At least two first light sources are arranged symmetrically respect to the vision plane and at least two second light sources are arranged symmetrically respect to the moving plane and so that the at least two first and two second light sources radiate the scan line from at least four different directions with uniform light intensity and uniform incident angles of the light sources over the entire length of the scan line. A scanning method is also described.

Abstract: A camera module and array camera module with circuit board unit and photosensitive unit and manufacturing method thereof is provided. The array camera module comprises two or more camera lenses and a circuit unit. The circuit unit comprises a circuit board portion for electrically connecting two or more photosensitive sensors of the array camera module, and a conjoined encapsulation portion integrally encapsulated on the circuit board portion. The camera lenses are respectively arranged along the photosensitive paths of the photosensitive sensors.

Abstract: A camera module and array camera module with circuit board unit and photosensitive unit and manufacturing method thereof is provided. The array camera module comprises two or more camera lenses and a circuit unit. The circuit unit comprises a circuit board portion for electrically connecting two or more photosensitive sensors of the array camera module, and a conjoined encapsulation portion integrally encapsulated on the circuit board portion. The camera lenses are respectively arranged along the photosensitive paths of the photosensitive sensors.

Abstract: A packaged sensor assembly and method of forming that includes a first substrate having opposing first and second surfaces and a plurality of conductive elements each extending between the first and second surfaces. A second substrate comprises opposing front and back surfaces, one or more detectors formed on or in the front surface, and a plurality of contact pads formed at the front surface which are electrically coupled to the one or more detectors. A third substrate is mounted to the front surface to define a cavity between the third substrate and the front surface, wherein the third substrate includes a first opening extending from the cavity through the third substrate. The back surface is mounted to the first surface. A plurality of wires each extend between and electrically connecting one of the contact pads and one of the conductive elements.

Abstract: An image sensor device may include an interconnect layer, an image sensor IC carried by the interconnect layer and having an image sensing surface, and encapsulation material laterally surrounding the image sensor IC and covering an upper surface of the image sensor IC up to the image sensing surface. The image sensor device may include an optical plate having a peripheral lower surface carried by an upper surface of the encapsulation material and aligned with the image sensing surface, the optical plate being spaced above the image sensing surface to define an internal cavity, and a lens assembly coupled to the encapsulation material and aligned with the image sensing surface.

Abstract: An image sensor device may include an interconnect layer, an image sensor IC adjacent the interconnect layer and having an image sensing surface, and a dielectric layer adjacent the image sensor IC and having an opening therein aligned with the image sensing surface. The image sensor device may also include an IR filter adjacent and aligned with the image sensing surface, and an encapsulation material adjacent the dielectric layer and laterally surrounding the IR filter.

Abstract: An image sensor device may include an interconnect layer having an opening extending therethrough, an image sensor IC within the opening and having an image sensing surface, and an IR filter aligned with the image sensing surface. The image sensor device may include an encapsulation material laterally surrounding the image sensor IC and filling the opening, and a flexible interconnect layer coupled to the interconnect layer opposite the image sensing surface.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers stacked alternately with a plurality of insulating layers on the substrate, a channel body provided inside a hole piercing the stacked body, and a memory portion provided between the channel body and each of the plurality of electrode layers. The hole has a large diameter portion and a small diameter portion. The diameter of the hole is smaller at the small diameter portion than at the large diameter portion. A thickness of the electrode layer adjacent to the small diameter portion is thicker than a thickness of the electrode layer adjacent to the large diameter portion.

Abstract: In a TDI-type linear image sensor in which pixels are constituted of CCDs (Charge Coupled Devices) of n phases (n being an integer not smaller than 3), a gate opening portion and a gate non-opening portion functioning as a TDI transfer channel (15) are formed in all of transfer gates of the CCDs of n phases constituting the pixels. Within one pixel pitch in a TDI transfer direction, n microlenses (18) are formed such that light is concentrated at the gate non-opening portion formed at the transfer gate of each phase.

Abstract: A pair of first gate electrodes IGR, IGL are provided on a semiconductor substrate 100 so that potentials ?TX1, ?TX2 between a light-sensitive area SA and a pair of first accumulation regions AR, AL alternately ramp. A pair of second gate electrodes IGR, IGL are provided on the semiconductor substrate 100 so as to control the height of first potential barriers ?BG each interposed between the first accumulation region AR, AL and a second accumulation region FDR, FDL, and increase the height of the first potential barrier ?BG to carriers as a higher output of a background light is detected by a photodetector.

Abstract: An image sensor for a semiconductor light-sensitive device including a semiconductor substrate and a light receiving device configured to receive light and generate a signal from the light. The image sensor may include an electron collecting device formed in the semiconductor substrate to receive at least a portion of the electrons generated by the light in the light receiving device. The image sensor may include a first type device isolation film configured to isolate the light receiving device from the electron collecting device. The image sensor may include a shielding film formed over the semiconductor substrate and configured to shield the first electron collecting device from the light.

Abstract: A photosensor chip package structure comprises a substrate, a light-emitting chip and a photosensor chip including an ambient light sensing unit and a proximity sensing unit. The substrate has a first basin, a second basin and a light-guiding channel. The openings of the first and second basins respectively face different directions. One opening of the light-guiding channel and the opening of the first basin face the same direction. The other opening of the light-guiding channel interconnects with the second basin. The light-emitting chip is arranged in the first basin. The photosensor chip is arranged in the second basin. The light-guiding channel conducts the light generated by the light-emitting chip and the ambient light to the photosensor chip. The photosensor chip operates as soon as it receives the light generated by the light-emitting chip and/or the ambient light.

Abstract: An integrated circuit includes a substrate. The substrate includes diffusion lines. The diffusion lines include impurities diffused into the substrate. A signal line layer includes first signal lines. A first metal layer includes second signal lines. The second signal lines include a first metallic material. A second metal layer includes third signal lines. The third signal lines include a second metallic material. First contacts connect the diffusion lines to (i) a first set of the second signal lines, or (ii) a first set of the third signal lines. Second contacts connect a first set of the first signal lines to a second set of the third signal lines. Each signal line in a first set of the second signal lines includes first portions and second portions. The first portions extend towards and are not connected to the second contacts. The first portions are not parallel to the second portions.

Abstract: In a semiconductor device in which a glass substrate is attached to a surface of a semiconductor die with an adhesive layer being interposed therebetween, it is an object to fill a recess portion of an insulation film formed on a photodiode with the adhesive layer without bubbles therein. In a semiconductor die in which an optical semiconductor integrated circuit including a photodiode having a recess portion of an interlayer insulation film in the upper portion, an NPN bipolar transistor, and so on are formed, generally, a light shield film covers a portion except the recess portion region on the photodiode and except a dicing region. In the invention, an opening slit is further formed in the light shield film, extending from the recess portion to the outside of the recess portion, so as to attain the object.

Abstract: The present invention provides a solid-state imaging device in which high S/N is achieved. A solid-state imaging device includes a photodiode, a transfer transistor, a floating diffusion, a floating diffusion wiring, an amplifying transistor, a power line, and first output signal lines, in which the first output signal lines are formed one on each side of the floating diffusion wiring in a layer having the floating diffusion wiring formed on a semiconductor substrate, and the power line is formed above the floating diffusion wiring.

Abstract: There is provided a linear sensor including a plurality of sensor elements that are disposed in line, each including a light sensing part that senses light, generates an electric charge according to an amount of the sensed light, and accumulates the electric charge, a readout gate used to read out the electric charge accumulated in the light sensing part, and a reset gate used to discharge the electric charge accumulated in the light sensing part so as to be reset, wherein a region having a highest concentration of an impurity included in the light sensing part is formed in a position similarly away from the readout gate and the reset gate in the light sensing part.

Abstract: A solid-state imaging device includes a semiconductor substrate; a first conductive region of the semiconductor substrate; a first conductive region on an upper surface side of the first conductive region of the semiconductor substrate; a second conductive region below the first conductive region on the upper surface side of the first conductive region of the semiconductor substrate. The solid-state imaging device further includes a photoelectric conversion region including the first conductive region located on the upper surface side of the first conductive region of the semiconductor substrate and the second conductive region and a transfer transistor transferring charges accumulated in the photoelectric conversion region to a readout region; and a pixel including the photoelectric conversion region and the transfer transistor. The first conductive region, which is included in the photoelectric conversion region, extends to the lower side of a sidewall of a gate electrode of the transfer transistor.

Abstract: A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with replacement metal gate (RMG) and high-k/metal gate (HKMG) modules. Embodiments include forming two substrate portions having upper surfaces at different heights, forming non-volatile gate stacks over the substrate portion with the lower upper surface, and forming high-voltage gate stacks and logic gate stacks over the other substrate portion. Embodiments include the upper surfaces of the non-voltage gate stacks, the high-voltage gate stacks, and the logic gate stacks being substantially coplanar.

Abstract: A solid-state image sensing device includes a plurality of pixels. Each pixel has a photodiode, a first transistor, and a second transistor. The photodiode is constituted by a first-conductivity-type semiconductor region and a second-conductivity-type semiconductor region. The first and second conductivity types are opposite to each other. The first transistor has a first-conductivity-type drain region formed in the second-conductivity-type semiconductor region to transfer signal charge to the drain region. The second transistor has a source region and a drain region which are formed in the second-conductivity-type semiconductor region and which have the first conductivity type. At least one second-conductivity-type potential barrier is provided under the drain region of the first transistor and the source region and/or the drain region of the second transistor.

Abstract: A multiple layer tunnel insulator is fabricated between a substrate and a discrete trap layer. The properties of the multiple layers determines the volatility of the memory device. The composition of each layer and/or the quantity of layers is adjusted to fabricate either a DRAM device, a non-volatile memory device, or both simultaneously.

Abstract: A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit includes a plurality of bit line structures, a plurality of word line structures intersecting said plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at said plurality of cell locations, each of said cells being selectively coupled to a corresponding bit line structure under control of a corresponding word line structure, each of said cells comprising a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor, wherein said at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of said bit line structures, and said at least first p-type field effect transistor is formed with a relatively thin buried oxide layer.

Abstract: MEMS devices (such as interferometric modulators) may be fabricated using a sacrificial layer that contains a heat vaporizable polymer to form a gap between a moveable layer and a substrate. One embodiment provides a method of making a MEMS device that includes depositing a polymer layer over a substrate, forming an electrically conductive layer over the polymer layer, and vaporizing at least a portion of the polymer layer to form a cavity between the substrate and the electrically conductive layer.

Abstract: A method manufactures semiconductor chips each comprising a component implanted in the semiconductor. The method includes collectively implanting components onto a front face of a semiconductor wafer and fixing a plate of a transparent material onto the front face of the wafer. Fixing the plate of transparent material is preceded by a step of depositing, on the front face of the wafer, at least one layer of polymer material forming an optical filter. Application is particularly to the manufacturing of imagers.

Abstract: An image scanning device includes a CCD pair provided with two rows of photodiode arrays for scanning an image on a paper, a motor drive circuit for causing the CCD pair to sub-scan the image on the paper, and an adder for superimposedly combining two outputs of the CCD pair with a predetermined time lag therebetween. A control unit controls the adder to add the two outputs of the CCD pair without the time lag when received an instruction of a low resolution that corresponds to ½ of a high resolution by a resolution switch and thereby doubles a speed of the sub-scan by the motor drive circuit.

Abstract: A charge accumulation region of a first conductivity type is buried in a semiconductor substrate. A charge transfer destination diffusion layer of the first conductivity type is formed on a surface of the semiconductor substrate. A transfer gate electrode is formed on the charge accumulation region, and charge is transferred from the charge accumulation region to the charge transfer destination diffusion layer.

Abstract: An object of the present invention is to provide a photoelectric conversion device, wherein improvement of charge transfer properties when charge is output from a charge storage region and suppression of dark current generation during charge storage are compatible with each other. This object is achieved by forming a depletion voltage of a charge storage region in the range from zero to one half of a power source voltage (V), forming a gate voltage of a transfer MOS transistor during a charge transfer period in the range from one half of the power source voltage to the power source voltage (V) and forming a gate voltage of the transfer MOS transistor during a charge storage period in the range from minus one half of the power source voltage to zero (V).

Abstract: A memory array including a diffusion layer, a poly layer, a metal one layer, a metal two layer, and a contact. The diffusion layer comprises diffusion lines extending in a first direction. The poly layer comprises poly lines extending in the first direction and being arranged on top of and insulated from the diffusion layer. The metal one layer comprises metal one lines extending in the first direction and being arranged on top of and insulated from the poly layer. The metal two layer comprises a metal two line extending in the first direction and being arranged on top of and insulated from the metal one layer. The contact extends through the poly layer, and connects a metal one line to a diffusion line. A poly line further extends in a second direction to bend around the contact such that a predetermined distance separates the poly lines from the contact.

Abstract: A memory circuit includes a plurality of bit line structures, a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells is selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures, and each of the cells in turn includes a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor. The at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of the bit line structures, and the at least first p-type field effect transistor is formed with a relatively thin buried oxide layer.

Abstract: An image sensor and a method for fabricating the same are provided. The image sensor includes a first conductive type substrate including a trench formed in a predetermined portion of the first conductive type substrate, a second conductive type impurity region for use in a photodiode, formed below a bottom surface of the trench in the first conductive type substrate, and a first conductive type epitaxial layer for use in the photodiode, buried in the trench.

Abstract: A unit pixel of an image sensor having a three-dimensional structure includes a first chip and a second chip which are stacked, one of the first chip and the second chip having a photodiode, and the other of the first chip and the second chip having a circuit for receiving information from the photodiode and outputting received information. The first chip includes a first pad which is projectedly disposed on an upper surface of the first chip in such a way as to define a concavo-convex structure, and the second chip includes a second pad which is depressedly disposed on an upper surface of the second chip in such a way as to define a concavo-convex structure corresponding to the concavo-convex structure of the first chip. The first chip and the second chip are mated with each other through bonding of the first pad and the second pad.

Abstract: A molecular device includes a gold electrode, cytochrome c552 or a derivative or variant thereof immobilized on the gold electrode, and an electron transfer protein coupled to the cytochrome c552 or the derivative or variant thereof. Electrons or holes, or both, are transferred through the electron transfer protein by transition of electrons between molecular orbitals of the electron transfer protein.

Abstract: A semiconductor device of the present invention includes a semiconductor substrate, a semiconductor element formed in the semiconductor substrate, a surface layer formed on the semiconductor substrate, and a capacitance type sensor formed on the surface layer. The surface layer has a planar portion whose surface is planar. The capacitance type sensor includes a lower thin film parallelly opposed to the surface of the planar portion and an upper thin film opposed to the lower thin film at a prescribed interval on the side opposite to the surface layer.

Abstract: A CMOS image sensor for improving light sensitivity and peripheral brightness ratio, and a method for fabricating the same. The CMOS image sensor includes a substrate on which a light sensor and device isolating insulation films are formed, in which the top of the substrate is coated with a plurality of metal layers and oxide films; a plurality of reflective layers formed inside the metal layers, each being spaced apart; a color filter embedded in a groove formed by etching the oxide films inside the reflective layers by a predetermined thickness; a plurality of protrusions formed on both sides of the top of the color filter, each arranged at a predetermined distance from one another; a flat layer formed on the top of the protrusions and the oxide films; and a micro-lens formed on the top of the flat layer. The reflective layer disposed at the top of the photodiode is made of a material having a high reflectance and low absorptivity.

Abstract: Methods for forming electrically conductive through-wafer interconnects in microelectronic devices and microelectronic devices are disclosed herein. In one embodiment, a microelectronic device can include a monolithic microelectronic substrate with an integrated circuit has a front side with integrated circuit interconnects thereon. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, first and second conductive layers deposited onto at least a portion of the dielectric liner, and a conductive fill material deposited into the passage over at least a portion of the second conductive layer and electrically coupled to the bond-pad.

Abstract: An integrated circuit includes a plurality of signal lines. A first signal line layer includes a plurality of first signal lines. A second signal line layer includes a plurality of second signal lines arranged on top of and insulated from the first signal line layer. A third signal line layer includes a plurality of third signal lines arranged on top of and insulated from the second signal line layer. A contact extends through the second signal line layer and connects at least one of the plurality of third signal lines to at least one of the first signal lines. At least one of the second signal lines further extends in a second direction to bend around the contact such that a predetermined distance separates the plurality of second signal lines from the contact.

Abstract: An object of the present invention is to provide a photoelectric conversion device, wherein improvement of charge transfer properties when charge is output from a charge storage region and suppression of dark current generation during charge storage are compatible with each other. This object is achieved by forming a depletion voltage of a charge storage region in the range from zero to one half of a power source voltage (V), forming a gate voltage of a transfer MOS transistor during a charge transfer period in the range from one half of the power source voltage to the power source voltage (V) and forming a gate voltage of the transfer MOS transistor during a charge storage period in the range from minus one half of the power source voltage to zero (V).

Abstract: An optical module includes an image sensor having an active area and a window mounted directly to the image sensor above the active area. The optical module further includes a mount mounted to the window, the mount supporting a barrel having a lens assembly. By mounting the window directly to the image sensor and the mount directly to the window, the substrate surface area of the optical module is minimized.

Abstract: A method manufactures semiconductor chips each comprising a component implanted in the semiconductor. The method includes collectively implanting components onto a front face of a semiconductor wafer and fixing the a plate of a transparent material onto the front face of the wafer. Fixing the plate of transparent material is preceded by a step of depositing, on the front face of the wafer, at least one layer of polymer material forming an optical filter. Application is particularly to the manufacturing of imagers.

Abstract: A solid-state imaging device includes a semiconductor substrate; a first conductive region of the semiconductor substrate; a first conductive region on an upper surface side of the first conductive region of the semiconductor substrate; a second conductive region below the first conductive region on the upper surface side of the first conductive region of the semiconductor substrate. The solid-state imaging device further includes a photoelectric conversion region including the first conductive region located on the upper surface side of the first conductive region of the semiconductor substrate and the second conductive region and a transfer transistor transferring charges accumulated in the photoelectric conversion region to a readout region; and a pixel including the photoelectric conversion region and the transfer transistor. The first conductive region, which is included in the photoelectric conversion region, extends to the lower side of a sidewall of a gate electrode of the transfer transistor.

Abstract: MEMS devices (such as interferometric modulators) may be fabricated using a sacrificial layer that contains a heat vaporizable polymer to form a gap between a moveable layer and a substrate. One embodiment provides a method of making a MEMS device that includes depositing a polymer layer over a substrate, forming an electrically conductive layer over the polymer layer, and vaporizing at least a portion of the polymer layer to form a cavity between the substrate and the electrically conductive layer.