Non-electrical Input Responsive (e.g., Light Responsive Imager, Input Programmed By Size Of Storage Sites For Use As A Read-only Memory, Etc.) Patents (Class 257/225)
  • Patent number: 11107961
    Abstract: The ultraviolet light-emitting device includes a base, a nitride semiconductor ultraviolet light-emitting element flip-chip mounted on the base, and a lens for sealing a nitride semiconductor ultraviolet light-emitting element to focus or diffuse light emitted from the nitride semiconductor ultraviolet light-emitting device. The lens is composed of an amorphous fluororesin in which a structural unit of a polymer or copolymer has a fluorine-containing aliphatic cyclic structure and a terminal functional group is a perfluoroalkyl group, and a density of the amorphous fluororesin is higher than 2.11 g/cm3.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: August 31, 2021
    Assignees: SOKO KAGAKU CO., LTD., AGC INC.
    Inventors: Akira Hirano, Yosuke Nagasawa, Masamichi Ippommatsu, Ko Aosaki, Yuki Suehara, Yoshihiko Sakane
  • Patent number: 11089270
    Abstract: A solid-state imaging device includes pixels arranged in matrix form, each including a photoelectric converter and first transfer electrodes, and control lines connected to mutually-corresponding ones of the first transfer electrodes in pixels arranged in a specific row. The pixels include first pixels that receive visible light and second pixels that receive infrared light. Each of floating diffusion layer-including pixels, which are some of the plurality of pixels, further includes a floating diffusion layer and a readout circuit. Each floating diffusion layer-lacking pixel shares the floating diffusion layer with one of the first pixels arranged in a column direction. At least some of the control lines are further connected to the first transfer electrodes of pixels arranged adjacent in the column direction to respective ones of the pixels arranged in the specific row and that share at least one of the floating diffusion layers.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: August 10, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Junichi Matsuo, Sei Suzuki
  • Patent number: 11081508
    Abstract: The present disclosure relates to a solid state imaging element and an electronic device that make it possible to improve sensitivity to light on a long wavelength side. A solid state imaging element according to a first aspect of the present disclosure has a solid state imaging element in which a large number of pixels are arranged vertically and horizontally, the solid state imaging element includes a periodic concave-convex pattern on a light receiving surface and an opposite surface to the light receiving surface of a light absorbing layer as a light detecting element. The present disclosure can be applied to, for example, a CMOS and the like installed in a sensor that needs a high sensitivity to light belonging to a region on the long wavelength side, such as light in the infrared region.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: August 3, 2021
    Assignee: SONY CORPORATION
    Inventor: Sozo Yokogawa
  • Patent number: 10971544
    Abstract: Methods for forming a magneto-resistive memory device and a capacitor in an interconnect structure are disclosed herein. An exemplary method includes forming a first level interconnect metal layer and a second level interconnect metal layer of an interconnect structure. The method further includes simultaneously forming a first plurality of layers in a first region of the interconnect structure and a second plurality of layers in a second region of the interconnect structure, wherein the first plurality of layers and the second plurality of layers are disposed between the first level interconnect metal layer and the second level interconnect metal layer. The first plurality of layers is configured as a magneto-resistive memory device. The second plurality of layers is configured as the capacitor. The magneto-resistive memory device and the capacitor are each coupled to the first level interconnect metal layer and the second level interconnect metal layer.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Chung-Cheng Chou, Ya-Chen Kao, Tien-Wei Chiang
  • Patent number: 10902786
    Abstract: The display device includes a pixel circuit including a driving transistor, an N-type transistor on a first path coupled from a data line to a gate electrode of the driving transistor, and a P-type transistor on the first path, a first scan driver to supply a first scan signal to the N-type transistor, and a second scan driver to supply a second scan signal to the P-type transistor, wherein a width of a high level section of the first scan signal is wider than that of a low level section of the second scan signal, and the low level section of the second scan signal overlaps with the high level section of the first scan signal.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: January 26, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong Won Park, Seung Kyu Lee, Hyun Woong Kim
  • Patent number: 10848702
    Abstract: A solid-state imaging device according to an embodiment includes: plural pixels, plural readout circuits, a control circuit, and a driving circuit. The plural pixels have light receiving elements. The plural readout circuits are connected to each of the plural pixels, and read out the charges accumulated by the light receiving elements. The control circuit gives a readout instruction to a readout pixel serving as a readout target out of the plural pixels. The driving circuit gives a driving instruction for driving a first constant current source provided in the readout circuit of the readout pixel and a second constant current source provided in a readout circuit of a corresponding pixel associated with the readout pixel out of the plural pixels.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: November 24, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Yutaka Okada
  • Patent number: 10830913
    Abstract: An apparatus suitable for detecting X-ray is disclosed. In one example, the apparatus comprises an X-ray absorption layer comprising a pixel and a second pixel, and a layer of material or vacuum extending across a thickness of the X-ray absorption layer and encircling the pixel, wherein the layer of material is configured to prevent a charge carrier in the pixel from moving through the layer of material. In another example, the apparatus comprises an X-ray absorption layer comprising a plurality of columns of a semiconductor configured to absorb X-ray, and a layer of material or vacuum extending across a thickness of the X-ray absorption layer and encircling each of the columns, wherein the layer of material is configured to prevent transfer of a charge carrier between two of the columns.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: November 10, 2020
    Assignee: SHENZHEN XPECTVISION TECHNOLOGY CO., LTD.
    Inventors: Peiyan Cao, Yurun Liu
  • Patent number: 10818708
    Abstract: A photoelectric conversion unit includes first, second, and third semiconductor regions having first, second, and first conductivity types, respectively. A fourth semiconductor region between the first and third semiconductor regions at the same depth as the second semiconductor region. A charge holding portion includes a fifth semiconductor region of the first conductivity type. A transfer transistor has a region between the first and fifth semiconductor regions as a channel portion. A pixel isolation portion includes a sixth semiconductor region of the second conductivity type between the third semiconductor regions of adjacent pixels. A relationship V6>V5>V4 is satisfied, where a potential of the fourth semiconductor region to charges is V4, a potential of a region having the highest potential to charges in the channel portion with the transfer transistor being in an off-state is V5, and a potential of the sixth semiconductor region to charges is V6.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: October 27, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Ginjiro Toyoguchi
  • Patent number: 10764527
    Abstract: A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 1, 2020
    Assignee: KLA-Tencor Corporation
    Inventors: Yung-Ho Alex Chuang, Jingjing Zhang, Sharon Zamek, John Fielden, Devis Contarato, David L. Brown
  • Patent number: 10741592
    Abstract: Image sensors may include an array of pixels each having nested sub-pixels. Nested sub-pixels may include an inner photosensitive region and an outer photosensitive region. Inner photosensitive regions of pixels in an array may be provided with a respective local vertical transfer gate structure formed in a trench that laterally surrounds the inner photosensitive region. A trench structure may be formed in a grid-like pattern having gaps in which the nested sub-pixels are formed. The trench structure may be coupled to outer photosensitive regions of each of the pixels in the array. The trench structure may be a global vertical transfer gate structure. The vertical transfer gate structures provided to the pixels may allow for accumulated charges to be transferred to respective charge storage nodes associated with the photosensitive regions in any given pixel. Image sensors formed in this way may be used in rolling shutter or global shutter configurations.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: August 11, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Manuel H. Innocent
  • Patent number: 10741602
    Abstract: An image sensor including at least one pixel for collecting charge in its photodiode is provided. The image sensor comprises: a substrate having a first surface on a front side and a second surface on a back side, a photodetector formed in the silicon substrate and having a light-receiving surface on the second surface, and a first layer with positive charges disposed on the second surface, the first layer being configured to form an electron accumulation region at the light-receiving surface of the photodetector for suppressing a dark current at a back side interface of the image sensor. A method for fabricating an image sensor including a first layer with positive charges is also provided.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: August 11, 2020
    Assignee: Cista System Corp.
    Inventors: Hirofumi Komori, Jingyi Bai
  • Patent number: 10644060
    Abstract: The present disclosure relates to a semiconductor image sensor with improved quantum efficiency. The semiconductor image sensor can include a semiconductor layer having a first surface and a second surface opposite of the first surface. An interconnect structure is disposed on the first surface of the semiconductor layer, and radiation-sensing regions are formed in the semiconductor layer. The radiation-sensing regions are configured to sense radiation that enters the semiconductor layer from the second surface and groove structures are formed on the second surface of the semiconductor layer.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Hsun-Ying Huang, Shih-Hsun Hsu
  • Patent number: 10600840
    Abstract: An imaging device includes a semiconductor substrate and a pixel. The semiconductor substrate includes first and second surfaces that oppose each other, a first region containing an impurity of a first conductivity type, a second region that contains an impurity of a second conductivity type and that is closer to the first surface than the first region is, a third region that contains an impurity of the first conductivity type and that is closer to the first surface than the second region is, and a fourth region that provides connection between the first and third regions and that contains an impurity of the first conductivity type. The pixel includes a photoelectric converter, and a first diffusion region that is electrically connected to the photoelectric converter, that is located in the third region, that is exposed at the first surface, and that overlaps the entire first diffusion region in plan view.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 24, 2020
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Morikazu Tsuno
  • Patent number: 10593714
    Abstract: An imaging device includes: a pixel that includes a semiconductor substrate including a first diffusion region containing a first impurity of a first conductivity type, and a second diffusion region containing a second impurity of the first conductivity type, a concentration of the first impurity in the first diffusion region being less than a concentration of the second impurity in the second diffusion region, an area of the first diffusion region being less than an area of the second diffusion region in a plan view, a photoelectric converter configured to convert light into charges, and a first transistor including a source and a drain, the first diffusion region functioning as one of the source and the drain, the second diffusion region functioning as the other of the source and the drain, the first diffusion region being configured to store at least a part of the charges.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: March 17, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yoshihiro Sato, Junji Hirase, Yoshinori Takami
  • Patent number: 10566368
    Abstract: A pixel structure of an image sensor is provided and includes following units. A crystalline layer of a first doping type is formed on a substrate. A photodiode region is formed in the crystalline layer. A gate of a source follower transistor is formed on a top surface of the crystalline layer. A reset gate is formed on the top surface of the crystalline layer. A doped region of a second doping type is formed in the crystalline layer and formed between the reset gate and the gate of the source follower. The first doping type is different from the second doping type, and the photodiode region is connected to the doped region under the top surface of the crystalline layer as an anti-blooming path.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: February 18, 2020
    Assignee: Himax Imaging Limited
    Inventors: Yang Wu, Fei-Xia Yu, Yu Hin Desmond Cheung
  • Patent number: 10560652
    Abstract: The present disclosure relates to a solid-state image sensor, driving method, and electronic apparatus, capable of achieving reduction in pixel size and sensitivity improvement. The solid-state image sensor includes a PD configured to convert light into electric charge by photoelectric conversion and to store the electric charge, a first transfer transistor configured to read out the electric charge stored in the photoelectric conversion unit, a multiplication region configured to store temporarily and multiply the electric charge read out through the read-out unit, and a second transfer transistor configured to transfer the electric charge stored in the multiplication region to a conversion unit configured to convert the electric charge into a pixel signal. Then, an intense electric field is generated in the multiplication region to multiply electric charge by the avalanche effect in transferring the electric charge from the multiplication region to an FD portion through the second transfer transistor.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: February 11, 2020
    Assignee: Sony Corporation
    Inventor: Takuya Sano
  • Patent number: 10559611
    Abstract: An image sensor includes a control circuit and pixels. Each pixel includes: a photosensitive area, a substantially rectangular storage area adjacent to the photosensitive area, and a read area. First and second insulated vertical electrodes electrically connected to each other are positioned opposite each other and delimit the storage area. The first electrode extends between the storage area and the photosensitive area. The second electrode includes a bent extension opposite a first end of the first electrode, with the storage area emerging onto the photosensitive area on the side of the first end. The control circuit operates to apply a first voltage to the first and second electrodes to perform a charge transfer, and a second voltage to block charge transfer.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: February 11, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Philippe Are
  • Patent number: 10551411
    Abstract: A test system for testing semiconductor chips including a docking plate, a test card, chip sockets, a stiffener, and test electronics. Each test card has a uniform card configuration that may be used with any of several different handlers. Each test card includes conductive pads electrically coupled to and longitudinally offset from a socket interface along a length of the test card. The stiffener includes a test interface including conductive pins for electrically interfacing the conductive pads of the test card. The test card is supported by the stiffener so that it remains undeformed as each chip is plunged into a test socket. The test interface includes a basin that is covered by the test card to form a thermal isolation cavity for thermal separation from the test electronics. A uniform radio frequency interface is provided between each test card and a corresponding test interface.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: February 4, 2020
    Assignee: Silicon Laboratories Inc.
    Inventors: Scott E. Caudle, Wenshui Zhang, Raymond A. Booher
  • Patent number: 10547016
    Abstract: A photoelectric conversion apparatus according to an embodiment includes a semiconductor substrate, a first electrode layer disposed on the semiconductor substrate, a second electrode layer disposed between the first electrode layer and the semiconductor substrate, an accumulation layer disposed between the first electrode layer and the second electrode layer and configured to accumulate signal electric charges generated by photoelectric conversion, an insulating layer disposed between the accumulation layer and the second electrode layer, a blocking layer disposed between the accumulation layer and the insulating layer and configured to prevent the signal electric charges in the accumulation layer from reaching the insulating layer, and a circuit unit disposed in the semiconductor substrate and connected to the second electrode layer to receive a signal based on the signal electric charges.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: January 28, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Kazuaki Tashiro
  • Patent number: 10522591
    Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes a first metal layer formed on a semiconductor substrate, wherein the first metal layer includes a first metal feature in a first region and a second metal feature in a second region; a second metal layer disposed on the first metal layer, wherein the second metal layer includes a third metal feature in the first region and a fourth metal feature in a second region; a magneto-resistive memory device sandwiched between the first metal feature and the third metal feature; and a capacitor sandwiched between the second metal feature and the fourth metal feature.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Cheng Chou, Ya-Chen Kao, Tien-Wei Chiang
  • Patent number: 10497735
    Abstract: The invention relates to an image sensor and method for reducing image defects. A photoconversion area is formed in a semiconductor layer. An insulating layer formed over the semiconductor layer contains a metal element. A lens over the insulting layer is positioned opposite the photoconversion area to focus light on it. A layer of light-absorbing material is deposited on the side of the metal element facing the lens to prevent reflection of parasitic light rays within the image device.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: December 3, 2019
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Axel Crocherie, Etienne Mortini, Jean Luc Huguenin
  • Patent number: 10488438
    Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: November 26, 2019
    Assignee: Intel Corporation
    Inventors: Pooya Tadayon, Mark Bohr, Joe Walczyk
  • Patent number: 10455178
    Abstract: An optical sensor device, which may be a time-of-flight sensor, comprises a pixel array having a plurality of pixels. Moreover, the optical sensor device comprises a read-out node configured to provide photo-generated charge carriers from a first pixel and a second pixel for read-out and a first transfer gate configured to enable a read-out of the first pixel using the read-out node and a second transfer gate to disable a read-out of the second pixel during read-out of the first pixel.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: October 22, 2019
    Assignee: Infineon Technologies AG
    Inventor: Henning Feick
  • Patent number: 10446600
    Abstract: An imaging system serving as an image generation device is provided with: a random color filter array that has a plurality of concave lenses and a plurality of color filters having different transmission characteristics; a photodiode that receives light that has passed through the random color filter array; an AD converter that converts the light received by the photodiode into digital data; and a color image generation circuit that generates an image using the digital data and modulation information of the random color filter array, in which the plurality of concave lenses are located between the plurality of color filters and the photodiode, or the plurality of color filters are located between the plurality of concave lenses and the photodiode.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: October 15, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Satoshi Sato, Hisashi Watanabe, Takeo Azuma, Kunio Nobori, Nobuhiko Wakai, Takamasa Ando
  • Patent number: 10396223
    Abstract: A method for making a CMOS image sensor may include forming a superlattice on a semiconductor substrate having a first conductivity type, with the superlattice including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a plurality of laterally adjacent photodiodes on the superlattice. Each photodiode may include a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate, a retrograde well extending downward into the semiconductor layer and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: August 27, 2019
    Assignee: ATOMERA INCORPORATED
    Inventors: Yi-Ann Chen, Abid Husain, Hideki Takeuchi
  • Patent number: 10361232
    Abstract: Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and a passivation region positioned between the textured region and the at least one junction. The passivation region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: July 23, 2019
    Assignee: SiOnyx, LLC
    Inventors: Homayoon Haddad, Jeffrey McKee, Jutao Jiang, Chintamani Palsule, Leonard Forbes
  • Patent number: 10347684
    Abstract: An image sensor includes a substrate including a photoelectric conversion part therein, and a fixed charge layer provided above the substrate. The fixed charge layer includes a first metal oxide and a second metal oxide, which are different from each other. The first metal oxide includes a first metal, and the second metal oxide includes a second metal different from the first metal. Concentration of the first metal in the fixed charge layer progressively increases from an upper portion of the fixed charge layer to a lower portion of the fixed charge layer.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: July 9, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Honglae Park, Jaeho Kim, Hyoshin Ahn, Inkook Jang
  • Patent number: 10326920
    Abstract: The present disclosure relates to a solid-state imaging device, a method for manufacturing the same, and an electronic apparatus capable of improving sensitivity while suppressing degradation of color mixture. The solid-state imaging device includes an anti-reflection portion having a moth-eye structure provided on a boundary surface on a light-receiving surface side of a photoelectric conversion region of each pixel arranged two-dimensionally, and an inter-pixel light-blocking portion provided below the boundary surface of the anti-reflection portion to block incident light. In addition, the photoelectric conversion region is a semiconductor region, and the inter-pixel light-blocking portion has a trench structure obtained by digging the semiconductor region in a depth direction at a pixel boundary. The techniques according to the present disclosure can be applied to, for example, a solid-state imaging device of a rear surface irradiation type.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: June 18, 2019
    Assignee: Sony Corporation
    Inventors: Yoshiaki Masuda, Yuki Miyanami, Hideshi Abe, Tomoyuki Hirano, Masanari Yamaguchi, Yoshiki Ebiko, Kazufumi Watanabe, Tomoharu Ogita
  • Patent number: 10304881
    Abstract: A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a superlattice on the semiconductor substrate including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The image sensor may further include a plurality of laterally adjacent photodiodes on the superlattice. Each photodiode may include a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate, a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: May 28, 2019
    Assignee: ATOMERA INCORPORATED
    Inventors: Yi-Ann Chen, Abid Husain, Hideki Takeuchi
  • Patent number: 10192911
    Abstract: Imaging apparatus includes a photosensitive medium and a bias electrode, which is at least partially transparent, overlying the photosensitive medium. An array of pixel circuits is formed on a semiconductor substrate. Each pixel circuit includes a pixel electrode coupled to collect the charge carriers from the photosensitive medium; a readout circuit configured to output a signal indicative of a quantity of the charge carriers collected by the pixel electrode; a skimming gate coupled between the pixel electrode and the readout circuit; and a shutter gate coupled in parallel with the skimming gate between a node in the pixel circuit and a sink site. The shutter gate and the skimming gate are opened sequentially in each of a sequence of image frames so as to apply a global shutter to the array and then to read out the collected charge carriers via the skimming gate to the readout circuit.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: January 29, 2019
    Assignee: APPLE INC.
    Inventors: Gennadiy A. Agranov, QingFei Chen, Oray O. Cellek, Xiangli Li
  • Patent number: 10141360
    Abstract: An imaging system includes a pixel array of pixel cells with each one of the pixel cells including a photodiode disposed in a semiconductor material, a global shutter gate transistor, disposed in the semiconductor material and coupled to the photodiode, a storage transistor disposed in the semiconductor material, an optical isolation structure disposed in the semiconductor material to isolate a sidewall of the storage transistor from stray light and stray charge. The optical isolation structure also includes a deep trench isolation structure that is filled with tungsten and a P+ passivation formed over an interior sidewall of the deep trench optical isolation structure. Each one of the pixel cells also include control circuitry coupled to the pixel array to control operation of the pixel array and readout circuitry coupled to the pixel array to readout image data from the plurality of pixels.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 27, 2018
    Assignee: OmniVision Technologies, Inc.
    Inventors: Kevin Ka Kei Leung, Dajiang Yang
  • Patent number: 9966405
    Abstract: A device having a sensor die with a sensor and a control circuit die with at least one control circuit disposed therein, the control circuit die on the sensor die. A plurality of mounting pads is disposed on a second side of the sensor die. A first electrical connection connects a first one of the plurality of mounting pads to a first control circuit of the at least one sensor control circuit and a second electrical connection connects the first control circuit to the sensor. A third electrical connection connects the sensor to a second control circuit of the at least one control circuit and a fourth electrical connection connects the second control circuit to second one of the plurality of mounting pads.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: May 8, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Tzu-Hsuan Hsu, Dun-Nian Yaung
  • Patent number: 9933300
    Abstract: A pixel comprises a high-response photodiode that collects photocharge, a first transfer gate that enables the charge to be transferred off the high-response photodiode, completely emptying it onto a low-response photodiode, a second transfer gate enables the charge to be transferred off the low-response photodiode, completely emptying it onto floating diffusion, a third transfer gate for anti-blooming; the floating diffusion collects the transferred charge creating a change of voltage, a means of resetting the floating diffusion. A source-follower is modulated by the voltage on floating diffusion to control bit-line voltage and column-amplifier output. In examples, photocharge is integrated onto both the high-response photodiode and onto the low-response photodiode.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: April 3, 2018
    Assignee: BAE Systems Imaging Solutions Inc.
    Inventors: Hung T Do, Alberto M Magnani, R Daniel McGrath
  • Patent number: 9911775
    Abstract: An image sensor includes a substrate including a pixel array region and a logic region where a surface of the pixel array region is higher than a surface of the logic region, and a light shielding pattern formed over the substrate of the logic region and having a surface on substantially the same plane as a surface of the substrate.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: March 6, 2018
    Assignee: SK Hynix Inc.
    Inventors: Do-Hwan Kim, Jong-Chae Kim, Kyoung-Oug Ro, Il-Ho Song
  • Patent number: 9865632
    Abstract: A global shutter image sensor formed on an n-type bulk substrate and including pixels having pinned n-type photodiodes and memory nodes formed in designated n-doped epitaxial layer regions that are separated from the bulk substrate by a p-type vertical (potential) barrier implant. Each memory node includes both a buried channel portion and a contiguous pinned diode portion having different doping levels such that an intrinsic lateral electrical field drives electrons from the buried channel portion into the pinned diode portion during global charge transfer from an adjacent photodiode. The p-type vertical (potential) barrier implant is coupled to ground, and the bulk substrate is switched between a low integration voltage level during integration periods, and a high reset voltage level, whereby the photodiodes are globally reset without requiring reset transistors. P-type sinker implant sections and p-type vertical barrier implants form box-like diffusions around each pixel's photodiode and memory node.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: January 9, 2018
    Assignee: Tower Semiconductor Ltd.
    Inventors: Assaf Lahav, Amos Fenigstein, Yakov Roizin, Avi Strum
  • Patent number: 9837465
    Abstract: An image sensor includes a plurality of photoelectric detectors, a plurality of color filters, and at least one pixel isolation region between adjacent ones of the photoelectric detectors. The color filters include a white color filter, and the color filters correspond to respective ones of the photoelectric detectors. The at least one pixel isolation region serves to physically and at least partially optically separate the photoelectric detectors from one another.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: December 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Chak Ahn, Bum-Suk Kim
  • Patent number: 9807329
    Abstract: An embodiment provides an imaging device including a pixel that includes a first photoelectric conversion portion, a second photoelectric conversion portion, a first transfer transistor, a second transfer transistor, and a floating diffusion portion. The first transfer transistor transfers a signal charge in the first photoelectric conversion portion to the floating diffusion portion. The second transfer transistor transfers a signal charge in the second photoelectric conversion portion to the floating diffusion portion. A potential at the first photoelectric conversion portion for the signal charge is higher than a potential at the second photoelectric conversion portion for the signal charge.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: October 31, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yoichiro Handa, Hajime Ikeda
  • Patent number: 9799778
    Abstract: A chip package includes a chip, an insulating layer, a flowing insulating material layer and conductive layer. The chip has a conductive pad, a side surface, a first surface and a second surface opposite to the first surface, which the side surface is between the first surface and the second surface, and the conductive is below the first surface and protruded from the side surface. The insulating layer covers the second surface and the side surface, and the flowing insulating material layer is disposed below the insulating layer, and the flowing insulating material layer has a trench exposing the conductive pad protruded form the side surface. The conductive layer is disposed below the flowing insulating material layer and extended into the trench to contact the conductive pad.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: October 24, 2017
    Assignee: XINTEC INC.
    Inventors: Yi-Ying Kuo, Ming-Chieh Huang, Hsi-Chien Lin
  • Patent number: 9791303
    Abstract: A package for a device to be inserted into a solid structure may include a building material that includes particles of one of micrometric and sub-micrometric dimensions. The device may include an integrated detection module having at least one integrated sensor and the package arranged to coat at least one portion of the device including the integrated detection module. A method aspect includes a method of manufacturing the device. A system aspect is for monitoring parameters in a solid structure that includes the device.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: October 17, 2017
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Alberto Pagani, Bruno Murari, Federico Giovanni Ziglioli, Marco Ronchi, Giulio Ricotti
  • Patent number: 9787931
    Abstract: A solid-state imaging device includes a first and second pixel regions. In the first pixel region, a photoelectric conversion unit, a floating diffusion region (FD), and a transferring transistor are provided. In the second pixel region, an amplifying transistor, and a resetting transistor are provided. A first element isolation portion is provided in the first pixel region, while a second element isolation portion is provided in the second pixel region. An amount of protrusion of an insulating film into a semiconductor substrate in the first element isolation portion is smaller, than that in the second element isolation portion.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: October 10, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Mineo Shimotsusa, Fumihiro Inui
  • Patent number: 9774770
    Abstract: An optical apparatus includes plural optical lens groups, an optical sensor, at least one lighting member and a casing. After a light beam passes through any of the plural optical lens groups, a travelling direction of the light beam is changed. After the light beam passes through at least one of the plural optical lens groups, the light beam is sensed and converted into an image signal by the optical sensor. The lighting member outputs a source beam. The plural optical lens groups, the optical sensor and the lighting member are accommodated within the casing. The optical apparatus has a single optical lens module, and is able to implement different optical functions simultaneously. Consequently, the overall volume of the optical apparatus is minimized, the fabricating cost of the optical apparatus is reduced, the assembling process is simplified, and the number of components to be assembled is reduced.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: September 26, 2017
    Assignee: Everready Precision Ind. Corp.
    Inventors: Jyh-Long Chern, Chih-Ming Yen
  • Patent number: 9726841
    Abstract: An integrated photo detector with enhanced electrostatic discharge damage (ESD) protection. The integrated photo detector includes a first photodiode formed in the SOI substrate and associated with a first p-electrode and a first n-electrode. Additionally, the integrated photo detector includes a second photodiode formed in the SOI substrate associated with a second p-electrode and a second n-electrode forming a capacitance no larger than a few femto Faradays. Moreover, the integrated photo detector includes a first electrode and a second electrode disposed respectively on the SOI substrate. The first/second electrode is respectively connected to the first p/n-electrode via a first/second metallic layer patterned with a reduced width from the first/second electrode to the first p/n-electrode and connected to the second p/n-electrode via a first/second metallic wire to make a parallel coupling between the first photodiode and the second photodiode with an ESD threshold of about 100V.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: August 8, 2017
    Assignee: INPHI CORPORATION
    Inventors: Jie Lin, Masaki Kato
  • Patent number: 9721987
    Abstract: The semiconductor device includes a semiconductor substrate, an isolation feature, a photodiode and a transistor gate. The isolation feature is disposed in the semiconductor substrate. The photodiode is disposed in the semiconductor substrate and adjacent to the isolation feature. The photodiode includes a first pinned photodiode (PPD) with a first dopant type and a second PPD with a second dopant type. The second PPD is embedded in the first PPD, and is different from the first dopant type. The transistor gate is disposed over the photodiode and includes a first portion and a second portion. The first portion with the first dopant type is used for controlling the operation of the semiconductor device. The second portion with the second dopant type is adjacent to the first portion. The second portion covers the photodiode and extends toward the isolation feature.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: August 1, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yueh-Chuan Lee
  • Patent number: 9712766
    Abstract: A signal processing device includes a control unit that suspends supplying of a signal to an A/D conversion unit which performs A/D conversion, during an A/D conversion period in which the A/D conversion is performed on the signal that depends on an electric charge read from a pixel; and a maintenance unit that maintains a signal value of the signal in a state where the signal is supplied by the control unit to the A/D conversion unit and that supplies the maintained signal value to the A/D conversion unit in a state where the supplying of the signal to the A/D conversion unit is suspended by the control unit.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: July 18, 2017
    Assignee: Sony Corporation
    Inventors: Satoshi Ogata, Rei Yoshikawa, Hiroaki Ebihara
  • Patent number: 9679934
    Abstract: A semiconductor device including a substrate, at least one sensor, a dielectric layer, at least one light pipe structure, at least one pad, a shielding layer, and a protection layer is provided. The sensor is located in the substrate of a first region. The dielectric layer is located on the substrate. The light pipe structure is located in the dielectric layer of the first region. The light pipe structure corresponds to the sensor. The pad is located in the dielectric layer of a second region. The shielding layer is located on the dielectric layer, wherein the light pipe structure is surrounded by the shielding layer. The protection layer is located on the shielding layer. At least one pad opening is disposed in the dielectric layer, the shielding layer, and the protection layer above the pad. The pad opening exposes a top surface of the corresponding pad.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: June 13, 2017
    Assignee: Powerchip Technology Corporation
    Inventors: Tse-Wei Chung, Tsung-Hui Chou, Hsu-Ting Chang
  • Patent number: 9659632
    Abstract: Static random access memories (SRAM) are provided. The SRAM includes a plurality of bit cells. Each bit cell includes a first inverter, a second inverter cross-coupled with the first inverter, a first pass gate transistor coupled between the first inverter and a bit line, and a second pass gate transistor coupled between the second inverter and a complementary bit line. The bit cells are divided into a plurality of top tier cells and a plurality of bottom tier cells, and each of the bottom tier cells is disposed under the individual top tier cell. The first inverter of the top tier cell is disposed on the second inverter of the corresponding bottom tier cell within a substrate, and the second inverter of the top tier cell is disposed on the first inverter of the corresponding bottom tier cell within the substrate.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ta-Pen Guo, Carlos H. Diaz, Chih-Hao Wang, Jean-Pierre Colinge
  • Patent number: 9654713
    Abstract: An image sensor includes at least one pixel with a transfer gate that is controllable among at least three biasing conditions, including a first biasing condition in which electrons are transferable from a photodiode to a potential well under the transfer gate, a second biasing condition in which the electrons are confined in the potential well under the transfer gate, and a third biasing condition in which the electrons are transferable out of the potential well under the transfer gate. The pixel includes a p+ type doped barrier implant located at least partially under a portion of the transfer gate, and a pinned charge transfer barrier located on the opposite side of the transfer gate from the photodiode that includes a p+ type doped region and an n-type doped region. The image sensor can operate in a global shutter mode and/or a rolling shutter mode.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: May 16, 2017
    Inventor: Alexander Krymski
  • Patent number: 9651839
    Abstract: The present invention provides an array substrate and a manufacturing method thereof, a display panel and a display device. The manufacturing method of an array substrate in the present invention comprises: forming light-shielding layers on the base substrate through a patterning process by using a light-shielding layer-doping multiplexing mask plate; and performing doping of CMOS transistors by using the light-shielding layer-doping multiplexing mask plate. In the invention, two mask plates used in manufacturing the light-shielding layer and the doping process in the prior art are replaced with one light-shielding layer-doping multiplexing mask plate, therefore the number of the mask plates during manufacturing is reduced and the cost is decreased. Meanwhile, providing of the light-shielding layer below the N type transistors in the driving region of the array substrate may prevent light-induced leakage current from being generated in the conductive region.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: May 16, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Like Hu, Xiaojing Qi
  • Patent number: 9614083
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • Patent number: 9613995
    Abstract: A semiconductor device including a substrate, at least one sensor, a dielectric layer, at least one light pipe structure, at least one pad, a shielding layer, and a protection layer is provided. The sensor is located in the substrate of a first region. The dielectric layer is located on the substrate. The light pipe structure is located in the dielectric layer of the first region. The light pipe structure corresponds to the sensor. The pad is located in the dielectric layer of a second region. The shielding layer is located on the dielectric layer, wherein the light pipe structure is surrounded by the shielding layer. The protection layer is located on the shielding layer. At least one pad opening is disposed in the dielectric layer, the shielding layer, and the protection layer above the pad. The pad opening exposes a top surface of the corresponding pad.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 4, 2017
    Assignee: Powerchip Technology Corporation
    Inventors: Tse-Wei Chung, Tsung-Hui Chou, Hsu-Ting Chang