Signal Charge Detection Type (e.g., Floating Diffusion Or Floating Gate Non-destructive Output) Patents (Class 257/239)
  • Patent number: 11075081
    Abstract: A method for fabricating a semiconductor device with multiple threshold voltages includes masking a substrate structure to selectively form work-function metal layers on vertical field effect transistors. In the method, a first work function metal layer is formed on a high-k dielectric layer of a substrate structure comprising vertical field effect transistors. The first work function metal layer and the high-k dielectric layer are etched to form gate regions for each vertical field effect transistor. A resist mask is formed over a first of the vertical field effect transistors. The resist mask isolates the first of the vertical field effect transistors from a second of the vertical field effect transistors. A second work function metal layer is selectively formed on the first work function metal layer of the gate region of the second of the vertical field effect transistors. The resist mask is then removed.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: July 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Praveen Joseph, Indira Seshadri, Ekmini Anuja De Silva
  • Patent number: 10867676
    Abstract: Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: December 15, 2020
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10804851
    Abstract: Described herein are systems and methods that reduce settling time in amplifier circuits, such as voltage sense amplifiers (VSA) or current sense amplifiers (CSA) circuits, that comprise a feedback path. When the feedback path is interrupted via a switch, a CSA circuit switches to open loop. A sample-and-hold circuit holds the output voltage of the amplifier, such that when a load is connected to the CSA circuit, the open loop settling time, which is shorter than the closed loop settling time, is allowed to pass before the CSA output voltage is measured, thereby, advantageously preventing any potential disturbance present at the CSA output from being fed back to the CSA input.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: October 13, 2020
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Daniel J. Black, Antoine D. Fifield, Brian A. Miller
  • Patent number: 10693063
    Abstract: A semiconductor device includes memory cells, a first dielectric liner material overlying side surfaces of the memory cells, a high-k dielectric material overlying side surfaces of the first dielectric liner material, a second dielectric liner material overlying side surfaces of the high-k dielectric material, and an additional dielectric material overlying side surfaces of the second dielectric liner material. A memory structure, an electronic system, and a method of forming a memory structure are also described.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Andrew J. Hansen, James A. Cultra
  • Patent number: 10658460
    Abstract: A tunnel field effect transistor (100) comprises a source region (102), a drain region (104), and a channel region (106) formed of a single material, in particular a half-metal. The channel extends between the source region and the drain region. The channel region (106) and the drain region (104) are smaller than a threshold size in a first dimension. The threshold size is the size required for the material to exhibit sufficient quantum confinement such that a non-zero band gap results and the material becomes a semiconductor. The source region (102) is larger than this threshold size in the first dimension and is thus metallic.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: May 19, 2020
    Assignee: University College Cork
    Inventors: Lida Ansari, Giorgos Fagas, James Greer
  • Patent number: 10580492
    Abstract: A memory array with memory cells arranged in rows and columns. Each memory cell includes source and drain regions with a channel region there between, a floating gate disposed over a first channel region portion, and a second gate disposed over a second channel region portion. A plurality of bit lines each extends along one of the columns and is electrically connected to the drain regions of a first group of one or more of the memory cells in the column and is electrically isolated from the drain regions of a second group of one or more of the memory cells in the column. A plurality of source lines each is electrically connected to the source regions of the memory cells in one of the columns or rows. A plurality of gate lines each is electrically connected to the second gates of memory cells in one of the columns or rows.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: March 3, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Vipin Tiwari, Nhan Do
  • Patent number: 10504895
    Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor fin, a second semiconductor fin, an air gap and a dielectric cap layer. The first semiconductor fin is disposed on the semiconductor substrate, and the second semiconductor fin is disposed on the semiconductor substrate. The air gap is located between the first semiconductor fin and the second semiconductor fin, and the dielectric cap layer caps a top of the air gap.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10419010
    Abstract: Pipelined analog-to-digital converters (ADCs) include a flash ADC that reduces noise tones in power supply current drawn by the flash ADC. A pipelined analog-to-digital converter (ADC) includes a flash ADC and error correction circuitry coupled to the flash ADC. The flash ADC includes a plurality of latched comparators and a plurality of driver circuits. Each of the latched comparators includes an inverting output and a non-inverting output. Each of the driver circuits is coupled to one of the latched comparators, and includes an input terminal and an output terminal. In a first subset of the driver circuits the input terminal is coupled to the inverting output of one of the latched comparators. In a second subset of the driver circuits the input terminal is coupled to the non-inverting output of one of the latched comparators.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: September 17, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rajendrakumar Joish, Himanshu Varshney
  • Patent number: 10411027
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a fin extending from the substrate. The fin includes a first and second fin sidewall, and a memory cell layer is adjacent to the first and second fin sidewalls. A first control gate is adjacent to the memory cell layer where the memory cell layer is between the first fin sidewall and the first control gate. A second control gate is also adjacent to the memory cell layer, where the memory cell layer is between the second fin sidewall and the second control gate. The first and second control gates are electrically isolated from each other.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: September 10, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Ming Zhu, Pinghui Li, Eng Huat Toh, Yiang Aun Nga, Danny Pak-Chum Shum
  • Patent number: 10396108
    Abstract: The present technology relates to a solid-state imaging element, a solid-state imaging element manufacturing method, and an electronic apparatus that make it possible to suppress both junction leakage and diffusion leakage of an FD in an FD storage sensor. The present technology includes a photodiode, a photoelectric conversion film, a diffusion layer, and an impurity layer. The photodiode and the photoelectric conversion film perform photoelectric conversion of incident light. The diffusion layer has a second polarity, which is different from a first polarity possessed by the photodiode, and stores an electric charge derived from photoelectric conversion by the photoelectric conversion film. The impurity layer includes impurities having the first polarity. The photodiode and the diffusion layer are disposed on an identical substrate in parallel with each other. The impurity layer is disposed below the diffusion layer. The present technology is applicable to solid-state imaging elements.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: August 27, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Kyosuke Ito
  • Patent number: 10393577
    Abstract: Color light sensors are used to sense colored light and a full spectrum light in order to generate at least three color channel signals and a clear channel signal. An infrared component IR is calculated by summing up the color channel signals with individual weighting factors and subtracting a weighted clear channel signal.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: August 27, 2019
    Assignee: ams AG
    Inventors: Kerry Glover, David Mehrl, Dan Jacobs
  • Patent number: 10356440
    Abstract: As the quality and quantity of shared video content increases, video encoding standards and techniques are being developed and improved to reduce bandwidth consumption over telecommunication and other networks. One such technique for compressing videos involves transforming image data into an alternate, encoding-friendly domain (e.g., by a two-dimensional discrete cosine transform). Transform modules may be implemented to perform these transformations, which may occur during both video encoding and decoding processes. Provided are exemplary techniques for improving the efficiency and performance of transform module implementations.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: July 16, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Ashish Mishra, Vikash Kumar
  • Patent number: 10237504
    Abstract: A solid-state imaging device and a camera system are disclosed. The solid-state imaging device includes a pixel unit and a pixel signal readout circuit. The pixel signal readout circuit includes a plurality of comparators disposed to correspond to a pixel column array, and a plurality of counters. Each counter includes a first amplifier, a second amplifier, and a mirror circuit to from a current mirror in parallel with the second amplifier. The first amplifier includes differential transistors, initializing switches connected between gates and collectors of the differential transistors, and first and second capacitors connected to each of the gates of the differential transistors. The second amplifier includes an initializing switch and a third capacitor. The mirror circuit includes a gate input transistor whose gate is inputted with a voltage sampled by the first amplifier or a voltage sampled by the second amplifier.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: March 19, 2019
    Assignee: Sony Corporation
    Inventor: Kenichi Tanaka
  • Patent number: 10199421
    Abstract: An image sensor includes a substrate including unit pixels. Each of the unit pixels includes photoelectric conversion elements and storage diodes.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuk Soon Choi, Jung Bin Yun, Jungchak Ahn
  • Patent number: 10115755
    Abstract: In a solid-state image pickup device including a pixel that includes a photoelectric conversion portion, a carrier holding portion, and a plurality of transistors, the solid-state image pickup device further includes a first insulating film disposed over the photoelectric conversion portion, the carrier holding portion, and the plurality of transistors, a conductor disposed in an opening of the first insulating film and positioned to be connected to a source or a drain of one or more of the plurality of transistors, and a light shielding film disposed in an opening or a recess of the first insulating film and positioned above the carrier holding portion.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: October 30, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Aiko Kato, Kouhei Hashimoto, Seiichi Tamura
  • Patent number: 10096737
    Abstract: Silicon-based or other electronic circuitry is dissolved or otherwise disabled by reactive materials within a semiconductor chip should the chip or a device containing the chip be subjected to tampering. Triggering circuits containing normally-OFF heterojunction field-effect photo-transistors are configured to cause reactions of the reactive materials within the chips upon exposure to light. The normally-OFF heterojunction field-effect photo-transistors can be fabricated during back-end-of-line processing through the use of polysilicon channel material, amorphous hydrogenated silicon gate contacts, hydrogenated crystalline silicon source/drain contacts, or other materials that allow processing at low temperatures.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: October 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Joel P. de Souza, Bahman Hekmatshoartabari, Daniel M. Kuchta, Devendra K. Sadana
  • Patent number: 10032730
    Abstract: Silicon-based or other electronic circuitry is dissolved or otherwise disabled by reactive materials within a semiconductor chip should the chip or a device containing the chip be subjected to tampering. Triggering circuits containing normally-OFF heterojunction field-effect photo-transistors are configured to cause reactions of the reactive materials within the chips upon exposure to light. The normally-OFF heterojunction field-effect photo-transistors can be fabricated during back-end-of-line processing through the use of polysilicon channel material, amorphous hydrogenated silicon gate contacts, hydrogenated crystalline silicon source/drain contacts, or other materials that allow processing at low temperatures.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: July 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Joel P. de Souza, Bahman Hekmatshoartabari, Daniel M. Kuchta, Devendra K. Sadana
  • Patent number: 9976981
    Abstract: Provided is a charge-transfer-type sensor suitable for high integration while eliminating a potential barrier. A sensor provided with a semiconductor substrate 10 partitioned into a sensing region 5 in which a potential varies in corresponding fashion to a variation in the external environment, a charge input region 2 for supplying charges to the sensing region 5, an input charge control region 3 interposed between the sensing region 5 and the charge input region 2, and a charge accumulation region 7 for accumulating electric charges transported from the sensing region 5, the sensor for detecting the amount of electric charges accumulated in the charge accumulation region 7, wherein a diffusion layer 4 is formed between the input charge control region 3 and the sensing region 5 of the substrate 10, and dopants for producing charges having the same polarity as the charges supplied from the charge input region 2 are diffused in the diffusion layer 4.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: May 22, 2018
    Assignee: National University Corporation Toyohashi University of Technology
    Inventors: Fumihiro Dasai, Kazuaki Sawada
  • Patent number: 9923012
    Abstract: An image pickup apparatus includes a pixel array including a plurality of pixels arranged in a two-dimensional pattern, each of which includes a conversion unit, an amplification unit, a first holding unit configured to hold a first signal obtained by the amplification unit amplifying an electric charge converted by the conversion unit having a first sensitivity, a second holding unit configured to hold a second signal obtained by the amplification unit amplifying the electric charge converted by the conversion unit having a second sensitivity different from the first sensitivity, and a third holding unit configured to hold an offset signal of the amplification unit, and a correction unit configured to correct the first signal using a second output signal output from the second holding unit or a first output signal output from the first holding unit, and a third output signal output from the third holding unit.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: March 20, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kanako Sato, Kazumasa Matsumoto, Katsuro Takenaka
  • Patent number: 9758824
    Abstract: A system and method employing at least one semiconductor device, or an arrangement of insulating and metal layers, having at least one detecting region which can include, for example, a recess or opening therein, for detecting a charge representative of a component of a polymer, such as a nucleic acid strand proximate to the detecting region, and a method for manufacturing such a semiconductor device. The system and method can thus be used for sequencing individual nucleotides or bases of ribonucleic acid (RNA) or deoxyribonucleic acid (DNA). The semiconductor device includes at least two doped regions, such as two n-typed regions implanted in a p-typed semiconductor layer or two p-typed regions implanted in an n-typed semiconductor layer. The detecting region permits a current to pass between the two doped regions in response to the presence of the component of the polymer, such as a base of a DNA or RNA strand.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: September 12, 2017
    Assignee: LIFE TECHNOLOGIES CORPORATION
    Inventors: Jon R. Sauer, Bart J. Van Zeghbroeck
  • Patent number: 9704913
    Abstract: Embodiments related to the manufacturing of an imager device and an imager device are disclosed. Embodiments associated with methods of an imager device are also disclosed.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: July 11, 2017
    Assignee: Infineon Technologies AG
    Inventors: Dirk Offenberg, Henning Feick, Stefano Parascandola
  • Patent number: 9653499
    Abstract: A solid-state imaging device including an imaging area where a plurality of unit pixels are disposed to capture a color image, wherein each of the unit pixels includes: a plurality of photoelectric conversion portions; a plurality of transfer gates, each of which is disposed in each of the photoelectric conversion portions to transfer signal charges from the photoelectric conversion portion; and a floating diffusion to which the signal charges are transferred from the plurality of the photoelectric conversion portions by the plurality of the transfer gates, wherein the plurality of the photoelectric conversion portions receive light of the same color to generate the signal charges, and wherein the signal charges transferred from the plurality of the photoelectric conversion portions to the floating diffusion are added to be output as an electrical signal.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: May 16, 2017
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Hiroaki Ishiwata
  • Patent number: 9648266
    Abstract: There are provided a driving method for an image pickup device, a driving method for an imaging system, an image pickup device, and an imaging system, which changes an operation for mixing signals generated by a plurality of pixels in accordance with an amplification factor of a signal processing circuit in the image pickup device or an amplification unit externally provided to the image pickup device.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: May 9, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Takahiro Yamasaki, Keisuke Ota, Hiroki Hiyama, Yasuhiro Oguro, Nobuhiro Takeda, Satoshi Suzuki
  • Patent number: 9577036
    Abstract: A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin isolation structure at a common boundary that is shared by the two cells. The fin isolation structure has an air gap extending from a top of the semiconductor fin to a stop layer on the semiconductor substrate. The air gap divides the semiconductor fin into two portions of the semiconductor fin. The fin isolation structure includes a dielectric cap layer capping a top of the air gap.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: February 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 9552004
    Abstract: A voltage regulator includes an error amplifier, a voltage buffer, a transistor, a frequency compensation circuit, a capacitor, and a resistive network. The error amplifier receives a reference signal and a feedback signal, and generates an intermediate control signal. The voltage buffer receives the intermediate control signal and generates a control signal. The transistor has a gate that receives the control signal, a first terminal that receives a supply voltage signal, and a second terminal that generates a regulated output signal. The frequency compensation circuit is connected to the second terminal of the transistor. The capacitor is connected to the error amplifier and the frequency compensation circuit. The resistive network receives the regulated output signal and generates the feedback signal.
    Type: Grant
    Filed: July 26, 2015
    Date of Patent: January 24, 2017
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Ravi Dixit, Parul K. Sharma
  • Patent number: 9496314
    Abstract: Shared source line magnetic tunnel junction (MTJ) bit cells employing uniform MTJ connection patterns for reduced area are disclosed. In one aspect, a two (2) transistor, two (2) MTJ (2T2MTJ) bit cell includes a shared source line system having first and second source lines. A uniform MTJ connection pattern results in the first source line disposed in an upper metal layer and electrically coupled to a free layer of a first MTJ, and the second source line disposed in a lower metal layer and electrically coupled to a second access transistor. Middle segments are disposed in middle metal layers to reserve the middle metal layers for strap segments of a strap cell that may be used to electrically couple the first and second source lines. Electrically coupling the first and second source lines using the strap cell allows each MTJ to logically share a single source line.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: November 15, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Yu Lu, Xiaochun Zhu, Xia Li, Seung Hyuk Kang
  • Patent number: 9442661
    Abstract: A multidimensional storage array includes independently addressable storage elements and an input shifter. The storage elements are physically arranged into rows and columns and store particular bit(s) of a data word. The input shifter implements a circular shift to serially loaded data words to the multidimensional storage array. An output shifter may reverse the circular shift of a requested data word. The data entering the storage array may be shifted to expose column addressed data such that an entire column or columns may be fed to a requesting device in a single hardware clock cycle and/or may be shifted to expose row addressed data such that an entire row or rows may be fed to the requesting device in a single hardware clock cycle. The data entering the storage array may be shifted such that column addressed data words may be stored in a plurality of diagonally arranged storage elements.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: September 13, 2016
    Assignee: International Business Machines Corporation
    Inventors: Tobias Blaettler, Charles J. Camp, Thomas Parnell
  • Patent number: 9425225
    Abstract: Unit pixel cells each includes: a photoelectric conversion film; a transparent electrode; a pixel electrode; an amplification transistor; a reset transistor; and an element isolation STI and a leakage suppression region for electrically isolating the amplification transistor and the reset transistor, the first isolation region being in a silicon substrate, between the amplification transistor and the reset transistor, the reset transistor including: a gate electrode; and a drain region which is connected to the pixel electrode, and is in the silicon substrate, between the gate electrode and element isolation STI and the leakage suppression region, in which a depletion layer formed by a first PN junction between the drain region and its surrounding region and in contact with a surface of the silicon substrate is narrower than a depletion layer formed by a second PN junction between the drain region and its surrounding region and formed in the silicon substrate.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: August 23, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Yoshiyuki Matsunaga
  • Patent number: 9264639
    Abstract: A control pulse is generated a first control signal line coupled to a transfer gate of a pixel to enable photocharge accumulated within a photosensitive element of the pixel to be transferred to a floating diffusion node, the first control signal line having a capacitive coupling to the floating diffusion node. A feedthrough compensation pulse is generated on a second signal line of the pixel array that also has a capacitive coupling to the floating diffusion node. The feedthrough compensation pulse is generated with a pulse polarity opposite the pulse polarity of the control pulse and is timed to coincide with the control pulse such that capacitive feedthrough of the control pulse to the floating diffusion node is reduced.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: February 16, 2016
    Assignee: Rambus Inc.
    Inventors: Michael Guidash, Jay Endsley, John Ladd, Thomas Vogelsang, Craig M. Smith
  • Patent number: 9190533
    Abstract: Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: November 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoungkeun Son, Hansoo Kim, Jinho Kim, Kihyun Kim
  • Patent number: 9190434
    Abstract: Techniques and mechanisms to improve potential well characteristics in a pixel cell. In an embodiment, a coupling portion of a pixel cell couples a reset transistor of the pixel cell to a floating diffusion node of the pixel cell, the reset transistor to reset a voltage of the floating diffusion node. In another embodiment, the pixel cell includes a shield line which extends athwart the coupling portion, where the shield line is to reduce a parasitic capacitance of the reset transistor to the floating diffusion node.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: November 17, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventor: Sohei Manabe
  • Patent number: 9184316
    Abstract: An insulating layer is layered above a substrate, and a plurality of pixel electrodes are formed above the insulating layer in a matrix with intervals therebetween. A photoelectric conversion layer and an opposing electrode are formed in respective order above the pixel electrodes. A dummy layer is formed above the insulating layer in a region that in plan-view is more peripheral than a pixel region in which the pixel electrodes are formed. The dummy layer is formed from the same material as the pixel electrodes. The dummy layer is composed of a plurality of dummy layer portions that are each equal to each of the pixel electrodes in terms of size in plan-view. The dummy layer functions as a support layer for planarization during polishing by chemical mechanical polishing.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: November 10, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shunsuke Isono, Tetsuya Ueda
  • Patent number: 9136276
    Abstract: A method for forming a memory cell structure includes following steps. A substrate including at least a memory cell region defined thereon is provided, and a first gate stack is formed in the memory cell region. A first LDD implantation is performed to form a first LDD at one side of the first gate stack in the memory cell region, and the first LDD includes a first conductivity type. A second LDD implantation is performed to form a second LDD at one side of the first gate stack opposite to the first LDD in the memory cell region, and the second LDD includes the first conductivity type. The first LDD and the second LDD are different from each other.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: September 15, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Huei Huang, Sung-Bin Lin, Wen-Chung Chang, Feng-Ji Tsai, Yen-Ting Ho, Chien-Hung Chen
  • Patent number: 9082877
    Abstract: A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: July 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Yue Liang, Dureseti Chidambarrao, Brian J. Greene, William K. Henson, Unoh Kwon, Shreesh Narasimha, Xiaojun Yu
  • Patent number: 9071780
    Abstract: A solid-state imaging device includes: a unit pixel including a photoelectric conversion section, an impurity-diffusion region capable of temporarily accumulating or holding electric charges generated by the photoelectric conversion section, and a reset transistor resetting the impurity-diffusion region by a voltage of a voltage-supply line, and having an impurity concentration such that at least the reset transistor side of the impurity-diffusion region becomes a depletion state; and a drive circuit changing the voltage of the voltage-supply line from a first voltage lower than a depletion potential of the reset transistor side of the impurity-diffusion region to a second voltage higher than the depletion potential while the reset transistor is on.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: June 30, 2015
    Assignee: SONY CORPORATION
    Inventor: Yusuke Oike
  • Patent number: 8969947
    Abstract: A memory device includes a substrate, a semiconductor column extending perpendicularly from the substrate and a plurality of spaced-apart charge storage cells disposed along a sidewall of the semiconductor column. Each of the storage cells includes a tunneling insulating layer disposed on the sidewall of the semiconductor column, a polymer layer disposed on the tunneling insulating layer, a plurality of quantum dots disposed on or in the polymer layer and a blocking insulating layer disposed on the polymer layer.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-goo Lee, Jung-dal Choi, Young-woo Park
  • Publication number: 20150048427
    Abstract: A pixel cell includes a photodiode disposed in an epitaxial layer in a first region of semiconductor material. A floating diffusion is disposed in a well region disposed in the epitaxial layer in the first region. A transfer transistor is disposed in the first region and coupled between the photodiode and the floating diffusion to selectively transfer image charge from the photodiode to the floating diffusion. A deep trench isolation (DTI) structure lined with a dielectric layer inside the DTI structure is disposed in the semiconductor material isolates the first region on one side of the DTI structure from a second region of the semiconductor material on an other side of the DTI structure. Doped semiconductor material inside the DTI structure is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion.
    Type: Application
    Filed: August 15, 2013
    Publication date: February 19, 2015
    Applicant: Omnivision Technologies, Inc.
    Inventors: Sing-Chung Hu, Rongsheng Yang, Gang Chen, Howard E. Rhodes, Sohei Manabe, Hsin-Chih Tai
  • Publication number: 20150041866
    Abstract: According to one embodiment, a solid-state imaging device is provided. The solid-state imaging device includes a photoelectric conversion element, a floating diffusion, and an amplifying transistor. The photoelectric conversion element photoelectrically convert incident light into electric charges with an amount corresponding to an amount of the incident light, and accumulates the electric charges. The floating diffusion accumulates the electric charges read out from the photoelectric conversion element. The amplifying transistor includes a gate electrode connected to the floating diffusion, and outputs a signal based on the amount of the electric charges accumulated in the floating diffusion. The amplifying transistor includes a first concentration region disposed in at least a part of the maximum region of the depletion layer and a second concentration region disposed at a deeper position than the first concentration region, and has higher impurity concentration than that of the first concentration region.
    Type: Application
    Filed: December 13, 2013
    Publication date: February 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Nagataka TANAKA
  • Publication number: 20150035013
    Abstract: An image pickup device according to the present invention is an image pickup device in which a plurality of pixel are arranged in a semiconductor substrate. Each of the plurality of pixels includes a photoelectric conversion element, a floating diffusion (FD) region, a transfer gate that transfers charges in the first semiconductor region to the FD region, and an amplification transistor whose gate is electrically connected to the FD region. The photoelectric conversion element has an outer edge which has a recessed portion in plan view, a source region and a drain region of the amplification transistor are located in the recessed portion, and the FD region is surrounded by the photoelectric conversion region or is located in the recessed portion in plan view.
    Type: Application
    Filed: October 15, 2014
    Publication date: February 5, 2015
    Inventors: Kazuaki Tashiro, Shin Kikuchi
  • Patent number: 8946794
    Abstract: An image sensor includes a first device isolation layer separating a plurality of pixels from one another, and a second device isolation layer disposed along inner side surfaces of parts of the first device isolation layer that extend around the pixels. The second device isolation layer delimits an active region of the semiconductor substrate. Each pixel includes a photoelectric converter, a floating diffusion region, a ground region, and a gate of a transfer transistor. The gate extends into the active region of the semiconductor substrate. The ground region is electrically connected to a ground voltage terminal.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jungchak Ahn
  • Patent number: 8878264
    Abstract: A global shutter pixel cell includes a serially connected anti-blooming (AB) transistor, storage gate (SG) transistor and transfer (TX) transistor. The serially connected transistors are coupled between a voltage supply and a floating diffusion (FD) region. A terminal of a photodiode (PD) is connected between respective terminals of the AB and the SG transistors; and a terminal of a storage node (SN) diode is connected between respective terminals of the SG and the TX transistors. A portion of the PD region is extended under the SN region, so that the PD region shields the SN region from stray photons. Furthermore, a metallic layer, disposed above the SN region, is extended downwardly toward the SN region, so that the metallic layer shields the SN region from stray photons. Moreover, a top surface of the metallic layer is coated with an anti-reflective layer.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: November 4, 2014
    Assignee: Aptina Imaging Corporation
    Inventors: Sergey Velichko, Jingyi Bai
  • Patent number: 8878279
    Abstract: A memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body by a tunneling dielectric film, and a control gate separated from the self-aligned floating gate by a blocking dielectric film. The floating gate is flanked by the memory cell body and the control gate to form a memory cell, and the self-aligned floating gate is at least as thick as the control gate. Methods for building such a memory device are also disclosed.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: November 4, 2014
    Assignee: Intel Corporation
    Inventor: Randy J. Koval
  • Patent number: 8872239
    Abstract: An image pickup device according to the present invention is an image pickup device in which a plurality of pixel are arranged in a semiconductor substrate. Each of the plurality of pixels includes a photoelectric conversion element, a floating diffusion (FD) region, a transfer gate that transfers charges in the first semiconductor region to the FD region, and an amplification transistor whose gate is electrically connected to the FD region. The photoelectric conversion element has an outer edge which has a recessed portion in plan view, a source region and a drain region of the amplification transistor are located in the recessed portion, and the FD region is surrounded by the photoelectric conversion region or is located in the recessed portion in plan view.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: October 28, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuaki Tashiro, Shin Kikuchi
  • Publication number: 20140284665
    Abstract: There is provided a solid-state imaging device including a pixel array unit in which pixels are arrayed in a two-dimensional manner, each of the pixels including a plurality of photoelectric conversion elements and a floating diffusion configured to accumulate an electric charge from the plurality of photoelectric conversion elements, wherein the floating diffusion is shared by at least two or more of the photoelectric conversion elements, and wherein one or more of the plurality of photoelectric conversion elements include a transfer gate configured to transfer an electric charge between the photoelectric conversion elements that are adjacent.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 25, 2014
    Applicant: Sony Corporation
    Inventor: Takashi Abe
  • Publication number: 20140263947
    Abstract: A pixel element for an image sensor comprises a semiconductor substrate; a radiation-sensitive element configured to generate electric charges in response to incident radiation, and provided with a charge accumulation region configured to accumulate at least a portion of said electric charges; a passive potential barrier region; and a capacitive element operably connected to the charge-accumulation region of the radiation-sensitive element via the passive potential barrier region, the passive potential barrier region being configured to conduct charges from said charge accumulation region to the capacitive element when at least a predetermined amount of electrical charge has accumulated in said charge accumulation region.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicants: CAELESTE CVBA
    Inventor: Bart DIERICKX
  • Patent number: 8829407
    Abstract: This is generally directed to systems and methods for reduced metal lines and control signals in an imaging system. For example, in some embodiments a pixel cell of an imaging system can operate without a row select transistor, and therefore can operate without a row select metal control line. As another example, in some embodiments a pixel cell can share its reset transistor control line with a transfer transistor control line of another pixel cell. In this manner, an imaging system can be created that averages a single metal line per pixel cell. In some embodiments, operation of such reduced-metal line imaging systems can use modified timing schemes of control signals.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: September 9, 2014
    Assignee: Aptina Imaging Corporation
    Inventors: John Ladd, Gennadiy Agranov, Xiangli Li
  • Patent number: 8803243
    Abstract: A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yue Liang, Dureseti Chidambarrao, Brian J. Greene, William K. Henson, Unoh Kwon, Shreesh Narasimha, Xiaojun Yu
  • Patent number: 8766228
    Abstract: An electrically actuated device includes a first electrode, a second electrode, and an active region disposed between the first and second electrodes. The device further includes at least one of dopant initiators or dopants localized at an interface between i) the first electrode and the active region, or ii) the second electrode and the active region, or iii) the active region and each of the first and second electrodes.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: July 1, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jianhua Yang, Duncan Stewart, Philip J. Kuekes, William M. Tong
  • Patent number: 8766387
    Abstract: A device includes a Backside Illumination (BSI) image sensor chip, which includes an image sensor disposed on a front side of a first semiconductor substrate, and a first interconnect structure including a plurality of metal layers on the front side of the first semiconductor substrate. A device chip is bonded to the image sensor chip. The device chip includes an active device on a front side of a second semiconductor substrate, and a second interconnect structure including a plurality of metal layers on the front side of the second semiconductor substrate. A first via penetrates through the BSI image sensor chip to connect to a first metal pad in the second interconnect structure. A second via penetrates through a dielectric layer in the first interconnect structure to connect to a second metal pad in the first interconnect structure, wherein the first via and the second via are electrically connected.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Feng-Chi Hung, Dun-Nian Yaung, Jen-Cheng Liu, Szu-Ying Chen, Wen-De Wang, Tzu-Hsuan Hsu
  • Patent number: 8749678
    Abstract: A solid-state imaging apparatus which performs a global exposure operation, in a determined imaging region, for performing exposure as matching respective start times and respective end times of all rows, comprises: plural unit pixels arranged in two-dimensional matrix and each comprising a photoelectric converting unit for generating a pixel signal by photoelectric conversion, a holding unit for holding the generated pixel signal, and a first gate for transferring the generated pixel signal to the holding unit; a first controlling line connected commonly to the first gates in the unit pixels on the same row; a vertical controlling circuit for resetting the unit pixel; and a first driving line connected to the first controlling line, and not connected to and thus independent of the vertical controlling circuit, thereby enabling to reduce a current flowing in a power supply of the vertical controlling circuit when driving electrodes of the holding units.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 10, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yuichiro Yamashita