Abstract: A solid-state imaging device includes a transfer element line for transferring an electric charge that is photoelectrically converted in a photoelectric conversion element line formed of a plurality of photoelectric conversion elements, and a charge detector for detecting an electric charge that is transferred by the transfer element line. The charge detector includes output gates disposed adjacently to a final transfer gate of the transfer element line, a reset gate for resetting an electric charge in the charge detector, a floating diffusion formed on a substrate surface adjacently to the output gates and the reset gate, and addition gates formed above the floating diffusion and along the direction from the output gates to the reset gate.

Abstract: A solid-state imaging apparatus includes a plurality of photoelectric conversion devices, a charge transfer device for transferring a signal charge converted by the photoelectric conversion devices, a signal charge detection portion for converting a signal charge transferred by the charge transfer device into a signal voltage, a reset circuit for resetting a potential of the signal charge detection portion, and an amplification portion for amplifying the signal voltage. The amplification portion includes a two-stage source follower, each supplied with power supply voltages different from the power supply voltage to be supplied to the reset circuit. The second stage source follower includes drive transistor, and a current source that changes a current amount according to a fluctuation of the reset potential VRD.

Abstract: A CMOS image sensor and a method for forming the same are provided. According to the method, a gate insulating layer and a doped polysilicon layer which are sequentially stacked on a substrate are patterned to form a transfer gate and a reset gate set apart from each other. A floating diffusion layer between the transfer gate and the reset gate, a light receiving element at a side of the transfer gate away from and opposite to the floating diffusion layer and a source/drain region at a side of the reset gate away from and opposite to the floating diffusion layer are formed. An insulation layer and a mold layer are sequentially formed on an entire surface of the substrate, and the mold layer is planarized until the insulation layer is exposed. The exposed insulation layer is removed to further expose an upper surface of the gates. A selective silicidation process is carried out using a metal gate layer to form a metal gate silicide on the exposed gate.

Abstract: An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices.

Abstract: Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.

Abstract: Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.

Abstract: An imaging device having a pixel array in which one plate of a storage capacitor is coupled to a storage node while another plate is formed by an electrode of a photo-conversion region.

Abstract: Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.

Abstract: A semiconductor device includes: a SOI substrate having a SOI layer, a buried oxide layer and a support substrate; multiple first separation trenches on the SOI layer; multiple MOS transistors, each of which is surrounded with one first separation trench; a second separation trench on the SOI layer including n-ply field trenches; and multiple field regions such that a k-th field region is surrounded with a k-th field trench. One MOS transistor is disposed in each field region. The MOS transistors are connected in series. The first MOS transistor has a gate terminal as an input terminal. The n-th MOS transistor is connected to the power source potential through an output resistor. The n-th field region has an electric potential, which is fixed to the power source potential.

Abstract: A pixel of an image sensor includes a gate insulation layer formed over a substrate doped with first-type impurities, a transfer gate formed over the gate insulation layer, a photodiode formed in the substrate at one side of the transfer gate, and a floating diffusion node formed in the substrate at the other side of the transfer gate, wherein the transfer gate has a negative bias during a charge integration cycle.

Abstract: A solid-state image sensing device has a pixel that includes a photodiode that generates an electrical charge according to an amount of incoming light, a floating diffusion portion, a charge transfer transistor that transfers the electrical charge to the floating diffusion portion from the photoelectric conversion portion, a reading circuit that outputs an signal on the basis of said electrical charge held in said floating diffusion portion, and a light-shielding member disposed so as to cover a side wall of a gate electrode of the charge transfer transistor on the photoelectric conversion portion side.

Abstract: Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.

Abstract: A signal processing device is provided which is capable of suppressing a voltage change of a power supply when output signals from a plurality of signal sources are read, and capable of outputting a stable signal at a high sensitivity, and an image pickup apparatus using such a signal processing device is also provided. The signal processing device has: a plurality of terminals connectable to a plurality of signal sources; and a read circuit for converting signals input from the terminals into serial signals and outputting the serial signals, wherein: the read circuit comprises a holding capacitor connected to each of the terminals, a transfer switch for transferring a signal held in the holding capacitor to a common signal line, and a shift register for driving the transfer switch; and a semiconductor layer under the common signal line has a conductivity type opposite to a first conductivity type of a semiconductor substrate.

Abstract: An imaging method, apparatus, and system having pixels that store charge from a photosensor in a storage diode are disclosed. Charge accumulated in the photosensor during an integration period is transferred to and stored in the storage diode prior to readout in a global shutter imager.

Abstract: A pixel circuit of an image sensor includes a photo-converting unit such as a photo-diode for generating charge from incident light. The pixel circuit also includes a charge storing capacitor for storing the charge generated by the photo-converting unit. The pixel circuit further includes a floating diffusion node that receives the charge from the charge storing unit after being reset. Thus, an image signal VSIG is generated after a reset signal VRES is generated from the pixel circuit.

Abstract: A solid-state image pickup device includes a semiconductor substrate, a photosensitive pixel which converts incident light on the semiconductor substrate into a signal charge, and a charge detection section which converts the converted signal charge into an output signal. The device further includes a charge transfer section which is disposed between the photosensitive pixel and the charge detection section and which temporarily stores the signal charge and which transfers the stored signal charge to the charge detection section by application of sequential pulses.

Abstract: Non-volatile memory devices and arrays are described that utilize back-side trapped floating node memory cells with band-gap engineered gate stacks with asymmetric tunnel barriers. Embodiments of the present invention allow for direct tunneling programming and efficient erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention and reduces the possibility of damage to the channel/insulator interface. The direct tunneling program and efficient erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory device embodiments of the present invention are presented that are arranged in NOR or NAND memory architecture arrays. Memory cell embodiments of the present invention also allow multiple levels of bit storage in a single memory cell, and allow for programming and erase with reduced voltages.

Abstract: A semiconductor memory (26) having a plurality of memory cells (25), the semiconductor memory (26) having a substrate (1), at least one wordline (2) and first (3) and second lines (4). Each memory cell (25) of the plurality of memory cells (25) includes a fin (15) of semiconductor material, the fin (15) having a top surface (5), first (6) and second (7) opposing sidewalls and first (8) and second (9) opposing ends. The fin (15) extends along a first direction (X). Each memory cell (25) also includes a charge-trapping layer (11) disposed on the first (6) and second (7) sidewalls of said fin (15), a patterned first insulating layer (10) disposed on the top surface (5) of the fin (15), wherein the first insulating layer (10) abuts the top surface (5) of the fin (15) and the charge-trapping layer (11). Each memory cell (25) also includes a first doping region (12) coupled to the first end (8) of said fin (15) and a second doping region (13) coupled to the second end (9) of the fin (15).

Abstract: The present invention provides an imager device with a floating diffusion region resistant to charge leakage. The floating diffusion region is formed having a first doped region and a second doped region which has a higher concentration of dopants than the first doped region. The floating diffusion region is resistant to charge leakage while maintaining good contact to a conductor connected to a gate of a source follower transistor.

Abstract: A solid-state imaging apparatus includes a pixel array comprising a plurality of light receiving elements disposed in a charge transfer direction, the plurality of light receiving elements converting a light signal into an electric signal, a first charge transfer unit and a second charge transfer unit arranged on each side of the pixel array and transferring a signal charge input from the pixel array in the charge transfer direction, a first floating diffusion region connected to the first charge transfer unit, a second floating diffusion region connected to the second charge transfer unit, a wiring layer connecting the first floating diffusion region with the second floating diffusion region, and an output circuit connected to the wiring layer and output a signal voltage in accordance with a potential of the first floating diffusion region and the second floating diffusion region.

Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor comprises a photodiode region generating electrical charges in response to incident light thereon. The CMOS image sensor further comprises a first floating diffusion layer adapted to receive the electrical charges from the photodiode region in response to a global transfer signal and a second floating diffusion region adapted to receive the electrical charges from the first floating diffusion region in response to a pixel selection signal.

Abstract: A solid-state image pickup device including a charge transferrer to transfer a signal charge obtained through photoelectric conversion; a floating diffusion region; a reset means for resetting the potential of the floating diffusion region; and a current source for supplying, to the floating diffusion region, a signal charge corresponding to the quantity of the signal charge transferred by the charge transferrer. The current source such as a current mirror circuit is interposed between the output stage of a horizontal CCD and the floating diffusion region so as to supply thereto a signal charge corresponding to the quantity of the signal charge transferred by the horizontal CCD, hence separating the horizontal CCD and the floating diffusion region potentially from each other, whereby the supply voltage, i.e., the reset voltage for the floating diffusion region, can be set independently of the potential of the horizontal CCD.

Abstract: A sense resistor and integrated circuit package combination is disclosed. A package lead frame is provided having a plurality of landing zones associated therewith and a die mounting area for mounting of a die thereon. The die has a plurality of bond pads associated therewith, with a first bond wire connected between a first one of the landing zones and a second one of the landing zones. The first bond wire forms a sense resistor with a resistance of a known value. A second bond wire is connected between the first one of the landing zones and a first one of the bond pads.

Abstract: A photoelectric conversion device comprising a semiconductor substrate of a first conduction type, and a photoelectric conversion element having an impurity region of the first conduction type and a plurality of impurity regions of a second conduction type opposite to the first conduction type. The plurality of second-conduction-type impurity regions include at least a first impurity region, a second impurity region provided between the first impurity region and a surface of the substrate, and a third impurity region provided between the second impurity region and the surface of the substrate. A concentration C1 corresponding to a peak of the impurity concentration in the first impurity region, a concentration C2 corresponding to a peak of the impurity concentration in the second impurity region and a concentration C3 corresponding to a peak of the impurity concentration in the third impurity region satisfy the following relationship: C2<C3<C1.

Abstract: An image sensor includes a reset transistor, reset gate electrodes and a potential shift circuit. The reset transistor includes a reset gate and a reset drain, and resets charges detected by a charge detection device. The reset gate electrodes control a potential of the reset gate. The potential shift circuit initializes output signals in response to a shift pulse, and outputs the output signals to the reset gate electrodes in response to a reset pulse.

Abstract: A gate electrode region of a junction transistor in a signal charge-voltage converter is allowed to have a structure that a gentle potential gradient is formed without generation of a potential barrier. Thus, it is possible to readily realize a signal charge-voltage converter which is high in S/N ratio without generation of reset noise and is excellent in signal charge-voltage conversion efficiency.

Abstract: The solid-state imaging device of the present invention includes: a floating diffusion capacity unit which is formed on a semiconductor substrate, and is operable to hold signal charges derived from incident light; an amplifier which is operable to convert the signal charges held in the floating diffusion capacity unit into a voltage; the first wire which connects the floating diffusion capacity unit to an input of the amplifier; and a second wire which is made of the same material as the first wire, formed in the same layer as the first wire, arranged around the first wire at least along long sides of the first wire, and electrically insulated from the first wire.

Abstract: A nonvolatile memory device includes a semiconductor substrate, a device isolation film, a tunnel insulation film, a plurality of floating gates, an inter-gate dielectric film, and a control gate pattern. Trenches are formed in the substrate that define active regions therebetween. The device isolation film is in the trenches in the substrate. The tunnel insulation film is on the active regions of the substrate. The plurality of floating gates are each on the tunnel insulation film over the active regions of the substrate. The inter-gate dielectric film extends across the floating gates and the device isolation film. The control gate pattern is on the inter-gate dielectric film and extends across the floating gates. A central region of the device isolation film in the trenches has an upper major surface that is recessed below an upper major surface of a surrounding region of the device isolation film in the trenches.

Abstract: A nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit comprises a semiconductor substrate, isolation insulating films for defining a plurality of element formation regions, each of the isolation insulating films being buried in an isolation trench provided in the semiconductor substrate, a floating gate provided in each of the element formation regions via a first gate insulating film, a control gate provided on the floating gate via a second gate insulating film, and source and drain regions provided in the semiconductor substrate in self-alignment with the control gate, wherein the floating gate is self-aligned at an isolation end in a direction of a channel width, and comprises a plurality of polysilicon films.

Abstract: To provide a solid-state imaging device in which the number of transistors for each signal readout circuit provided in a semiconductor substrate side is reduced and the number of image signal readout lines is reduced, solid-state imaging device a semiconductor substrate; a stacked photoelectric conversion films detecting different colors contained in an incident light; and pixel electrode films partitioned in accordance with pixels, wherein the semiconductor substrate includes: a plurality of color selection transistors corresponding to one of the pixels, wherein the color selection transistors each corresponds to one of the photoelectric conversion films and connects to one of the pixel electrode films on the one of the photoelectric conversion films so as to be capable of selecting the one of the photoelectric conversion films; and a charge detection cell corresponding to one of the pixels, the charge detection cell being common to the photoelectric conversion films.

Abstract: A split gate flash memory is provided. Trenches are formed in the substrate to define active layers. The device isolation layers are formed in the trenches. The surface of the device isolation layers is lower than the surface of the active layers. The stacked gate structures each including a tunneling dielectric layer, a floating gate and a cap layer are formed on the active layers. The inter-gate dielectric layers are formed on the sidewalls of the stacked gate structures. The select gates are formed on one side of the stacked gate structure and across the active layer. The select gate dielectric layers are formed between the select gates and the active layers. The source regions are formed in the active layers on the other side of the stacked gate structures. The drain regions are formed in the active layers on one side of the select gates.

Abstract: An active pixel is described comprising a semiconductor substrate and a radiation sensitive source of carriers in the substrate, such as for instance, a photodiode. A non-carrier storing, carrier collecting region in the substrate is provided for attracting carriers from the source as they are generated. At least one doped or inverted region of a first conductivity is provided in or on the substrate for storing the carriers before read-out. At least one non-carrier storing, planar current flow, carrier transport pathway is provided from or through the carrier collecting region to the at least one doped or inverted region to transfer the carriers without intermediate storage to the read-out electronics.

Abstract: A high-performance solid-state imaging device is provided. The solid-state imaging device includes: a plurality of pixel cells; and a driving unit. Each of the plurality of pixel cells includes: a photodiode that converts incident light into a signal charge and stores the signal charge; a MOS transistor that is provided for reading out the signal charge stored in the photodiode; an element isolation portion that is formed of a STI that is a grooved portion of the semiconductor substrate so that the photodiode and the MOS transistor are isolated from each other; and a deep-portion isolation implantation layer that is formed under the element isolation portion for preventing a flow of a charge from the photodiode to the MOS transistor.

Abstract: Structures and methods for programmable array type logic and/or memory devices with graded composition metal oxide tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include a floating gate transistor. The floating gate has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate and is separated from the floating gate by a compositionally graded mixed metal oxide tunnel barrier intergate insulator.

Abstract: In the present invention, a charge transfer unit is arranged on a first-plane side of a thinly-formed semiconductor base. Charge accumulating units are arranged on a second-plane side, the opposite side. A depletion prevention layer is arranged closer to the second-plane side than the charge accumulating units. The depletion prevention layer prevents a depletion region around the charge accumulating units from reaching the second plane of the semiconductor base. The depletion prevention layer can suppress surface dark current going into the charge accumulating units. Meanwhile, an energy ray incident from the second-plane side pass through the depletion prevention layer to generate signal charges in the charge accumulating units (depletion regions). The charge accumulating units collect, on a pixel-by-pixel basis, the signal charges which are to be transported to the charge transfer unit under voltage control or the like, and then are read to exterior as image signals.

Abstract: Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which has a first source/drain region and a second source/drain region separated by a p-type channel region in an n-type substrate. A floating gate opposing the p-type channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator. The asymmetrical low tunnel barrier intergate insulator includes a metal-oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

Abstract: Structures and methods for programmable array type logic and/or memory devices with graded composition metal oxide tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include a floating gate transistor. The floating gate has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate and is separated from the floating gate by a compositionally graded mixed metal oxide tunnel barrier intergate insulator.

Abstract: A pixel cell with increased dynamic range is formed by providing a floating diffusion region having a variable capacitance, controlled by at least one gate having source and drain regions commonly connected to the floating diffusion region. The gate has an intrinsic capacitance which, when the gate is activated, is added to the capacitance of the floating diffusion region, providing a low conversion gain readout. When the gate is off, the floating diffusion region capacitance is minimized, providing a high conversion gain readout. The gate may also be selectively switched to mid-level. At mid-level, a mid-level conversion gain, which is between the high and low conversion gains, readout is provided, but the gate still provides some capacitance to prevent the floating diffusion region from saturating.

Abstract: A method for fabricating gate electrodes (7) in a field plate trench transistor (1) having a cell array with a plurality of trenches (3) and a plurality of mesa regions (8) arranged between the trenches comprises the following steps: application of a gate electrode layer (7) to the cell array in such a way that the gate electrode layer (7) has depressions within or above the trenches (3), application of a mask layer (10) to the cell array, etching-back of the mask layer (10) in such a way that mask layer residues (10) remain only within the depressions of the gate electrode layer (7), and etching-back of the gate electrode layer (7) using the mask layer residues (10) as an etching mask in such a way that gate electrode layer residues (7) remain only within/above the trenches (3).

Abstract: A static random access memory has first and second complementary field-effect transistors. The first complementary field-effect transistor includes a semiconductor substrate, a first field-effect transistor of electron conduction type which has a first drain region constituting a Schottky junction and a gate electrode, and a first field-effect transistor of positive hole conduction type which shares the first drain region and has a shared gate electrode. The second complementary field-effect transistor includes a second field-effect transistor of electron conduction type which has a second drain region and a gate electrode, a second field-effect transistor of positive hole conduction type which shares the second drain region and has a shared gate electrode.

Abstract: A field effect transistor has a floating gate with an extended portion. A selectively chemoreceptive finger or layer is electrostatically coupled to the extended portion of the floating gate, and induces a voltage on the gate in response to selected chemicals or other conditions affecting the finger. The voltage on the gate modulates current flowing between a source and a drain of the transistor, effectively sensing the presence of the selected chemicals or conditions. In one embodiment, multiple chemoreceptive fingers are electrostatically coupled to the extended portion of the floating gate. In a further embodiment, an array of such field effect transistors provide a sensor for multiple conditions.

Abstract: There is provided a charge detecting device that can convert an accumulated charge to a voltage at a low voltage and a high efficiency, and has a large dynamic range of an output voltage and satisfactory linearity of a conversion efficiency. The charge detecting device includes a charge accumulating portion including a low concentration N-type (N?) layer 108 formed in a P-type well 101 and a high concentration N-type (N+) layer formed between the N? layer and a principal surface. The N+ layer is connected to an input terminal of an amplifying transistor of an output circuit, and after a reverse bias is applied to the N+ layer during discharging of the accumulated charge, the entire N? layer is depleted at least until a saturated charge is accumulated.

Abstract: The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (2) for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate (1). The memory transistor (ST) has a first insulation layer (3), a charge storage layer (4), a second insulation layer (5) and a memory transistor control layer (6), while the selection transistor (AT) has a first insulation layer (3?) and a selection transistor control layer (4*). By using different materials for the charge storage layer (4) and the selection transistor control layer (4*), it is possible to significantly improve the charge retention properties of the memory cell by adapting the substrate doping with electrical properties remaining the same.

Abstract: The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first mass. While the sacrificial layer is over the first mass, a nitrogen-containing material is formed across the second mass. After the nitrogen-containing material is formed, the sacrificial layer is removed. Subsequently, a silicon nitride layer is formed to extend across the first and second masses, with the silicon nitride layer being over the nitrogen-containing material. Also, a conductivity-enhancing dopant is provided within the first mass. The invention also pertains to methods of forming capacitor constructions.

Abstract: A plurality of first wiring structures of a first width are arranged periodically at first intervals. A second wiring structure is formed next to one of the first wiring structures. The lower part of the second wiring structure has a second width substantially equal to the sum of n times the first width of the first wiring structure (n is a positive integer equal to two or more) and (n?1) times the first interval.

Abstract: Hot-electron injection driven by hole impact ionization in the channel-to-drain junction of a p-channel MOSFET provides a new mechanism for writing a floating-gate memory. Various pFET floating-gate structures use a combination of this mechanism and electron tunneling to implement nonvolatile analog memory, nonvolatile digital memory, or on-line learning in silicon. The memory is nonvolatile because the devices use electrically isolated floating gates to store electronic charge. The devices enable on-line learning because the electron injection and tunneling mechanisms that write the memory can occur during normal device operation. The memory updates and learning are bidirectional because the injection and tunneling mechanisms add and remove electrons from the floating gate, respectively. Because the memory updates depend on both the stored memory and the pFETs terminal voltages, and because they are bidirectional, the devices can implement on-line learning functions.

Abstract: A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate.

Abstract: A multi-bit split-gate (MSG) flash cell with multi-shared source/drain, a method of making and a method of programming the same are disclosed. Furthermore, a method of bit-by-bit erasing, in addition to page erasing, of a plurality of cells of two or more is disclosed through the application of a positive voltage forced onto the control gate of the unselected cell. Thus, by providing the bit-by-bit erasing flexibility, the bit alterability is enhanced. The MSG is formed with N+1 stacked gates comprising floating gates and control gates, separated by N select gates, all sharing the same source/drain between a pair of bit lines. The programming, that is, writing of the plurality of N+1 bits is accomplished also bit by bit where the programmed bits are selected by word line, bit line and control gate. The read operation is similar to the write operation.

Abstract: Embodiments include semiconductor devices and methods of manufacture, one of which includes a capacitor unit formed on a silicon substrate. The capacitor unit is divided into a plurality of capacitor subunits which are partitioned from each other by a separating insulation layer. Each of the capacitor subunits includes a first electrode layer composed of an impurity diffusion layer formed in the silicon substrate, a second electrode layer composed of a conductive polysilicon layer and a dielectric layer composed of a silicon oxide layer interposed between the first electrode layer and the second electrode layer. The respective capacitor subunits are connected in parallel to each other through a connector.

Abstract: A CMOS imaging device which includes a charge pump connected to one or more of a reset gate, transfer gate and row select gate of sensor cells and provides gate control signals which give the imaging device an increased dynamic range charge capacity while minimizing signal leakage. A charge pump may also supply control signals to photogates used in the cells.