Field Effect Device Patents (Class 257/24)
  • Patent number: 11170948
    Abstract: The present invention relates to a method for preparing an electrode comprising a metal substrate, vertically aligned carbon nanotubes and a metal oxide deposited over the entire length of said vertically aligned carbon nanotubes, said method comprising the following consecutive steps: (a) synthesizing, on a metal substrate, a mat of vertically aligned carbon nanotubes; and (b) depositing a metal oxide matrix over the entire height of said vertically aligned carbon nanotube mat via spontaneous reduction at a temperature not exceeding 40° C. The present invention also relates to said electrode and to the uses thereof.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: November 9, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Mathieu Pinault, Fouad Ghamouss, Francois Tran Van, Emeline Charon, Baptiste Pibaleau
  • Patent number: 11158730
    Abstract: A method of forming a field effect transistor (FET) includes performing an oxidation on a nanosheet structure having alternating sheets of silicon and silicon germanium. An oxide etch is performed to remove portions of the sheets of silicon germanium. Other embodiments are also described herein.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: October 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 11152516
    Abstract: There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: October 19, 2021
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 11152346
    Abstract: A capacitive element using VNW FETs is provided. First and second components each constituting a transistor are arranged in an X direction. From the first component, a first gate interconnect extends away from the second component, and a first top interconnect and a first bottom interconnect extend toward the second component. From the second component, a second gate interconnect extends toward the first component, and a second top interconnect and a second bottom interconnect extend away from the first component. The first top interconnect, the first bottom interconnect, and the second gate interconnect are connected.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: October 19, 2021
    Assignee: SOCIONEXT INC.
    Inventor: Isaya Sobue
  • Patent number: 11145753
    Abstract: The present disclosure discloses a ballistic transport semiconductor device based on nano array and a manufacturing method thereof. The ballistic transport semiconductor device based on nano array comprises a conducting substrate, more than one semiconductor nano bump portion is arranged on a first surface of the conducting substrate, a top end of the semiconductor nano bump portion is electrically connected with a first electrode, a second surface of the conducting substrate is electrically connected with a second electrode, the second surface and the first surface are arranged back to back, and the height of the semiconductor nano bump portion is less than or equal to a mean free path of a carrier. The carrier is not influenced by various scattering mechanisms in a transporting procedure by virtue of the existence of ballistic transport characteristics, thereby obtaining a semiconductor device having advantages of lower on resistance, less working power consumption.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: October 12, 2021
    Assignee: SUZHOU INSTITUTE OF NANO-TECH AND NANO-BIONICS (SINANO), CHINESE ACADEMY OF SCIENCES
    Inventors: Guohao Yu, Fu Chen, Wenxin Tang, Xiaodong Zhang, Yong Cai, Baoshun Zhang
  • Patent number: 11139299
    Abstract: Embodiments of the present invention provide improved methods and structures for fabrication of capacitor-less DRAM devices, sometimes referred to as ZRAM devices. A channel is formed in a fin-type field effect transistor (finFET) that is comprised of a finned channel portion and a convex channel portion. The finned channel portion may be comprised of a first semiconductor material and the convex channel portion may be comprised of a second, different semiconductor material. In embodiments, a metal gate is disposed around the elongated surface of the channel region, but is not disposed on the short surface of the channel region. A first spacer is disposed adjacent to the gate and in direct physical contact with the short surface of the channel region, and a second spacer is disposed adjacent to the first spacer.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: October 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ravikumar Ramachandran, Reinaldo Ariel Vega
  • Patent number: 11133384
    Abstract: A semiconductor transistor device includes an emitter region that includes a plurality of metal quantum wires and is connected to an emitter terminal, a base region that includes a plurality of metal quantum wires and is connected to a base terminal, a collector region comprising a plurality of metal quantum wires and is connected to a collector terminal, an emitter barrier region between the emitter region and the base region, and a collector barrier region between the collector region and the base region.
    Type: Grant
    Filed: April 19, 2020
    Date of Patent: September 28, 2021
    Inventor: Koucheng Wu
  • Patent number: 11133403
    Abstract: A device includes a substrate, a first doping portion, a second doping portion, a channel, a semiconductor film, a high-k layer, and a gate. The first doping portion and the second doping portion are over the substrate. The channel is over the substrate and between the first doping portion and the second doping portion. The semiconductor film is around the channel. The high-k layer is around the semiconductor film. The gate is over the high-k layer.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Sheng Chen, Cheng-Hsien Wu, Chih-Chieh Yeh
  • Patent number: 11127820
    Abstract: A quantum well field-effect transistor (QWFET) includes a barrier layer, a quantum well layer, and a spacer layer. The quantum well layer is on the barrier layer. The barrier layer and the spacer layer comprise aluminum indium antimonide that is undoped. The quantum well layer comprises indium antimonide. The spacer layer is on the quantum well layer. The quantum well layer and the spacer layer are between a source contact and a drain contact. A gate contact is on a dielectric layer, which is on the spacer layer. By providing the barrier layer and the spacer layer as undoped layers, a performance of the QWFET may be improved.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: September 21, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Michael James Manfra, Candice Fanny Thomas
  • Patent number: 11121215
    Abstract: A technique relates to a semiconductor device. A stack includes two or more nanowires separated by a high-k dielectric material, the high-k dielectric material being formed on at least a center portion of the two or more nanowires in the stack. A separation space between the two or more nanowires is less than two times a thickness of the high-k dielectric material formed on a side wall of the two or more nanowires. A source or a drain formed on sides of the stack.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: September 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juntao Li, Kangguo Cheng, Chen Zhang, Xin Miao
  • Patent number: 11114435
    Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to FinFET transistors. In one aspect, at least three fins are arranged to extend in parallel in a first direction and are laterally separated from each other in a second direction by shallow trench isolation structures having a first fin spacing, where at least a portion of each fin protrudes out from a substrate. At least a portion of each of a first fin and a second fin of the at least three fins vertically protrude to a level higher than an upper surface of the shallow trench isolation structures. A third fin is formed laterally between the first fin and the second fin in the second direction, where the third fin has a non-protruding region which extends vertically to a level below or equal to the upper surface of the shallow trench isolation structures.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 7, 2021
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Geert Hellings, Roman Boschke, Dimitri Linten, Naoto Horiguchi
  • Patent number: 11107932
    Abstract: There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: August 31, 2021
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 11101371
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay Chuang, Yi-Ren Chen, Chi-Wen Liu, Chao-Hsiung Wang, Ming Zhu
  • Patent number: 11094811
    Abstract: A semiconductor device includes a substrate, a channel layer, an insulating layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The channel layer over the substrate and includes two dimensional (2D) material. The insulating layer is on the channel layer. The source/drain contacts are over the channel layer. The gate dielectric layer is over the insulating layer and the channel layer. The gate electrode is over the gate dielectric layer and between the source/drain contacts.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tse-An Chen, Lain-Jong Li, Wen-Hao Chang, Chien-Chih Tseng
  • Patent number: 11088032
    Abstract: In embodiments of the present disclosure, an ambient medium of a two-dimensional semiconductor is doped or an ambient medium of a semiconductor is locally filled with a solid material, to form a filled region, and an electronic device based on the two-dimensional semiconductor is implemented by means of a doping effect of the doped region or the filled region on a characteristic of the two-dimensional semiconductor. In the embodiments of the present disclosure, doping the two-dimensional semiconductor is not directly processing the two-dimensional semiconductor. Therefore, damage caused to the two-dimensional semiconductor in a doping process and device performance deterioration caused accordingly can be effectively reduced, and stability of device performance after doping is improved.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: August 10, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Wen Yang, Riqing Zhang, Yu Xia
  • Patent number: 11081567
    Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: August 3, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jingyun Zhang, Choonghyun Lee, Chun Wing Yeung, Robin Hsin Kuo Chao, Heng Wu
  • Patent number: 11081589
    Abstract: A semiconductor device includes a substrate, an N-type bottom vertical gate-all-around (VGAA) transistor, a P-type bottom VGAA transistor, and a top VGAA transistor. The N-type bottom vertical gate-all-around (VGAA) transistor is over the semiconductor substrate and comprising a first nanowire made of InAs. The P-type bottom VGAA transistor is over the semiconductor substrate and comprising a second nanowire made of Ge. The top VGAA transistor is over the N-type bottom VGAA transistor, in which the top VGAA transistor includes a third nanowire in contact with the N-type bottom VGAA transistor, a fourth nanowire on and in contact with the third nanowire, and a bit line wrapping the fourth nanowire.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Mark Van Dal
  • Patent number: 11075107
    Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun Hao Liao, Chu Fu Chen, Chun-Wei Hsu, Chia-Cheng Pao
  • Patent number: 11069775
    Abstract: Field effect transistors and methods of forming the same include forming a stack of nanosheets of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: July 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 11069808
    Abstract: A negative capacitance field effect transistor (NCFET) and a manufacturing method thereof. The NCFET includes: a substrate structure, including a MOS region; a gate insulating dielectric structure, covering the MOS region; and a metal gate stack layer, covering the gate insulating dielectric structure. The gate insulating dielectric structure includes an interface oxide layer, a HfO2 layer, a doping material layer, and a ferroelectric material layer, which are sequentially stacked along a direction away from the substrate structure. A ferroelectric material in the ferroelectric material layer is HfxA1-xO2, A represents a doping element, and 0.1?x?0.9. A material forming the doping material layer is AyOz or A, and a ratio of y/z is equal to 1/2, 2/3, 2/5 or 1/1. Ferroelectric characteristics, material stability, and material reliability of the NCFET are improved by increasing domain polarity of the ferroelectric material.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 20, 2021
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Qingzhu Zhang, Zhaohao Zhang, Tianchun Ye
  • Patent number: 11060997
    Abstract: A biosensor comprising a substrate, a gate electrode provided on the substrate, an insulating layer provided on the gate electrode, a source electrode and a drain electrode, provided on the insulating layer, respectively, an n-type channel provided between the source electrode and the drain electrode, and a quantum dot layer provided on the n-type channel and provided so as to have electronic transition energy capable of resonating with vibration energy of a target biological material.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: July 13, 2021
    Inventors: Kwang Seob Jeong, Hang Beum Shin, Young Do Jeong, Bit Na Yoon, Dong Sun Choi, Ju Yeon Jeong
  • Patent number: 11056647
    Abstract: A carbon nanotube (CNT) single ion memory (or memory device) may include a mobile ion conductor with a CNT on one side and an ion drift electrode (IDE) on the other side. The mobile ion conductor may be used as a transport medium to shuttle ions to and from the CNT and the IDE. The IDE may move the ions towards or away from the CNT.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: July 6, 2021
    Assignee: The Aerospace Corporation
    Inventors: Adam W. Bushmaker, Don Walker
  • Patent number: 11031239
    Abstract: Devices comprising germanium nanosheets are described herein. Methods of forming such germanium nanosheets and devices including such germanium nanosheets are also described.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: June 8, 2021
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventor: Hung-Hsiang Cheng
  • Patent number: 11024746
    Abstract: Gate all-around devices are disclosed in which an angled channel comprising a semiconducting nanostructure is located between a source and a drain. The angled channel has an axis that is oriented at an angle to the top surface of the substrate at an angle in a range of about 1° to less than about 90°. The gate all-around device is intended to meet design and performance criteria for the 7 nm technology generation.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: June 1, 2021
    Assignee: Applied Materrials, Inc.
    Inventors: Russell Chin Yee Teo, Benjamin Colombeau
  • Patent number: 11005046
    Abstract: In order to obtain a carbon nanotube array including no m-CNTs through simple steps using a mechanism that is different from thermocapillary flow, there are provided a process for producing a carbon nanotube array including (A) a step of preparing a carbon nanotube array in which m-CNTs and s-CNTs are horizontally aligned; (B) a step of forming an organic layer on the carbon nanotube array; (C) a step of applying voltage to the carbon nanotube array in a long axis direction of the carbon nanotubes constituting the carbon nanotube array in the air; and (D) a step of removing the organic layer, and a carbon nanotube array obtained by the process.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: May 11, 2021
    Assignees: THE UNIVERSITY OF TOKYO, DENSO CORPORATION
    Inventors: Shigeo Maruyama, Shohei Chiashi, Keigo Ohtsuka, Taiki Inoue
  • Patent number: 10991627
    Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: April 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Chia Tai Lin, Chao-Cheng Chen
  • Patent number: 10991694
    Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: April 27, 2021
    Inventors: Sung-Dae Suk, Jongho Lee, Geumjong Bae
  • Patent number: 10988688
    Abstract: A quantum dot manufacturing method comprises (a) dispersing, in a solvent, nano-seed particles whose crystal planes are exposed, and (b) growing semiconductor layers on the exposed crystal planes of the nano-seed particles in the solvent.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: April 27, 2021
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Takuya Kazama, Wataru Tamura, Yasuyuki Miyake
  • Patent number: 10985070
    Abstract: A method for forming a nanodevice sensing chip includes forming nanodevices having a sensing region capable of producing localized Joule heating. Individual nanodevice is electrical-biased in a chemical vapor deposition (CVD) system or an atomic layer deposition (ALD) system enabling the sensing region of the nanodevice produce localized Joule heating and depositing sensing material only on this sensing region. A sensing chip is formed via nanodevices with sensing region of each nanodevice deposited various materials separately. The sensing chip is also functioned under device Joule self-heating to interact and detect the specific molecules.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: April 20, 2021
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Ru-Zheng Lin, Jeng-Tzong Sheu
  • Patent number: 10957605
    Abstract: The present invention provides VFET device designs for top contact resistance measurement. In one aspect, a method of forming a VFET test structure includes: etching fins in a substrate (for active and sensing devices); forming bottom source/drains at a base of the fins; forming a STI region that isolates the bottom source/drains of the active device from that of the sensing device; forming a gate surrounding each of the fins; forming top source/drains over the gate, wherein the top source/drains of the active device and that of the sensing device are merged; and forming contacts to i) the bottom source/drains of the active device, ii) the top source/drains of the active device, and iii) the bottom source/drains of the sensing device. A test structure formed by the method as well as techniques for use thereof for measuring contact resistance are also provided.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Zuoguang Liu
  • Patent number: 10934163
    Abstract: Novel and useful quantum structures having a continuous well with control gates that control a local depletion region to form quantum dots. Local depleted well tunneling is used to control quantum operations to implement quantum computing circuits. Qubits are realized by modulating gate potential to control tunneling through local depleted region between two or more sections of the well. Complex structures with a higher number of qdots per continuous well and a larger number of wells are fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. Combining a number of elementary quantum structure, a quantum computing machine is realized. An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 2, 2021
    Assignee: Equal1.Labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Patent number: 10930784
    Abstract: FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chun-Hsiang Fan, Tung Ying Lee, Chi-Wen Liu
  • Patent number: 10923659
    Abstract: Provided herein are wafers that can be used to align carbon nanotubes, as well as methods of making and using the same. Such wafers include alignment areas that have four sides and a surface charge, where the alignment areas are surrounded by areas that have a surface charge of a different polarity. Methods of the disclosure may include depositing and selectively etching a number of hardmasks on a substrate. The described methods may also include depositing a carbon nanotube on such a wafer.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: February 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Timothy Vasen, Gerben Doornbos, Marcus Johannes Henricus van Dal, Matthias Passlack
  • Patent number: 10916544
    Abstract: The present invention provides a Gate-All-Around nano-sheet complementary inverter, comprising: P-type semiconductor transistors and N-type semiconductor transistors, wherein the P-type semiconductor transistors comprise P-type semiconductor nano-sheet channels, a first gate dielectric layer fully surrounding the P-type semiconductor nano-sheet channels, a first gate electrode layer fully surrounding the first gate dielectric layer, a first source region and a first drain region, connected to two ends of the P-type semiconductor nano-sheet channel respectively, the N-type semiconductor transistors comprise N-type semiconductor nano-sheet channels, a second gate dielectric layer fully surrounding the N-type semiconductor nano-sheet channels, a second gate electrode layer fully surrounding the second gate dielectric layer, a second source region and a second drain region, connected to two ends of the N-type semiconductor nano-sheet channel respectively; and a common electrode fully surrounding the first gate el
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: February 9, 2021
    Assignee: SiEn (QingDao) Integrated Circuits Co., Ltd
    Inventor: Deyuan Xiao
  • Patent number: 10910488
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin has a first side face and a second side face, and the fin includes a quantum well layer; and a gate above the fin, wherein the gate extends down along the first side face.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Hubert C. George, Lester Lampert, James S. Clarke, Ravi Pillarisetty, Zachary R. Yoscovits, Nicole K. Thomas, Roman Caudillo, Kanwaljit Singh, David J. Michalak, Jeanette M. Roberts
  • Patent number: 10903370
    Abstract: In a standard cell including nanowire FETs, pads connected to nanowires are arranged at a predetermined pitch in X direction along which the nanowires extend. A cell width of the standard cell is an integral multiplication of the pitch. In a case where the standard cell is arranged to constitute the layout of a semiconductor integrated circuit device, the pads are regularly arranged in the X direction.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: January 26, 2021
    Assignee: SOCIONEXT INC.
    Inventor: Hiroyuki Shimbo
  • Patent number: 10886385
    Abstract: A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim
  • Patent number: 10886368
    Abstract: An I/O device nanosheet material stack of suspended semiconductor channel material nanosheets is provided above a semiconductor substrate. A physically exposed portion of each suspended semiconductor channel material nanosheet is thinned to increase the inter-nanosheet spacing between each vertically stacked semiconductor channel material nanosheet. An I/O device functional gate structure is formed wrapping around the thinned portion of each suspended semiconductor channel material nanosheet.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jingyun Zhang, Alexander Reznicek, Choonghyun Lee, Xin Miao
  • Patent number: 10886268
    Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. A mask pattern is formed over the sacrificial layer. The sacrificial layer and the source/drain structure are patterned by using the mask pattern as an etching mask, thereby forming openings adjacent to the patterned sacrificial layer and source/drain structure. A dielectric layer is formed in the openings. After the dielectric layer is formed, the patterned sacrificial layer is removed to form a contact opening over the patterned source/drain structure. A conductive layer is formed in the contact opening.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: January 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Chih Chieh Yeh, Tsung-Lin Lee, Yee-Chia Yeo, Meng-Hsuan Hsiao
  • Patent number: 10872983
    Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: December 22, 2020
    Inventors: Jung Gil Yang, Woo Seok Park, Dong Chan Suh, Seung Min Song, Geum Jong Bae, Dong Il Bae
  • Patent number: 10872004
    Abstract: Systems, apparatuses and methods may provide for technology that assigns a plurality of data portions associated with a workload to a plurality of cores, wherein each data portion from the plurality of data portions is only modifiable by a respective one of the plurality of cores. The technology may further pass a message between the plurality of cores to modify one or more of the data portions in response to an identification that the one or more of the data portions are unmodifiable by one or more of the plurality of cores.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: December 22, 2020
    Assignee: Intel Corporation
    Inventors: Piotr Rozen, Sagar Koorapati
  • Patent number: 10854724
    Abstract: A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of example, a first metal portion is formed within the insulating layer. In various embodiments, a first lateral surface of the first metal portion is exposed. After exposure of the first lateral surface of the first metal portion, a first graphene layer is formed on the exposed first lateral surface. In some embodiments, the first graphene layer defines a first vertical plane parallel to the exposed first lateral surface. Thereafter, in some embodiments, a first nanobar is formed on the first graphene layer, where the first nanobar extends in a first direction normal to the first vertical plane defined by the first graphene layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Wei Yang, Chi-Wen Liu, Hao-Hsiung Lin, Ling-Yen Yeh
  • Patent number: 10839902
    Abstract: A method for programming a non-volatile resistive memory including a plurality of non-volatile resistive memory cells, each memory cell being able to switch in a reversible manner between a low resistance state in which the memory cell has an electrical resistance value lower than a first resistance threshold; and a high resistance state in which the memory cell has an electrical resistance value greater than the first resistance threshold; the programming method including determining the first resistance threshold carried out periodically during the lifetime of the resistive memory.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: November 17, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Alessandro Grossi, Elisa Vianello
  • Patent number: 10818803
    Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A source/drain region is connected with a channel layer, and a gate structure extends across the channel layer. The channel layer is composed of a two-dimensional material.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Ali Razavieh
  • Patent number: 10817780
    Abstract: A circuit is disclosed that includes a first electrode, a second electrode and a plurality of quantum dot devices disposed between the first electrode and the second electrode. An impedance is coupled to the second electrode and has a value selected to conduct or block conduction of current when a coherent electron conduction band is formed by one or more of the quantum dot devices, such as with quantum dot devices in an adjacent circuit.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: October 27, 2020
    Inventor: Christopher J. Rourk
  • Patent number: 10818775
    Abstract: The method for fabricating a field-effect transistor comprises a step of producing a sacrificial gate and first and second spacers covering first, second and third parts of successive first to fifth semiconductor nanowires of a stack. The fabricating method comprises a step of forming a channel area of the transistor, which channel area is compressively stressed and distinct from the second part of the third nanowire. The channel area is connected to a source electrode of the transistor by the first part of the second nanowire, and to a drain electrode of the transistor by the third part of the second nanowire.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: October 27, 2020
    Assignees: Commissariat a l'energie atomique et aux energies alternatives, International Business Machines Corporation
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
  • Patent number: 10811509
    Abstract: A semiconductor device includes a source/drain feature disposed over a substrate. The source/drain feature includes a first nanowire, a second nanowire disposed over the first nanowire, a cladding layer disposed over the first nanowire and the second nanowire and a spacer layer extending from the first nanowire to the second nanowire. The device also includes a conductive feature disposed directly on the source/drain feature such that the conductive feature physically contacts the cladding layer and the spacer layer.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ching-Fang Huang, Carlos H. Diaz, Chih-Hao Wang, Wen-Hsing Hsieh, Ying-Keung Leung
  • Patent number: 10741664
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a plurality of first gates disposed on the quantum well stack; a plurality of pairs of spacers, each pair of spacers disposed on opposites sides of an associated first gate, wherein each spacer in a pair has a curved surface that curves away from the associated first gate; and a plurality of second gates disposed on the quantum well stack, wherein the curved surface of each spacer is adjacent to one of the second gates such that at least a portion of each second gate is shaped complementarily to the curved surface of an adjacent spacer.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: August 11, 2020
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Jeanette M. Roberts, Hubert C. George, James S. Clarke, Nicole K. Thomas
  • Patent number: 10741660
    Abstract: A method of forming a semiconductor device that includes providing a first stack of nanosheets having a first thickness and a second stack of nanosheets having a second thickness; and forming a oxide layer on the first and second stack of nanosheets. The oxide layer fills a space between said nanosheets in the first stack, and is conformally present on the nanosheets in the second stack. The method further includes forming a work function metal layer on the first and second stack of nanosheets. In some embodiments, the work function metal layer is present on only exterior surfaces of the first stack to provide a single gate structure and is conformally present about an entirety of the nanosheets in the second stack to provide a multiple gate structure.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicolas J. Loubet, Siva Kanakasabapathy, Kangguo Cheng, Jingyun Zhang
  • Patent number: 10734482
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; and one or more gates disposed on the fin. In some such embodiments, the one or more gates may include first, second, and third gates. Spacers may be disposed on the sides of the first and second gates, such that a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate. The third gate may be disposed on the fin between the first and second gates and extend between the first and second spacers.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Zachary R. Yoscovits, James S. Clarke