Field Effect Device Patents (Class 257/24)
  • Patent number: 11484262
    Abstract: A composite thread includes first and second segments joined to each other. The first segment comprises a functional segment that interacts with an environment of the thread. The second segment communicates information between the first segment and a point external to said composite thread.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: November 1, 2022
    Assignee: Trustees of Tufts College
    Inventors: Sameer Sonkusale, Pooria Mostafalu
  • Patent number: 11450760
    Abstract: Novel and useful quantum structures having a continuous fully depleted well with control gates that form two quantum dot on either side of the gate. Appropriate potentials are applied to the well and control gate to control quantum tunneling between quantum dots thereby enabling quantum operations to occur. Qubits are realized by modulating applied gate potential to control tunneling through a quantum transport path between two or more sections of the well. Complex structures with a higher number of quantum dots per continuous well and a larger number of wells can be fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. An injection device permits tunneling of a single quantum particle from a classic side to a quantum side of the device. Detection interface devices detect the presence or absence of a particle destructively or nondestructively.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: September 20, 2022
    Assignee: Equal1.Labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Patent number: 11437594
    Abstract: In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Timothy Vasen, Mark Van Dal, Gerben Doornbos, Matthias Passlack
  • Patent number: 11417751
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a plurality of first semiconductor layers and a plurality of second semiconductor layers on a substrate, and the first semiconductor layers and the second semiconductor layers are alternately stacked. The method also includes forming a dummy gate structure over the first semiconductor layers and the second semiconductor layers. The method further includes removing a portion of the first semiconductor layers and second semiconductor layers to form a trench, and removing the second semiconductor layers to form a recess between two adjacent first semiconductor layers. The method includes forming a dummy dielectric layer in the recess, and removing a portion of the dummy dielectric layer to form a cavity. The method also includes forming an inner spacer layer in the cavity.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: August 16, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tze-Chung Lin, Han-Yu Lin, Li-Te Lin, Pinyen Lin
  • Patent number: 11417776
    Abstract: A semiconductor device, including a silicon on insulator (SOI) substrate is disclosed. The device may include gate structures formed on the SOI substrate and being spaced apart from each other in a horizontal direction, and a plurality of channels spaced apart from each other in a vertical direction. Each of the channels may extend through each of the gate structures in the horizontal direction. The device may include a seed layer and a source/drain region. The source/drain region may be connected to the channels, and each sidewall of the source/drain region in the horizontal direction may have a concave-convex shape. The device may include a protruding portion of the source/drain region formed between the gate structures that protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: August 16, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sujin Jung, Junbeom Park, Kihwan Kim, Sunguk Jang, Youngdae Cho
  • Patent number: 11411535
    Abstract: A device is disclosed that includes an insulating layer, a first electrode, a second electrode, and a bottom electrode. The insulating layer is disposed on a first surface of a substrate. The first electrode and the second electrode are disposed on a first surface of the insulating layer. The first electrode receives an input signal, and the second electrode outputs, in response to the input signal, an output signal. The bottom electrode is disposed on a second surface, opposite to the first surface, of the substrate and receives an operating voltage to modify a frequency of the output signal.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: August 9, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jenn-Gwo Hwu, Ting-Hao Hsu
  • Patent number: 11398478
    Abstract: Semiconductor nanowire devices having (111)-plane channel sidewalls and methods of fabricating semiconductor nanowire devices having (111)-plane channel sidewalls are described. For example, an integrated circuit structure includes a first semiconductor device including a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising a discrete channel region having <111> lateral sidewalls along a <110> carrier transport direction. The integrated circuit structure also includes a second semiconductor device including a semiconductor fin disposed above the substrate, the semiconductor fin having a channel region with a top and side surfaces, the channel region having <111> lateral sidewalls along a <110> carrier transport direction.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: July 26, 2022
    Assignee: Intel Corporation
    Inventors: Cory E. Weber, Harold W. Kennel, Willy Rachmady, Gilbert Dewey
  • Patent number: 11362180
    Abstract: A semiconductor device includes a substrate, a channel stack, source/drain contacts, and a gate electrode. The channel stack is over the substrate and includes a 2D channel layer and a barrier layer. An energy band gap of the barrier layer is greater than an energy band gap of the 2D channel layer. The source/drain contacts are in contact with the channel stack. The gate electrode is above the substrate.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: June 14, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Yun-Yuan Wang, Chih-Hsiang Hsiao, I-Chih Ni, Chih-I Wu
  • Patent number: 11362200
    Abstract: A field-effect transistor (FET) includes a fin, an insulator region, and at least one gate. The fin has a doped first region, a doped second region, and an interior region between the first region and the second region. The interior region is undoped or more lightly doped than the first and second regions. The interior region of the fin is formed as a superlattice of layers of first and second materials alternating vertically. The insulator layer extends around the interior region. The gate is formed on at least a portion of the insulator region. The insulator layer and the gate are configured to generate an inhomogeneous electrostatic potential within the interior region, the inhomogeneous electrostatic potential cooperating with physical properties of the superlattice to cause scattering of charge carriers sufficient to change a quantum property of such charge carriers to change the ability of the charge carriers to move between the first and second materials.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: June 14, 2022
    Assignee: Purdue Research Foundation
    Inventors: Tillmann C. Kubis, James Charles
  • Patent number: 11362183
    Abstract: A semiconductor device includes a substrate; and a fin protruding from the substrate. The fin includes a first material and a second material. The fin includes a lower section, a middle section, and an upper section. The middle section has a smaller width at a middle portion than a width at lower and upper portions of the middle section. A concentration of the second material gradually decreases from the middle portion in upward and downward directions.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: June 14, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sungmin Kim
  • Patent number: 11302777
    Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: April 12, 2022
    Assignee: Sony Group Corporation
    Inventors: Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong, Rafael Rios, Abhijit Jayant Pethe, Willy Rachmady
  • Patent number: 11302580
    Abstract: According to one example, a method includes performing a Chemical Mechanical Polishing (CMP) process on a semiconductor workpiece that includes a nanosheet region, the nanosheet region having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes stopping the CMP process when the first type of semiconductor material is covered by the second type of semiconductor material, patterning the nanosheet region to form nanosheet stacks, forming an isolation structure around the nanosheet stacks, removing a top layer of the second type of semiconductor material from the nanosheet stacks, recessing the isolation structure, and forming a gate structure over the nanosheet stacks.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Ting Lan, Kuan-Ting Pan, Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 11292938
    Abstract: A process for chemical mechanical polishing a substrate containing cobalt, zirconium oxide, poly-silicon and silicon dioxide, wherein the cobalt, zirconium, and poly-silicon removal rates are selective over silicon dioxide. The chemical mechanical polishing composition includes water, a benzyltrialkyl quaternary ammonium compound, cobalt chelating agent, corrosion inhibitor, colloidal silica abrasive, optionally a biocide and optionally a pH adjusting agent, and a pH greater than 7, and the chemical mechanical polishing compositions are free of oxidizing agents.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: April 5, 2022
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Murali Ganth Theivanayagam, Matthew Richard Van Hanehem, Yi Guo
  • Patent number: 11296237
    Abstract: A microelectronic device includes a gated graphene component over a semiconductor material. The gated graphene component includes a graphitic layer having at least one layer of graphene. The graphitic layer has a channel region, a first connection and a second connection make electrical connections to the graphitic layer adjacent to the channel region. The graphitic layer is isolated from the semiconductor material. A backgate region having a first conductivity type is disposed in the semiconductor material under the channel region. A first contact field region and a second contact field region are disposed in the semiconductor material under the first connection and the second connection, respectively. At least one of the first contact field region and the second contact field region has a second, opposite, conductivity type. A method of forming the gated graphene component in the microelectronic device with a transistor is disclosed.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: April 5, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Archana Venugopal, Luigi Colombo, Arup Polley
  • Patent number: 11288586
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a base and a fin extending away from the base and including a quantum well layer. The device may further include a first gate disposed on a first side of the fin and a second gate disposed on a second side of the fin, different from the first side. Providing gates on different sides of a fin advantageously allows increasing the number of quantum dots which may be independently formed and manipulated in the fin. The quantum dots formed in such a device may be constrained in the x-direction by the one or more gates, in the y-direction by the fin, and in the z-direction by the quantum well layer, as discussed in detail herein. Methods for fabricating such devices are also disclosed.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Hubert C. George, Jeanette M. Roberts, Nicole K. Thomas, James S. Clarke
  • Patent number: 11289477
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a fin structure formed over a substrate and an isolation structure formed around the fin structure. The semiconductor structure further includes a nanowire structure formed over the fin structure and a gate structure formed around the nanowire structure. In addition, a bottommost of the nanowire structure is lower than a top surface of the isolation structure.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Blandine Duriez, Georgios Vellianitis
  • Patent number: 11245011
    Abstract: The current disclosure describes a new vertical tunnel field-effect transistor (TFET). The TFET includes a source layer over a substrate. A first channel layer is formed over the source layer. A drain layer is stacked over the first channel layer with a second channel layer stacked therebetween. The drain layer and the second channel layer overlap a first surface portion of the first channel layer. A gate structure is positioned over the channel layer by a second surface portion of the channel layer and contacts a sidewall of the second channel layer.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: February 8, 2022
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Jiun-Yun Li, Pao-Chuan Shih, Wei-Chih Hou
  • Patent number: 11239085
    Abstract: A device includes a non-insulator structure, a first dielectric layer, and a first conductive feature. The first dielectric layer is over the non-insulator structure. The first conductive feature is in the first dielectric layer and includes carbon nano-tubes. The first catalyst layer is between the first conductive feature and the non-insulator structure. A top of the first catalyst layer is lower than a top of the first conductive feature.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: You-Hua Chou, Kuo-Sheng Chuang
  • Patent number: 11201283
    Abstract: A method of forming a memory device that includes depositing a first dielectric material within a trench of composed of a second dielectric material; positioning a nanotube within the trench using chemical recognition to the first dielectric material; depositing a dielectric for cation transportation within the trench on the nanotube; and forming a second electrode on the dielectric for cation transportation, wherein the second electrode is composed of a metal.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: December 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Jianshi Tang, Ning Li
  • Patent number: 11170948
    Abstract: The present invention relates to a method for preparing an electrode comprising a metal substrate, vertically aligned carbon nanotubes and a metal oxide deposited over the entire length of said vertically aligned carbon nanotubes, said method comprising the following consecutive steps: (a) synthesizing, on a metal substrate, a mat of vertically aligned carbon nanotubes; and (b) depositing a metal oxide matrix over the entire height of said vertically aligned carbon nanotube mat via spontaneous reduction at a temperature not exceeding 40° C. The present invention also relates to said electrode and to the uses thereof.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: November 9, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Mathieu Pinault, Fouad Ghamouss, Francois Tran Van, Emeline Charon, Baptiste Pibaleau
  • Patent number: 11158730
    Abstract: A method of forming a field effect transistor (FET) includes performing an oxidation on a nanosheet structure having alternating sheets of silicon and silicon germanium. An oxide etch is performed to remove portions of the sheets of silicon germanium. Other embodiments are also described herein.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: October 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 11152516
    Abstract: There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: October 19, 2021
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 11152346
    Abstract: A capacitive element using VNW FETs is provided. First and second components each constituting a transistor are arranged in an X direction. From the first component, a first gate interconnect extends away from the second component, and a first top interconnect and a first bottom interconnect extend toward the second component. From the second component, a second gate interconnect extends toward the first component, and a second top interconnect and a second bottom interconnect extend away from the first component. The first top interconnect, the first bottom interconnect, and the second gate interconnect are connected.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: October 19, 2021
    Assignee: SOCIONEXT INC.
    Inventor: Isaya Sobue
  • Patent number: 11145753
    Abstract: The present disclosure discloses a ballistic transport semiconductor device based on nano array and a manufacturing method thereof. The ballistic transport semiconductor device based on nano array comprises a conducting substrate, more than one semiconductor nano bump portion is arranged on a first surface of the conducting substrate, a top end of the semiconductor nano bump portion is electrically connected with a first electrode, a second surface of the conducting substrate is electrically connected with a second electrode, the second surface and the first surface are arranged back to back, and the height of the semiconductor nano bump portion is less than or equal to a mean free path of a carrier. The carrier is not influenced by various scattering mechanisms in a transporting procedure by virtue of the existence of ballistic transport characteristics, thereby obtaining a semiconductor device having advantages of lower on resistance, less working power consumption.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: October 12, 2021
    Assignee: SUZHOU INSTITUTE OF NANO-TECH AND NANO-BIONICS (SINANO), CHINESE ACADEMY OF SCIENCES
    Inventors: Guohao Yu, Fu Chen, Wenxin Tang, Xiaodong Zhang, Yong Cai, Baoshun Zhang
  • Patent number: 11139299
    Abstract: Embodiments of the present invention provide improved methods and structures for fabrication of capacitor-less DRAM devices, sometimes referred to as ZRAM devices. A channel is formed in a fin-type field effect transistor (finFET) that is comprised of a finned channel portion and a convex channel portion. The finned channel portion may be comprised of a first semiconductor material and the convex channel portion may be comprised of a second, different semiconductor material. In embodiments, a metal gate is disposed around the elongated surface of the channel region, but is not disposed on the short surface of the channel region. A first spacer is disposed adjacent to the gate and in direct physical contact with the short surface of the channel region, and a second spacer is disposed adjacent to the first spacer.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: October 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ravikumar Ramachandran, Reinaldo Ariel Vega
  • Patent number: 11133384
    Abstract: A semiconductor transistor device includes an emitter region that includes a plurality of metal quantum wires and is connected to an emitter terminal, a base region that includes a plurality of metal quantum wires and is connected to a base terminal, a collector region comprising a plurality of metal quantum wires and is connected to a collector terminal, an emitter barrier region between the emitter region and the base region, and a collector barrier region between the collector region and the base region.
    Type: Grant
    Filed: April 19, 2020
    Date of Patent: September 28, 2021
    Inventor: Koucheng Wu
  • Patent number: 11133403
    Abstract: A device includes a substrate, a first doping portion, a second doping portion, a channel, a semiconductor film, a high-k layer, and a gate. The first doping portion and the second doping portion are over the substrate. The channel is over the substrate and between the first doping portion and the second doping portion. The semiconductor film is around the channel. The high-k layer is around the semiconductor film. The gate is over the high-k layer.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Sheng Chen, Cheng-Hsien Wu, Chih-Chieh Yeh
  • Patent number: 11127820
    Abstract: A quantum well field-effect transistor (QWFET) includes a barrier layer, a quantum well layer, and a spacer layer. The quantum well layer is on the barrier layer. The barrier layer and the spacer layer comprise aluminum indium antimonide that is undoped. The quantum well layer comprises indium antimonide. The spacer layer is on the quantum well layer. The quantum well layer and the spacer layer are between a source contact and a drain contact. A gate contact is on a dielectric layer, which is on the spacer layer. By providing the barrier layer and the spacer layer as undoped layers, a performance of the QWFET may be improved.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: September 21, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Michael James Manfra, Candice Fanny Thomas
  • Patent number: 11121215
    Abstract: A technique relates to a semiconductor device. A stack includes two or more nanowires separated by a high-k dielectric material, the high-k dielectric material being formed on at least a center portion of the two or more nanowires in the stack. A separation space between the two or more nanowires is less than two times a thickness of the high-k dielectric material formed on a side wall of the two or more nanowires. A source or a drain formed on sides of the stack.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: September 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juntao Li, Kangguo Cheng, Chen Zhang, Xin Miao
  • Patent number: 11114435
    Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to FinFET transistors. In one aspect, at least three fins are arranged to extend in parallel in a first direction and are laterally separated from each other in a second direction by shallow trench isolation structures having a first fin spacing, where at least a portion of each fin protrudes out from a substrate. At least a portion of each of a first fin and a second fin of the at least three fins vertically protrude to a level higher than an upper surface of the shallow trench isolation structures. A third fin is formed laterally between the first fin and the second fin in the second direction, where the third fin has a non-protruding region which extends vertically to a level below or equal to the upper surface of the shallow trench isolation structures.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 7, 2021
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Geert Hellings, Roman Boschke, Dimitri Linten, Naoto Horiguchi
  • Patent number: 11107932
    Abstract: There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: August 31, 2021
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 11101371
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay Chuang, Yi-Ren Chen, Chi-Wen Liu, Chao-Hsiung Wang, Ming Zhu
  • Patent number: 11094811
    Abstract: A semiconductor device includes a substrate, a channel layer, an insulating layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The channel layer over the substrate and includes two dimensional (2D) material. The insulating layer is on the channel layer. The source/drain contacts are over the channel layer. The gate dielectric layer is over the insulating layer and the channel layer. The gate electrode is over the gate dielectric layer and between the source/drain contacts.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tse-An Chen, Lain-Jong Li, Wen-Hao Chang, Chien-Chih Tseng
  • Patent number: 11088032
    Abstract: In embodiments of the present disclosure, an ambient medium of a two-dimensional semiconductor is doped or an ambient medium of a semiconductor is locally filled with a solid material, to form a filled region, and an electronic device based on the two-dimensional semiconductor is implemented by means of a doping effect of the doped region or the filled region on a characteristic of the two-dimensional semiconductor. In the embodiments of the present disclosure, doping the two-dimensional semiconductor is not directly processing the two-dimensional semiconductor. Therefore, damage caused to the two-dimensional semiconductor in a doping process and device performance deterioration caused accordingly can be effectively reduced, and stability of device performance after doping is improved.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: August 10, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Wen Yang, Riqing Zhang, Yu Xia
  • Patent number: 11081589
    Abstract: A semiconductor device includes a substrate, an N-type bottom vertical gate-all-around (VGAA) transistor, a P-type bottom VGAA transistor, and a top VGAA transistor. The N-type bottom vertical gate-all-around (VGAA) transistor is over the semiconductor substrate and comprising a first nanowire made of InAs. The P-type bottom VGAA transistor is over the semiconductor substrate and comprising a second nanowire made of Ge. The top VGAA transistor is over the N-type bottom VGAA transistor, in which the top VGAA transistor includes a third nanowire in contact with the N-type bottom VGAA transistor, a fourth nanowire on and in contact with the third nanowire, and a bit line wrapping the fourth nanowire.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Mark Van Dal
  • Patent number: 11081567
    Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: August 3, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jingyun Zhang, Choonghyun Lee, Chun Wing Yeung, Robin Hsin Kuo Chao, Heng Wu
  • Patent number: 11075107
    Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun Hao Liao, Chu Fu Chen, Chun-Wei Hsu, Chia-Cheng Pao
  • Patent number: 11069775
    Abstract: Field effect transistors and methods of forming the same include forming a stack of nanosheets of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: July 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 11069808
    Abstract: A negative capacitance field effect transistor (NCFET) and a manufacturing method thereof. The NCFET includes: a substrate structure, including a MOS region; a gate insulating dielectric structure, covering the MOS region; and a metal gate stack layer, covering the gate insulating dielectric structure. The gate insulating dielectric structure includes an interface oxide layer, a HfO2 layer, a doping material layer, and a ferroelectric material layer, which are sequentially stacked along a direction away from the substrate structure. A ferroelectric material in the ferroelectric material layer is HfxA1-xO2, A represents a doping element, and 0.1?x?0.9. A material forming the doping material layer is AyOz or A, and a ratio of y/z is equal to 1/2, 2/3, 2/5 or 1/1. Ferroelectric characteristics, material stability, and material reliability of the NCFET are improved by increasing domain polarity of the ferroelectric material.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 20, 2021
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Qingzhu Zhang, Zhaohao Zhang, Tianchun Ye
  • Patent number: 11060997
    Abstract: A biosensor comprising a substrate, a gate electrode provided on the substrate, an insulating layer provided on the gate electrode, a source electrode and a drain electrode, provided on the insulating layer, respectively, an n-type channel provided between the source electrode and the drain electrode, and a quantum dot layer provided on the n-type channel and provided so as to have electronic transition energy capable of resonating with vibration energy of a target biological material.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: July 13, 2021
    Inventors: Kwang Seob Jeong, Hang Beum Shin, Young Do Jeong, Bit Na Yoon, Dong Sun Choi, Ju Yeon Jeong
  • Patent number: 11056647
    Abstract: A carbon nanotube (CNT) single ion memory (or memory device) may include a mobile ion conductor with a CNT on one side and an ion drift electrode (IDE) on the other side. The mobile ion conductor may be used as a transport medium to shuttle ions to and from the CNT and the IDE. The IDE may move the ions towards or away from the CNT.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: July 6, 2021
    Assignee: The Aerospace Corporation
    Inventors: Adam W. Bushmaker, Don Walker
  • Patent number: 11031239
    Abstract: Devices comprising germanium nanosheets are described herein. Methods of forming such germanium nanosheets and devices including such germanium nanosheets are also described.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: June 8, 2021
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventor: Hung-Hsiang Cheng
  • Patent number: 11024746
    Abstract: Gate all-around devices are disclosed in which an angled channel comprising a semiconducting nanostructure is located between a source and a drain. The angled channel has an axis that is oriented at an angle to the top surface of the substrate at an angle in a range of about 1° to less than about 90°. The gate all-around device is intended to meet design and performance criteria for the 7 nm technology generation.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: June 1, 2021
    Assignee: Applied Materrials, Inc.
    Inventors: Russell Chin Yee Teo, Benjamin Colombeau
  • Patent number: 11005046
    Abstract: In order to obtain a carbon nanotube array including no m-CNTs through simple steps using a mechanism that is different from thermocapillary flow, there are provided a process for producing a carbon nanotube array including (A) a step of preparing a carbon nanotube array in which m-CNTs and s-CNTs are horizontally aligned; (B) a step of forming an organic layer on the carbon nanotube array; (C) a step of applying voltage to the carbon nanotube array in a long axis direction of the carbon nanotubes constituting the carbon nanotube array in the air; and (D) a step of removing the organic layer, and a carbon nanotube array obtained by the process.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: May 11, 2021
    Assignees: THE UNIVERSITY OF TOKYO, DENSO CORPORATION
    Inventors: Shigeo Maruyama, Shohei Chiashi, Keigo Ohtsuka, Taiki Inoue
  • Patent number: 10988688
    Abstract: A quantum dot manufacturing method comprises (a) dispersing, in a solvent, nano-seed particles whose crystal planes are exposed, and (b) growing semiconductor layers on the exposed crystal planes of the nano-seed particles in the solvent.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: April 27, 2021
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Takuya Kazama, Wataru Tamura, Yasuyuki Miyake
  • Patent number: 10991627
    Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: April 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Chia Tai Lin, Chao-Cheng Chen
  • Patent number: 10991694
    Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: April 27, 2021
    Inventors: Sung-Dae Suk, Jongho Lee, Geumjong Bae
  • Patent number: 10985070
    Abstract: A method for forming a nanodevice sensing chip includes forming nanodevices having a sensing region capable of producing localized Joule heating. Individual nanodevice is electrical-biased in a chemical vapor deposition (CVD) system or an atomic layer deposition (ALD) system enabling the sensing region of the nanodevice produce localized Joule heating and depositing sensing material only on this sensing region. A sensing chip is formed via nanodevices with sensing region of each nanodevice deposited various materials separately. The sensing chip is also functioned under device Joule self-heating to interact and detect the specific molecules.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: April 20, 2021
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Ru-Zheng Lin, Jeng-Tzong Sheu
  • Patent number: 10957605
    Abstract: The present invention provides VFET device designs for top contact resistance measurement. In one aspect, a method of forming a VFET test structure includes: etching fins in a substrate (for active and sensing devices); forming bottom source/drains at a base of the fins; forming a STI region that isolates the bottom source/drains of the active device from that of the sensing device; forming a gate surrounding each of the fins; forming top source/drains over the gate, wherein the top source/drains of the active device and that of the sensing device are merged; and forming contacts to i) the bottom source/drains of the active device, ii) the top source/drains of the active device, and iii) the bottom source/drains of the sensing device. A test structure formed by the method as well as techniques for use thereof for measuring contact resistance are also provided.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Zuoguang Liu
  • Patent number: 10934163
    Abstract: Novel and useful quantum structures having a continuous well with control gates that control a local depletion region to form quantum dots. Local depleted well tunneling is used to control quantum operations to implement quantum computing circuits. Qubits are realized by modulating gate potential to control tunneling through local depleted region between two or more sections of the well. Complex structures with a higher number of qdots per continuous well and a larger number of wells are fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. Combining a number of elementary quantum structure, a quantum computing machine is realized. An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 2, 2021
    Assignee: Equal1.Labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker