Field Effect Device Patents (Class 257/24)
  • Patent number: 10811509
    Abstract: A semiconductor device includes a source/drain feature disposed over a substrate. The source/drain feature includes a first nanowire, a second nanowire disposed over the first nanowire, a cladding layer disposed over the first nanowire and the second nanowire and a spacer layer extending from the first nanowire to the second nanowire. The device also includes a conductive feature disposed directly on the source/drain feature such that the conductive feature physically contacts the cladding layer and the spacer layer.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ching-Fang Huang, Carlos H. Diaz, Chih-Hao Wang, Wen-Hsing Hsieh, Ying-Keung Leung
  • Patent number: 10741664
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a plurality of first gates disposed on the quantum well stack; a plurality of pairs of spacers, each pair of spacers disposed on opposites sides of an associated first gate, wherein each spacer in a pair has a curved surface that curves away from the associated first gate; and a plurality of second gates disposed on the quantum well stack, wherein the curved surface of each spacer is adjacent to one of the second gates such that at least a portion of each second gate is shaped complementarily to the curved surface of an adjacent spacer.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: August 11, 2020
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Jeanette M. Roberts, Hubert C. George, James S. Clarke, Nicole K. Thomas
  • Patent number: 10741660
    Abstract: A method of forming a semiconductor device that includes providing a first stack of nanosheets having a first thickness and a second stack of nanosheets having a second thickness; and forming a oxide layer on the first and second stack of nanosheets. The oxide layer fills a space between said nanosheets in the first stack, and is conformally present on the nanosheets in the second stack. The method further includes forming a work function metal layer on the first and second stack of nanosheets. In some embodiments, the work function metal layer is present on only exterior surfaces of the first stack to provide a single gate structure and is conformally present about an entirety of the nanosheets in the second stack to provide a multiple gate structure.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicolas J. Loubet, Siva Kanakasabapathy, Kangguo Cheng, Jingyun Zhang
  • Patent number: 10734482
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; and one or more gates disposed on the fin. In some such embodiments, the one or more gates may include first, second, and third gates. Spacers may be disposed on the sides of the first and second gates, such that a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate. The third gate may be disposed on the fin between the first and second gates and extend between the first and second spacers.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Zachary R. Yoscovits, James S. Clarke
  • Patent number: 10720521
    Abstract: An enhancement mode GaN transistor is provided, which includes a GaN layer, a quantum well structure, a gate, a source a drain and a first barrier layer. The quantum well structure is disposed on the upper surface of the GaN layer. The gate is disposed on the quantum well structure. The source is disposed on one end of the upper surface of the GaN layer. The drain is disposed on the other end of the upper surface of the GaN layer. The first barrier layer is disposed on the upper surface of the GaN layer and extends to the lateral surfaces of the quantum well structure.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: July 21, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jung-Tse Tsai, Po-Chun Yeh, Chien-Hua Hsu, Po-Tsung Tu
  • Patent number: 10714595
    Abstract: Example embodiments relate to germanium nanowire fabrication. One embodiment includes a method of forming a semiconductor device that includes at least one Ge nanowire. The method includes providing a semiconductor structure that includes at least one, the at least one fin including a stack of at least one Ge layer alternative with SiGe layers. The method also includes at least partially oxidizing the SiGe layer into SiGeOx. Further, the method includes capping the fin with a dielectric material. In addition, the method includes annealing. Still further, the method includes selectively removing the dielectric material and the SiGeOx.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: July 14, 2020
    Assignee: IMEC VZW
    Inventors: Liesbeth Witters, Kurt Wostyn
  • Patent number: 10707354
    Abstract: In a standard cell including nanowire FETs, pads connected to nanowires are arranged at a predetermined pitch in X direction along which the nanowires extend. A cell width of the standard cell is an integral multiplication of the pitch. In a case where the standard cell is arranged to constitute the layout of a semiconductor integrated circuit device, the pads are regularly arranged in the X direction.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: July 7, 2020
    Assignee: SOCIONEXT INC.
    Inventor: Hiroyuki Shimbo
  • Patent number: 10686009
    Abstract: A method for forming three-dimensional magnetic memory arrays by forming crystalized silicon structures from amorphous structures in the magnetic memory array, wherein the temperature needed to crystalize the amorphous silicon is lower than the temperature budget of the memory element so as to avoid damage to the memory element. An amorphous silicon is deposited, followed by a layer of Ti or Co. An annealing process is then performed which causes the Ti or Co to form TiSi2 or CoSi2 and also causes the underlying amorphous silicon to crystallize.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: June 16, 2020
    Assignee: SPIN MEMORY, INC.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Marcin Gajek, Michail Tzoufras, Kadriye Deniz Bozdag, Eric Michael Ryan, Satoru Araki, Andrew J. Walker
  • Patent number: 10665770
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a gate above the fin; and a material on side faces of the fin; wherein the fin has a width between its side faces, and the fin is strained in the direction of the width.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Kanwaljit Singh, Patrick H. Keys, Roman Caudillo, Hubert C. George, Zachary R. Yoscovits, Nicole K. Thomas, James S. Clarke, Roza Kotlyar, Payam Amin, Jeanette M. Roberts
  • Patent number: 10658419
    Abstract: A back-illuminated single-photon avalanche diode (SPAD) image sensor includes a sensor wafer stacked vertically over a circuit wafer. The sensor wafer includes one or more SPAD regions, with each SPAD region including an anode gradient layer, a cathode region positioned adjacent to a front surface of the SPAD region, and an anode avalanche layer positioned over the cathode region. Each SPAD region is connected to a voltage supply and an output circuit in the circuit wafer through inter-wafer connectors. Deep trench isolation elements are used to provide electrical and optical isolation between SPAD regions.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: May 19, 2020
    Assignee: Apple Inc.
    Inventors: Shingo Mandai, Cristiano L. Niclass, Nobuhiro Karasawa, Xiaofeng Fan, Arnaud Laflaquiere, Gennadiy A. Agranov
  • Patent number: 10651279
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphed barrier layer. The present disclosure provides a method of forming a graphed barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphed barrier layers can be selected by varying the thickness of the amorphous carbon layer.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Yi Yang, Ching-Fu Yeh, Ming-Han Lee, Shau-Lin Shue
  • Patent number: 10651325
    Abstract: A device includes a first semiconductor layer; a portion of a second semiconductor layer disposed on the first semiconductor layer; and a third semiconductor layer including a first region disposed on the portion of the second semiconductor layer and a second region disposed on the first semiconductor layer. A thickness of the first region is less than a predefined thickness. The device also includes an etch stop layer disposed on the third semiconductor layer; a plurality of distinct portions of a fourth semiconductor layer disposed on the etch stop layer and exposing one or more distinct portions of the etch stop layer over the portion of the second semiconductor layer; and a plurality of distinct portions of a superconducting layer disposed on the plurality of distinct portions of the fourth semiconductor layer and the exposed one or more distinct portions of the etch stop layer.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 12, 2020
    Assignee: PSIQUANTUM CORP.
    Inventors: Faraz Najafi, Mark Thompson, Damien Bonneau, Joaquin Matres Abril
  • Patent number: 10651293
    Abstract: A vertical transistor device includes a vertically oriented channel semiconductor structure, a bottom source/drain (S/D) region, a top source/drain (S/D) region, and a gate structure positioned around the vertically oriented channel semiconductor structure, above the bottom source/drain (S/D) region, and below the top source/drain (S/D) region. The gate structure includes a gate electrode and a gate insulation layer positioned between the gate electrode and at least a portion of the vertically oriented channel semiconductor structure. A top spacer is positioned between the gate electrode and at least a portion of the top source/drain (S/D) region, a bottom spacer is positioned between the gate electrode and at least a portion of the bottom source/drain (S/D) region, and a gate cap is positioned around an outer perimeter surface of the gate structure, wherein the top spacer, the bottom spacer, and the gate cap all include a same insulating material.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: John H. Zhang
  • Patent number: 10644150
    Abstract: A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: May 5, 2020
    Assignee: International Business Machines Corporation
    Inventors: Xin Miao, Chen Zhang, Kangguo Cheng, Wenyu Xu
  • Patent number: 10636972
    Abstract: A method for producing the photoelectric conversion element includes, in carbon nanotubes including semiconducting carbon nanotubes having different chiralities from each other and metallic carbon nanotubes, changing a chirality distribution in the semiconducting carbon nanotubes, separating the carbon nanotubes into the semiconducting carbon nanotubes and the metallic carbon nanotubes after changing the chirality distribution, covering the semiconducting carbon nanotubes with a polymer after performing separating, and forming a photoelectric conversion film including the semiconducting carbon nanotubes between a pair of electrodes after performing covering with the polymer.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: April 28, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kazunori Hayashida, Nozomu Matsukawa, Katsuya Nozawa
  • Patent number: 10622181
    Abstract: Nanoscale field-emission devices are presented, wherein the devices include at least a pair of electrodes separated by a gap through which field emission of electrons from one electrode to the other occurs. The gap is dimensioned such that only a low voltage is required to induce field emission. As a result, the emitted electrons energy that is below the ionization potential of the gas or gasses that reside within the gap. In some embodiments, the gap is small enough that the distance between the electrodes is shorter than the mean-free path of electrons in air at atmospheric pressure. As a result, the field-emission devices do not require a vacuum environment for operation.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: April 14, 2020
    Assignee: California Institute of Technology
    Inventors: Axel Scherer, William M. Jones, Danil M. Lukin, Sameer Walavalkar, Chieh-feng Chang
  • Patent number: 10622257
    Abstract: The present invention provides VFET device designs for top contact resistance measurement. In one aspect, a method of forming a VFET test structure includes: etching fins in a substrate (for active and sensing devices); forming bottom source/drains at a base of the fins; forming a STI region that isolates the bottom source/drains of the active device from that of the sensing device; forming a gate surrounding each of the fins; forming top source/drains over the gate, wherein the top source/drains of the active device and that of the sensing device are merged; and forming contacts to i) the bottom source/drains of the active device, ii) the top source/drains of the active device, and iii) the bottom source/drains of the sensing device. A test structure formed by the method as well as techniques for use thereof for measuring contact resistance are also provided.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Zuoguang Liu
  • Patent number: 10615256
    Abstract: Embodiments are directed to a method of fabricating a semiconductor device. A non-limiting example of the method includes performing fabrication operations to form a nanosheet field effect transistor device on a substrate. The fabrication operations include, forming a channel stack over the substrate, wherein the channel stack include stacked and spaced apart channel nanosheets. A metal gate is formed adjacent to end regions of the channel stack and around and between the stacked and spaced apart channel nanosheets. A permanent dummy gate is formed above the channel stack.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10615258
    Abstract: A semiconductor structure includes a nanosheet stack disposed on a base. The nanosheet stack includes one or more first nanosheet layers and one or more second nanosheet layers. Each of the one or more first nanosheet layers includes a first material and each of the one or more second nanosheet layers includes a second material different from the first material. Each of the one or more first nanosheet layers further includes outer portions of a third material converted from the first material. The outer portions are inner spacers.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Xin Miao, Kangguo Cheng, Chen Zhang, Wenyu Xu
  • Patent number: 10608109
    Abstract: A stacked vertical field effect transistor that has enhanced drive current is provided. The stacked vertical field effect transistor includes a lower functional gate structure located adjacent sidewall surfaces of a lower channel portion of a semiconductor channel material pillar. An upper functional gate structure is located above the lower functional gate structure and adjacent sidewall surfaces of an upper channel portion of the semiconductor channel material pillar. A bottom source/drain region is located beneath the lower functional gate structure, a middle source/drain region is located between the lower functional gate structure and the upper functional gate structure, and a top source/drain region is located above the upper functional gate structure.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Alexander Reznicek
  • Patent number: 10607840
    Abstract: A semiconductor device includes: a substrate; a p-type GaN layer that is formed above the substrate, and includes GaN containing p-type impurities; and a Ti film formed on a surface of the p-type GaN layer. The Ti film includes a Ti film containing no nitrogen and a nitrogen-containing Ti film that is less chemically active than such Ti film. The nitrogen-containing Ti film continuously surrounds an outer periphery of the Ti film containing no nitrogen in a planar view.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: March 31, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takeshi Harada, Koji Utaka
  • Patent number: 10600885
    Abstract: A method of forming a fin field effect transistor device is provided. The method includes forming a plurality of vertical fins on a substrate. The method further includes forming a bottom source/drain layer adjacent to the plurality of vertical fins, and growing a doped layer on the bottom source/drain layer and sidewalls of the plurality of vertical fins. The method further includes forming a dummy gate liner on the doped layer and the bottom source/drain layer, and forming a dummy gate fill on the dummy gate liner. The method further includes forming a protective cap layer on the dummy gate fill, and removing a portion of the protective cap layer to expose a top surface of the plurality of vertical fins.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Choonghyun Lee, Shogo Mochizuki
  • Patent number: 10586848
    Abstract: Transistor devices having an indium-containing ternary or greater III-V compound active channels, and processes for the fabrication of the same, may be formed that enables improved carrier mobility when fabricating fin shaped active channels, such as those used in tri-gate or gate all around (GAA) devices. In one embodiment, an indium-containing ternary or greater III-V compound may be deposited in narrow trenches on a reconstructed upper surface of a sub-structure, which may result in a fin that has indium rich side surfaces and an indium rich bottom surface. These indium rich surfaces will abut a gate oxide of a transistor and may result in high electron mobility and an improved switching speed relative to conventional homogeneous compositions of indium-containing ternary or greater III-V compound active channels.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: March 10, 2020
    Assignee: Intel Corporation
    Inventors: Chandra S. Mohapatra, Anand S. Murthy, Glenn A. Glass, Matthew V. Metz, Willy Rachmady, Gilbert Dewey, Tahir Ghani, Jack T. Kavalieros
  • Patent number: 10586657
    Abstract: Described herein is a device that includes an alkyl ammonium metal halide perovskite layer, and a nanostructured semiconductor layer in physical contact with the alkyl ammonium metal halide perovskite layer. The alkyl ammonium metal halide perovskite layer may include methyl ammonium cations. The alkyl ammonium metal halide perovskite layer may include anions of at least one of chlorine, bromine, astatine, and/or iodine. The alkyl ammonium metal halide perovskite layer may include cations of a metal in a 2+ valence state. The metal may include at least one of lead, tin, and/or germanium.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: March 10, 2020
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Jeffrey Lee Blackburn, Kai Zhu, Mengjin Yang, Anne-Marie Dowgiallo, Rachelle Rosemarie Ihly
  • Patent number: 10573714
    Abstract: Field effect transistors and methods of forming the same include forming a stack of nanosheets of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 10573561
    Abstract: A method of fabricating a stacked semiconductor device includes forming nanosheet stacks including silicon layers and silicon germanium layers on a substrate. The method includes growing a first epitaxial layer on a source and drain and depositing an interlayer dielectric on the first epitaxial layer. The method includes etching the interlayer dielectric to expose the first epitaxial layer. The method includes etching a portion of the first epitaxial layer and growing a second epitaxial layer on the first epitaxial layer and etching the interlayer dielectric and depositing a first liner in a recess left by the etching, forming a pFET. The method includes etching a portion of the first liner and removing the second epitaxial layer leaving a portion of the first epitaxial layer exposed and depositing a second insulator layer on the first epitaxial layer, forming an nFET. The pFET and nFET are disposed adjacent to one another vertically.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: February 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Heng Wu, Peng Xu
  • Patent number: 10553730
    Abstract: A broadband multi-purpose optical device includes a semiconductor layer having a light absorption characteristic, a first active layer having a light absorption band different from a light absorption band of the semiconductor layer, a first two-dimensional (2D) material layer adjacent to the first active layer, and a first interfacial layer configured to control a pinning potential of the semiconductor layer and the first active layer. The broadband multi-purpose optical device may further include at least one second active layer, and may include a tandem structure that further includes at least one second 2D material layer. The first active layer and the second active layer may have different light absorption bands. The broadband multi-purpose optical device may further include a second interfacial layer adjacent to the first 2D material layer.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: February 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kiyoung Lee, Jinseong Heo, Jaeho Lee, Haeryong Kim, Seongjun Park, Hyeonjin Shin, Eunkyu Lee, Sanghyun Jo
  • Patent number: 10522669
    Abstract: A method of making a quantum device with a quantum island structure is provided. The method includes the formation of a stack including a first semiconducting layer based on an undoped semiconducting material on which at least one second doped semiconducting layer is grown by epitaxy, the doping being made during epitaxial growth, a first region belonging to the first semiconducting layer and a second region belonging to the second semiconducting layer being suitable for forming a quantum island.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: December 31, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Sylvain Barraud
  • Patent number: 10522706
    Abstract: A photosensitive field-effect transistor configured to provide an electrical response when illuminated by electromagnetic radiation incident on the transistor. The photosensitive field-effect transistor comprises a layer of two-dimensional material which forms a horizontal transistor channel configured to transport current, and a horizontal semiconducting layer in contact with the transistor channel. The semiconducting layer comprises two or more assemblies of semiconducting material. If the two-dimensional material in the transistor channel has a high work function, the assemblies of semiconducting material are vertically stacked on the transistor channel in order of decreasing work function. If the two-dimensional material in the transistor channel has a low work function, the assemblies of semiconducting material are vertically stacked on the transistor channel in order of increasing work function.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: December 31, 2019
    Assignee: EMBERION OY
    Inventors: Alexander Bessonov, Mark Allen
  • Patent number: 10516064
    Abstract: A technique relates to a semiconductor device. A first stack includes a first plurality of nanowires respectively coupled to first source and drain regions, and a second stack includes a second plurality of nanowires respectively coupled to second source and drain regions. First source and drain contacts couple to a first predefined number of the first plurality of nanowires. Second source and drain contacts to couple to a second predefined number of the second plurality of nanowires, wherein the first predefined number is different from the second predefined number.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: December 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Lawrence A. Clevenger, Carl Radens, Junli Wang, John H. Zhang
  • Patent number: 10497701
    Abstract: A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins, a gate stack and an epitaxy structure. The semiconductor fins are present on the semiconductor substrate. The semiconductor fins respectively include recesses therein. The gate stack is present on portions of the semiconductor fins that are adjacent to the recesses. The epitaxy structure is present across the recesses of the semiconductor fins. The epitaxy structure includes a plurality of corners and at least one groove present between the corners, and the groove has a curvature radius greater than that of at least one of the corners.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: December 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Wen Cheng, Chih-Shan Chen, Mu-Tsang Lin
  • Patent number: 10497814
    Abstract: Semiconductor devices including a subfin including a first III-V semiconductor alloy and a channel including a second III-V semiconductor alloy are described. In some embodiments the semiconductor devices include a substrate including a trench defined by at least two trench sidewalls, wherein the first III-V semiconductor alloy is deposited on the substrate within the trench and the second III-V semiconductor alloy is epitaxially grown on the first III-V semiconductor alloy. In some embodiments, a conduction band offset between the first III-V semiconductor alloy and the second III-V semiconductor alloy is greater than or equal to about 0.3 electron volts. Methods of making such semiconductor devices and computing devices including such semiconductor devices are also described.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: December 3, 2019
    Assignee: INTEL CORPORATION
    Inventors: Harold W. Kennel, Matthew V. Metz, Willy Rachmady, Gilbert Dewey, Chandra S. Mohapatra, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani
  • Patent number: 10479069
    Abstract: The present invention relates to a method for manufacturing an angle and curvature detection sensor, and the sensor and, more specifically, to: a method for manufacturing a thin-film transistor array-based backplane by a roll-to-roll gravure printing process and manufacturing a sensor for measuring an angle change and a degree of curvature of the X axis and the Y axis by using the backplane; and the sensor. The method for manufacturing an angle and curvature detection sensor, according to an embodiment of the present invention, comprises the steps of: manufacturing a thin-film transistor backplane by a roll-to-roll gravure printing process; forming a protective layer on the thin-film transistor backplane by printing; forming a sealed space by adhering a flexible plastic case onto the upper part of the protective layer by means of an adhesive; and filling the sealed space with a first liquid and injecting a second liquid.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: November 19, 2019
    Assignee: INDUSTRY-ACADEMY COOPERATION CORPS OF SUNCHON NATIONAL UNIVERSITY
    Inventors: Gyou-jin Cho, Jun Feng Sun, Woo Kyu Lee, Jin Soo Noh
  • Patent number: 10483166
    Abstract: A method of fabricating a vertically stacked nanosheet semiconductor device includes epitaxially growing at least three layers each of alternating silicon and silicon germanium layers on a substrate and patterning a gate structure. The method includes performing at least three reactive ion etch processes forming recesses. The method includes forming source or drain regions in a channel formed by a shallow trench isolation layer formed in the recesses. The method includes growing a first epitaxial layer on the source or drain regions, forming at least three pFET structures. The method includes etching away a portion of each of the pFET structures and depositing a dielectric layer on each. The method includes growing a second epitaxial layer, forming at least three nFET structures. Each layer of the pFET structure and nFET structure are stacked vertically and each layer of the pFET structure and nFET structures have independent source or drain contacts.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: November 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Tenko Yamahita, Chun Wing Yeung, Chen Zhang
  • Patent number: 10439057
    Abstract: A multi-gate high electron mobility transistor (HEMT) and its methods of formation are disclosed. The multi-gate HEMT includes a substrate and an adhesion layer on top of the substrate. A channel layer is disposed on top of the adhesion layer, and a first gate electrode is disposed on top of the channel layer. The first gate electrode has a first gate dielectric layer in between the first gate electrode and the channel layer. A second gate electrode is embedded within the substrate and beneath the channel layer. The second gate electrode has a second gate dielectric layer completely surrounding the second gate electrode. A pair of source and drain contacts are disposed on opposite sides of the first gate electrode.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Kimin Jun, Sansaptak Dasgupta, Alejandro X. Levander, Patrick Morrow
  • Patent number: 10424581
    Abstract: An integrated circuit (IC) including a circuit block including a plurality of complementary metal oxide semiconductor field-effect transistors (CMOSFETs), and a tunnel field-effect transistor (TFET) between the circuit block and ground for power gating the circuit block.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: September 24, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Titash Rakshit, Mark Rodder, Rwik Sengupta
  • Patent number: 10396152
    Abstract: A semiconductor device including a plurality of suspended nanowires and a gate structure present on a channel region portion of the plurality of suspended nanowires. The gate structure has a uniform length extending from an upper surface of the gate structure to the base of the gate structure. The semiconductor device further includes a dielectric spacer having a uniform composition in direct contact with the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10388872
    Abstract: A method of forming a memory cell material comprises forming a first portion of a dielectric material over a substrate by atomic layer deposition. Discrete conductive particles are formed on the first portion of the dielectric material by atomic layer deposition. A second portion of the dielectric material is formed on and between the discrete conductive particles by atomic layer deposition. A memory cell material, a method of forming a semiconductor device structure, and a semiconductor device structure are also described.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, John A. Smythe
  • Patent number: 10388569
    Abstract: A method of fabricating a stacked semiconductor device includes forming nanosheet stacks including silicon layers and silicon germanium layers on a substrate. The method includes growing a first epitaxial layer on a source and drain and depositing an interlayer dielectric on the first epitaxial layer. The method includes etching the interlayer dielectric to expose the first epitaxial layer. The method includes etching a portion of the first epitaxial layer and growing a second epitaxial layer on the first epitaxial layer and etching the interlayer dielectric and depositing a first liner in a recess left by the etching, forming a pFET. The method includes etching a portion of the first liner and removing the second epitaxial layer leaving a portion of the first epitaxial layer exposed and depositing a second insulator layer on the first epitaxial layer, forming an nFET. The pFET and nFET are disposed adjacent to one another vertically.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Heng Wu, Peng Xu
  • Patent number: 10381584
    Abstract: The present disclosure provides a carbon nanotube thin film transistor (CNT-TFT) and its manufacturing method. The carbon nanotube thin film transistor includes a source electrode, a drain electrode, a channel region, a plurality of protrusions, and a carbon nanotube layer. The channel region is between the source electrode and the drain electrode. The plurality of protrusions are at, and extend in a length direction of, the channel region. The carbon nanotube layer is disposed over the plurality of protrusions, and comprises a plurality of carbon nanotubes.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: August 13, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., PEKING UNIVERSITY
    Inventors: Xuelei Liang, Guanbao Hui, Boyuan Tian, Fangzhen Zhang, Haiyan Zhao, Jiye Xia, Qiuping Yan, Lianmao Peng
  • Patent number: 10374073
    Abstract: Transistors and methods of forming the same include forming a fin that has an active layer between two sacrificial layers. Material from the two sacrificial layers is etched away in a region of the fin. A gate stack is formed around the active layer in the region. Source and drain regions are formed in contact with the active layer.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10347752
    Abstract: A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim
  • Patent number: 10340376
    Abstract: A process for fabricating a heterojunction field-effect transistor including a semiconductor structure made up of superposed layers, including: providing on a substrate layer (1) a buffer layer (2), a channel layer (3) and a barrier layer (4), the layers being made of materials having hexagonal crystal structures of the Ga(1-p-q)Al(p)In(q)N type; forming an opening in a dielectric masking layer (5) deposited on the barrier layer; growing by high-temperature epitaxy a semiconductor material (6, 6?) having a hexagonal crystal structure, namely Ga(1-x?-y?)Al(x?)In(y?)N, doped with germanium, on a growth zone defined by the opening formed in the masking layer; and depositing a source or drain contact electrode (15, 16) on the material thus deposited by epitaxy, and a gate electrode (13) in a location outside of the growth zone.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: July 2, 2019
    Assignee: OMMIC
    Inventor: Peter Frijlink
  • Patent number: 10332962
    Abstract: A method for fabricating a semiconductor structure includes forming a nanosheet stack on a base. The nanosheet stack comprises one or more first nanosheet layers each comprised of a first material and one or more second nanosheet layers each comprised of a second material different from the first material. The nanosheet stack is recessed. Inner spacers comprising a third material are formed. Forming the inner spacers includes converting the first material corresponding to outer portions of each of the one or more first nanosheet layers into the third material.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Xin Miao, Kangguo Cheng, Chen Zhang, Wenyu Xu
  • Patent number: 10332999
    Abstract: A method for manufacturing a semiconductor device includes patterning a strained semiconductor layer on a substrate into at least one strained fin, forming a plurality of dummy gates spaced apart from each other on the at least one strained fin, forming a spacer layer on the plurality of dummy gates, and on part of the at least one strained fin between the plurality of dummy gates, growing a plurality of source/drain regions on exposed portions of the at least one strained fin, removing the spacer layer from the part of the at least one strained fin between the plurality of dummy gates, and converting the part of the at least one strained fin between the plurality of dummy gates into at least one oxide.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Choonghyun Lee, Peng Xu, Heng Wu
  • Patent number: 10325821
    Abstract: Techniques facilitating three-dimensional stacked vertical transport field effect transistor logic gates with buried power bus are provided. A logic device can comprise a plate and a first vertical transport field effect transistor formed over and adjacent the plate. The logic device can also comprise a second vertical transport field effect transistor stacked on the first vertical transport field effect transistor. The plate can be a power layer and can be continuous within regions of the device that utilize a common voltage. The plate can be contacted from a surface of the device at intervals corresponding to the regions of common voltage. The plate can be electrically connected to ground. Alternatively, the plate can be electrically connected to a power supply.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Terry Hook, Ardasheir Rahman, Joshua Rubin, Chen Zhang
  • Patent number: 10326000
    Abstract: A method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed portions of semiconductor fins not covered by a gate electrode, wherein an upper surface of the self-aligned silicide contact is substantially flush with an upper surface of an adjacent isolation region, patterning a blanket metal layer to form a source-drain contact on the upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the semiconductor fins to the source-drain contact, and recessing a portion of the self-aligned silicide contact without recessing the isolation region, the self-aligned silicide contact is recessed selective to a mask used to pattern the source-drain contact.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Veeraraghavan S. Basker, Sivananda K. Kanakasabapathy
  • Patent number: 10319813
    Abstract: Integrated chips and methods of forming the same include forming a respective stack of sheets in two regions, each stack having first layers and second layers. The second layers are etched away in the first region. The second region is annealed to change the composition of the first layers in the second region by interaction with the second layers in the second region. A gate stack is formed in the first and second region.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10319860
    Abstract: A device and method for fabricating a nanowire include patterning a first set of structures on a substrate. A dummy structure is formed over portions of the substrate and the first set of structures. Exposed portions of the substrate are etched to provide an unetched raised portion. First spacers are formed about a periphery of the dummy structure and the unetched raised portion. The substrate is etched to form controlled undercut etched portions around a portion of the substrate below the dummy structure. Second spacers are formed in the controlled undercut etched portions. Source/drain regions are formed with interlayer dielectric regions formed thereon. The dummy structure is removed. The substrate is etched to release the first set of structures. Gate structures are formed including a top gate formed above the first set of structures and a bottom gate formed below the first set of structures to provide a nanowire.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 10312337
    Abstract: A method of forming two or more nano-sheet devices with varying electrical gate lengths, including, forming at least two cut-stacks including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate, removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess having a recess depth in the at least one alternating nano-sheet channel layers, where the recess depth is greater than the indentation depth.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek