Field Effect Device Patents (Class 257/24)
  • Patent number: 10439057
    Abstract: A multi-gate high electron mobility transistor (HEMT) and its methods of formation are disclosed. The multi-gate HEMT includes a substrate and an adhesion layer on top of the substrate. A channel layer is disposed on top of the adhesion layer, and a first gate electrode is disposed on top of the channel layer. The first gate electrode has a first gate dielectric layer in between the first gate electrode and the channel layer. A second gate electrode is embedded within the substrate and beneath the channel layer. The second gate electrode has a second gate dielectric layer completely surrounding the second gate electrode. A pair of source and drain contacts are disposed on opposite sides of the first gate electrode.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Kimin Jun, Sansaptak Dasgupta, Alejandro X. Levander, Patrick Morrow
  • Patent number: 10424581
    Abstract: An integrated circuit (IC) including a circuit block including a plurality of complementary metal oxide semiconductor field-effect transistors (CMOSFETs), and a tunnel field-effect transistor (TFET) between the circuit block and ground for power gating the circuit block.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: September 24, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Titash Rakshit, Mark Rodder, Rwik Sengupta
  • Patent number: 10396152
    Abstract: A semiconductor device including a plurality of suspended nanowires and a gate structure present on a channel region portion of the plurality of suspended nanowires. The gate structure has a uniform length extending from an upper surface of the gate structure to the base of the gate structure. The semiconductor device further includes a dielectric spacer having a uniform composition in direct contact with the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10388569
    Abstract: A method of fabricating a stacked semiconductor device includes forming nanosheet stacks including silicon layers and silicon germanium layers on a substrate. The method includes growing a first epitaxial layer on a source and drain and depositing an interlayer dielectric on the first epitaxial layer. The method includes etching the interlayer dielectric to expose the first epitaxial layer. The method includes etching a portion of the first epitaxial layer and growing a second epitaxial layer on the first epitaxial layer and etching the interlayer dielectric and depositing a first liner in a recess left by the etching, forming a pFET. The method includes etching a portion of the first liner and removing the second epitaxial layer leaving a portion of the first epitaxial layer exposed and depositing a second insulator layer on the first epitaxial layer, forming an nFET. The pFET and nFET are disposed adjacent to one another vertically.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Heng Wu, Peng Xu
  • Patent number: 10388872
    Abstract: A method of forming a memory cell material comprises forming a first portion of a dielectric material over a substrate by atomic layer deposition. Discrete conductive particles are formed on the first portion of the dielectric material by atomic layer deposition. A second portion of the dielectric material is formed on and between the discrete conductive particles by atomic layer deposition. A memory cell material, a method of forming a semiconductor device structure, and a semiconductor device structure are also described.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, John A. Smythe
  • Patent number: 10381584
    Abstract: The present disclosure provides a carbon nanotube thin film transistor (CNT-TFT) and its manufacturing method. The carbon nanotube thin film transistor includes a source electrode, a drain electrode, a channel region, a plurality of protrusions, and a carbon nanotube layer. The channel region is between the source electrode and the drain electrode. The plurality of protrusions are at, and extend in a length direction of, the channel region. The carbon nanotube layer is disposed over the plurality of protrusions, and comprises a plurality of carbon nanotubes.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: August 13, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., PEKING UNIVERSITY
    Inventors: Xuelei Liang, Guanbao Hui, Boyuan Tian, Fangzhen Zhang, Haiyan Zhao, Jiye Xia, Qiuping Yan, Lianmao Peng
  • Patent number: 10374073
    Abstract: Transistors and methods of forming the same include forming a fin that has an active layer between two sacrificial layers. Material from the two sacrificial layers is etched away in a region of the fin. A gate stack is formed around the active layer in the region. Source and drain regions are formed in contact with the active layer.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10347752
    Abstract: A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim
  • Patent number: 10340376
    Abstract: A process for fabricating a heterojunction field-effect transistor including a semiconductor structure made up of superposed layers, including: providing on a substrate layer (1) a buffer layer (2), a channel layer (3) and a barrier layer (4), the layers being made of materials having hexagonal crystal structures of the Ga(1-p-q)Al(p)In(q)N type; forming an opening in a dielectric masking layer (5) deposited on the barrier layer; growing by high-temperature epitaxy a semiconductor material (6, 6?) having a hexagonal crystal structure, namely Ga(1-x?-y?)Al(x?)In(y?)N, doped with germanium, on a growth zone defined by the opening formed in the masking layer; and depositing a source or drain contact electrode (15, 16) on the material thus deposited by epitaxy, and a gate electrode (13) in a location outside of the growth zone.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: July 2, 2019
    Assignee: OMMIC
    Inventor: Peter Frijlink
  • Patent number: 10332999
    Abstract: A method for manufacturing a semiconductor device includes patterning a strained semiconductor layer on a substrate into at least one strained fin, forming a plurality of dummy gates spaced apart from each other on the at least one strained fin, forming a spacer layer on the plurality of dummy gates, and on part of the at least one strained fin between the plurality of dummy gates, growing a plurality of source/drain regions on exposed portions of the at least one strained fin, removing the spacer layer from the part of the at least one strained fin between the plurality of dummy gates, and converting the part of the at least one strained fin between the plurality of dummy gates into at least one oxide.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Choonghyun Lee, Peng Xu, Heng Wu
  • Patent number: 10332962
    Abstract: A method for fabricating a semiconductor structure includes forming a nanosheet stack on a base. The nanosheet stack comprises one or more first nanosheet layers each comprised of a first material and one or more second nanosheet layers each comprised of a second material different from the first material. The nanosheet stack is recessed. Inner spacers comprising a third material are formed. Forming the inner spacers includes converting the first material corresponding to outer portions of each of the one or more first nanosheet layers into the third material.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Xin Miao, Kangguo Cheng, Chen Zhang, Wenyu Xu
  • Patent number: 10326000
    Abstract: A method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed portions of semiconductor fins not covered by a gate electrode, wherein an upper surface of the self-aligned silicide contact is substantially flush with an upper surface of an adjacent isolation region, patterning a blanket metal layer to form a source-drain contact on the upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the semiconductor fins to the source-drain contact, and recessing a portion of the self-aligned silicide contact without recessing the isolation region, the self-aligned silicide contact is recessed selective to a mask used to pattern the source-drain contact.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Veeraraghavan S. Basker, Sivananda K. Kanakasabapathy
  • Patent number: 10325821
    Abstract: Techniques facilitating three-dimensional stacked vertical transport field effect transistor logic gates with buried power bus are provided. A logic device can comprise a plate and a first vertical transport field effect transistor formed over and adjacent the plate. The logic device can also comprise a second vertical transport field effect transistor stacked on the first vertical transport field effect transistor. The plate can be a power layer and can be continuous within regions of the device that utilize a common voltage. The plate can be contacted from a surface of the device at intervals corresponding to the regions of common voltage. The plate can be electrically connected to ground. Alternatively, the plate can be electrically connected to a power supply.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Terry Hook, Ardasheir Rahman, Joshua Rubin, Chen Zhang
  • Patent number: 10319813
    Abstract: Integrated chips and methods of forming the same include forming a respective stack of sheets in two regions, each stack having first layers and second layers. The second layers are etched away in the first region. The second region is annealed to change the composition of the first layers in the second region by interaction with the second layers in the second region. A gate stack is formed in the first and second region.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10319860
    Abstract: A device and method for fabricating a nanowire include patterning a first set of structures on a substrate. A dummy structure is formed over portions of the substrate and the first set of structures. Exposed portions of the substrate are etched to provide an unetched raised portion. First spacers are formed about a periphery of the dummy structure and the unetched raised portion. The substrate is etched to form controlled undercut etched portions around a portion of the substrate below the dummy structure. Second spacers are formed in the controlled undercut etched portions. Source/drain regions are formed with interlayer dielectric regions formed thereon. The dummy structure is removed. The substrate is etched to release the first set of structures. Gate structures are formed including a top gate formed above the first set of structures and a bottom gate formed below the first set of structures to provide a nanowire.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 10312367
    Abstract: High voltage transistors spanning multiple non-planar semiconductor bodies, such as fins or nanowires, are monolithically integrated with non-planar transistors utilizing an individual non-planar semiconductor body. The non-planar FETs may be utilized for low voltage CMOS logic circuitry within an IC, while high voltage transistors may be utilized for high voltage circuitry within the IC. A gate stack may be disposed over a high voltage channel region separating a pair of fins with each of the fins serving as part of a source/drain for the high voltage device. The high voltage channel region may be a planar length of substrate recessed relative to the fins. A high voltage gate stack may use an isolation dielectric that surrounds the fins as a thick gate dielectric. A high voltage transistor may include a pair of doped wells formed into the substrate that are separated by the high voltage gate stack with one or more fin encompassed within each well.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Kinyip Phoa, Nidhi Nidhi, Chia-Hong Jan, Ting Chang
  • Patent number: 10312337
    Abstract: A method of forming two or more nano-sheet devices with varying electrical gate lengths, including, forming at least two cut-stacks including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate, removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess having a recess depth in the at least one alternating nano-sheet channel layers, where the recess depth is greater than the indentation depth.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10304840
    Abstract: A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Keun-hee Bai, Myeong-cheol Kim, Kwan-heum Lee, Do-hyoung Kim, Jin-wook Lee, Seung-mo Ha, Dong-Hoon Khang
  • Patent number: 10297508
    Abstract: Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Cheng, Tzu-Chiang Chen, Chen-Feng Hsu, Yu-Lin Yang, Tung Ying Lee, Chih Chieh Yeh
  • Patent number: 10281464
    Abstract: Provided herein is a field-effect transistor based sensor for real-time detection of water contaminants and methods of use thereof.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: May 7, 2019
    Assignee: UWM Research Foundation, Inc.
    Inventors: Junhong Chen, Jingbo Chang
  • Patent number: 10269962
    Abstract: A semiconductor device has a fin-type structure which extends in a first direction and includes a laminate of oxide and semiconductor patterns disposed one on another on a first region of a substrate, and a first gate electrode that extends longitudinally in a second direction different from the first direction on the fin-type structure. Each oxide pattern is an oxidized compound containing a first element.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: April 23, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Ryul Lee, Sang Moon Lee, Chul Kim, Ji Eon Yoon
  • Patent number: 10256102
    Abstract: A process for fabricating a gate-wrap-around field-effect transistor is provided, including providing a substrate surmounted with first and second nanowires extending in a same longitudinal direction and having a median portion covered by a first material, and first and second ends that are arranged on either side of the median portion, a periphery of which is covered by respective first and second dielectric spacers made of a second material that is different from the first material, the ends having exposed lateral faces; doping a portion of the first and second ends via the lateral faces; depositing an amorphous silicon alloy on the first and second lateral faces followed by crystallizing the alloy; and depositing a metal on either side of the nanowires to form first and second metal contacts that respectively make electrical contact with the doped portions of the first and second ends of the nanowires.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 9, 2019
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Remi Coquand, Emmanuel Augendre, Shay Reboh
  • Patent number: 10242920
    Abstract: Embodiments of the invention are directed to a method of forming an insulation region during fabrication of a nanosheet channel field effect transistor (FET). The method includes forming a first sacrificial nanosheet across from a major surface of a substrate, wherein the first sacrificial nanosheet includes a first semiconductor material at a concentration percentage less than or equal to about fifty percent. A first nanosheet stack is formed on an opposite side of the first sacrificial nanosheet from the major surface of the substrate, wherein the first nanosheet stack includes alternating channel nanosheets and sacrificial stack nanosheets, wherein a thickness dimension of the first sacrificial nanosheet is greater than a thickness dimension of at least one of the alternating channel nanosheets. An oxidation operation is performed that converts the first sacrificial nanosheet to a dielectric oxide, wherein the insulation region includes the dielectric oxide.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, Nicolas J. Loubet, Muthumanickam Sankarapandian
  • Patent number: 10242882
    Abstract: Methods are provided to implement a cyclic etch process to remove oxide layers for semiconductor device fabrication. For example, a method comprises performing a cyclic etch process to incrementally etch an oxide layer, wherein the cyclic etch process comprises sequentially performing at least two instances of an etch cycle. The etch cycle comprises performing an etch process to partially etch a portion of the oxide layer using an etch chemistry and environment which is configured to etch down the oxide layer at an etch rate of about 25 angstroms/minute or less, and performing a thermal treatment to remove by-products of the etch process. The cyclic etch process can be implemented as part of a replacement metal gate process to remove a dummy gate oxide layer of a dummy gate structure as part of, e.g., a FinFET semiconductor fabrication process flow.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Donald F. Canaperi, Thamarai S. Devarajan, Sean Teehan
  • Patent number: 10229981
    Abstract: Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Abhijit Jayant Pethe, Tahir Ghani, Harry Gomez
  • Patent number: 10217823
    Abstract: An electron device having a channel layer made of graphene is disclosed. The electron device includes a graphene layer on a substrate, and a source electrode, a drain electrode, and a gate insulating film on the graphene layer. The electron device further includes a first gate electrode on the gate insulating film between the source electrode and the drain electrode, and a second gate electrode within the substrate. For the second gate electrode, another gate insulating film is on the graphene layer, or alternatively, a part of the substrate is interposed between the second gate electrode and the channel layer.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: February 26, 2019
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., TOHOKU UNIVERSITY
    Inventors: Yasunori Tateno, Masaki Ueno, Masaya Okada, Fuminori Mitsuhashi, Maki Suemitsu, Hirokazu Fukidome
  • Patent number: 10217730
    Abstract: A method of making a micro-transfer printed system includes providing a source wafer having a plurality of micro-transfer printable source devices arranged at a source spatial density; providing an intermediate wafer having a plurality of micro-transfer printable intermediate supports arranged at an intermediate spatial density less than or equal to the source spatial density; providing a destination substrate; micro-transfer printing the source devices from the source wafer to the intermediate supports of the intermediate wafer with a source stamp having a plurality of posts at a source transfer density to make an intermediate device on each intermediate support; and micro-transfer printing the intermediate devices from the intermediate wafer to the destination substrate at a destination spatial density less than the source spatial density with an intermediate stamp having a plurality of posts at an intermediate transfer density less than the source transfer density.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: February 26, 2019
    Assignee: X-Celeprint Limited
    Inventors: Christopher Bower, Matthew Meitl
  • Patent number: 10204902
    Abstract: A semiconductor device includes a first active structure on a substrate including a first epitaxial pattern, a second epitaxial pattern and a first channel pattern between the first epitaxial pattern and the second epitaxial pattern, the first channel pattern including at least one channel pattern stacked on the substrate. A first gate structure is disposed on top and bottom surfaces of the first channel pattern. A second active structure on the substrate and includes the second epitaxial pattern, a third epitaxial pattern and a second channel pattern between the second epitaxial pattern and the third epitaxial pattern in the first direction. The second channel pattern includes at least one channel pattern stacked on the substrate. The number of stacked second channel patterns is greater than the number of stacked first channel patterns. A second gate structure is disposed on top and bottom surfaces of the second channel pattern.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hae-Wang Lee
  • Patent number: 10170637
    Abstract: A semiconductor device including a plurality of suspended nanowires and a gate structure that is present on a channel region portion of the plurality of suspended nanowires. The gate structure includes a uniform length extending from an upper surface of the gate structure to the base of the gate structure. A dielectric spacer having a graded composition is present in direct contact with the gate structure. The dielectric spacer having a uniform length extending from an upper surface of the gate structure to the base of the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10170550
    Abstract: A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires. Isolated gate structures are formed in regions underlying the disposable gate structure by deposition and recessing of a first gate dielectric layer and a first gate conductor layer. After formation of a gate spacer, source regions, and drain regions, raised source and drain regions are formed on the source regions and the drain regions by selective deposition of a semiconductor material. The disposable gate structure is replaced with a replacement gate structure by deposition and patterning of a second gate dielectric layer and a second gate conductor layer. Distortion of the suspended semiconductor nanowires is prevented by the disposable gate structure and the isolated gate structures.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Frank, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10170547
    Abstract: A nanodevice capable of controlling the state of electric charge of a metal nanoparticle is provided. The device includes: nanogap electrodes 5 including one electrode 5A and the other electrode 5B disposed so as to have a nanosize gap in between; a nanoparticle 7 placed between the nanogap electrodes 5; and a plurality of gate electrodes 9. At least one of the plurality of gate electrodes 9 is used as a floating gate electrode to control the state of electric charge of the nanoparticle 7, which achieves a multivalued memory and rewritable logical operation.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: January 1, 2019
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Yutaka Majima, Toshiharu Teranishi, Shinya Kano, Eiki Aoyama
  • Patent number: 10170331
    Abstract: Techniques for producing stacked SiGe nanowires using a condensation process without parasitic Ge nanowires as an undesired by-product. In one aspect, a method of forming SiGe nanowires includes the steps of: forming a stack of alternating Si and SiGe layers on a wafer; patterning fins in the stack; selectively thinning the SiGe layers in the fins such that the Si and SiGe layers give the fins an hourglass shape; burying the fins in an oxide material; and annealing the fins under conditions sufficient to diffuse Ge from the SiGe layers in the fins to the Si layers in the fins to form the SiGe nanowires. A FET device and method for formation thereof are also provided.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Xin Miao
  • Patent number: 10153348
    Abstract: In an example, a memory may have a group of series-coupled memory cells, where a memory cell of the series-coupled memory cells has an access gate, a control gate coupled to the access gate, and a dielectric stack between the control gate and a semiconductor. The dielectric stack is to store a charge.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: December 11, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 10141305
    Abstract: Semiconductor devices employing Field Effect Transistors (FETs) with multiple channel structures without shallow trench isolation (STI) void-induced electrical shorts are disclosed. In one aspect, a semiconductor device is provided that includes a substrate. The semiconductor device includes channel structures disposed over the substrate, the channel structures corresponding to a FET. An STI trench is formed between each corresponding pair of channel structures. Each STI trench includes a bottom region filled with a lower quality oxide, and a top region filled with a higher quality oxide. The lower quality oxide is susceptible to void formation in the bottom region during particular fabrication steps of the semiconductor device. However, the higher quality oxide is not susceptible to void formation. Thus, the higher quality oxide does not include voids with which a gate may electrically couple to other active components, thus preventing STI void-induced electrical shorts in the semiconductor device.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: November 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Jeffrey Junhao Xu, Haining Yang, Jun Yuan, Kern Rim, Periannan Chidambaram
  • Patent number: 10134640
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes a gate structure over the fin portion and extending across the fin portion. The semiconductor device structure includes a first semiconductor wire over the fin portion and passing through the gate structure. The semiconductor device structure includes a second semiconductor wire over the first semiconductor wire and passing through the gate structure. The gate structure surrounds the second semiconductor wire and separates the first semiconductor wire from the second semiconductor wire. The first semiconductor wire and the second semiconductor wire are made of different materials.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Li Chiang, I-Sheng Chen, Tzu-Chiang Chen, Chao-Ching Cheng, Chih-Chieh Yeh, Yee-Chia Yeo
  • Patent number: 10134594
    Abstract: The invention relates to a method for manufacture of an electrical contact on a structure (10) made of an anisotropic material NA which exhibits an anisotropic electrical conductivity, where the structure (10) exhibits an axial electrical conductivity along a first axis XX? of the structure (10) and an orthogonal conductivity along a direction YY? orthogonal to the first axis XX? of the structure (10), where the orthogonal conductivity is less than the axial conductivity, where the method comprises: a step for the formation of a conductive electrode (20), with an initial thickness Ei, comprising a species M, on a first surface (30) of the structure (10), where the first surface (30) is orthogonal to the orthogonal direction YY?; the method being characterized in that the step for the formation of the conductive electrode (20) is followed by a step for implantation of species X through the conductive electrode (20), into the structure (10).
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: November 20, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Raphael Ramos, Jean Dijon
  • Patent number: 10134889
    Abstract: A disclosed compound semiconductor device includes a substrate, a channel layer formed over the substrate, an electron supply layer famed on the channel layer, a first cap layer and a second cap layer formed at a distance from each other on the electron supply layer, a source electrode formed on the first cap layer, a drain electrode formed on the second cap layer, and a gate electrode formed on the electron supply layer between the first cap layer and the second cap layer. Each of the first cap layer and the second cap layer is a stacked film formed by alternately stacking i-type first compound semiconductor layers and n-type second compound semiconductor layers having a wider bandgap than the first compound semiconductor layers.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: November 20, 2018
    Assignee: Fujitsu Limited
    Inventor: Tsuyoshi Takahashi
  • Patent number: 10128122
    Abstract: Techniques for producing stacked SiGe nanowires using a condensation process without parasitic Ge nanowires as an undesired by-product. In one aspect, a method of forming SiGe nanowires includes the steps of: forming a stack of alternating Si and SiGe layers on a wafer; patterning fins in the stack; selectively thinning the SiGe layers in the fins such that the Si and SiGe layers give the fins an hourglass shape; burying the fins in an oxide material; and annealing the fins under conditions sufficient to diffuse Ge from the SiGe layers in the fins to the Si layers in the fins to form the SiGe nanowires. A FET device and method for formation thereof are also provided.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: November 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Xin Miao
  • Patent number: 10121857
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: November 6, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
  • Patent number: 10103253
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: October 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay Chuang, Yi-Ren Chen, Chi-Wen Liu, Chao-Hsiung Wang, Ming Zhu
  • Patent number: 10074575
    Abstract: Embodiments of the invention are directed to methods of fabricating nanosheet channel field effect transistors. An example method includes forming a first sacrificial nanosheet and forming a first nanosheet stack over the first sacrificial nanosheet, wherein the first nanosheet stack includes alternating channel nanosheets and sacrificial nano sheets. The method further includes exposing a surface area of the first sacrificial nanosheet and exposing surface areas of the alternating channel nanosheets and sacrificial nanosheets, wherein the exposed surface area of the first sacrificial nanosheet is greater than each of the exposed surface areas of the alternating channel nanosheets and sacrificial nanosheets. The method further includes applying an etchant to the exposed surface areas, wherein the etchant is selective based at least in part on the amount of surface area to which the etchant is applied.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: September 11, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, Nicolas J. Loubet, Muthumanickam Sankarapandian
  • Patent number: 10068970
    Abstract: A method for manufacturing a semiconductor device includes forming a doped silicon layer on a bulk substrate, forming an undoped silicon cap layer on the doped silicon layer, forming a stacked configuration of silicon germanium (SiGe) and silicon layers on the undoped silicon cap layer, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on an SiGe layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, the doped silicon layer and the undoped silicon cap layer, forming a spacer layer on each of the plurality of dummy gates, and on the doped silicon layer and the undoped silicon cap layer, selectively etching the doped silicon layer with respect to the undoped silicon layer, and filling the area from where the doped s silicon layer was selectively removed with a dielectric layer.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Junli Wang
  • Patent number: 10068990
    Abstract: A MOS transistor with stacked nanowires and a method of manufacturing the same. The transistor may include a stack of cascaded nanowires extending in a first direction on a substrate; a gate stack extending in a second direction across the nanowire stack; source and drain regions disposed on opposite sides of the gate stack in the second direction; and a channel region constituted of the nanowire stack between the source and drain regions. The cascaded nanowires can be formed by repeated operations of etching back, and lateral etching and then filling of grooves, thereby increasing an effective width of the channel, increasing a total area of an effective conductive section, and thus improving a drive current.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: September 4, 2018
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Huaxiang Yin, Xiaolong Ma, Weijia Xu, Qiuxia Xu, Huilong Zhu
  • Patent number: 10068969
    Abstract: A method for fabricating a nanowire transistor is disclosed. First, a substrate is provided, and a stack structure is formed on the substrate, in which the stack structure includes a first semiconductor layer and a second semiconductor layer and the first semiconductor layer and the second semiconductor layer are made of different material. Next, a hard mask is formed on the stack structure and a first spacer adjacent to the hard mask, part of the stack structure is removed; a second spacer is formed adjacent to the first spacer and the stack structure; and a source/drain structure is formed adjacent to two sides of the second spacer.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: September 4, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Yu-Cheng Tung
  • Patent number: 10069093
    Abstract: One example includes a semiconductor device. The semiconductor device include a carbon nanotube substrate, a self-assembled monolayer, and a gate oxide. The self-assembled monolayer overlies the carbon nanotube substrate and is comprised of molecules each including a tail group, a carbon backbone, and a head group. The gate oxide overlies the self-assembled monolayer, wherein the self-assembled monolayer forms an interface between the carbon nanotube substrate and the gate oxide.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: September 4, 2018
    Assignee: Northrop Grumman Systems Corporation
    Inventors: James T. Kelliher, Monica P. Lilly, Robert S. Howell, Wayne Stephen Miller, Patrick B. Shea, Matthew J. Walker, William J. Sweet
  • Patent number: 10043796
    Abstract: A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: August 7, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Vladimir Machkaoutsan, Stanley Seungchul Song, Mustafa Badaroglu, John Jianhong Zhu, Junjing Bao, Jeffrey Junhao Xu, Da Yang, Matthew Michael Nowak, Choh Fei Yeap
  • Patent number: 10037831
    Abstract: A nanowire device and a method of making a nanowire device are provided. The device includes a plurality of nanowires functionalized with different functionalizing compounds. The method includes functionalizing the nanowires with a functionalizing compound, dispersing the nanowires in a polar or semi-polar solvent, aligning the nanowires on a substrate such that longitudinal axes of the nanowires are oriented about perpendicular to a major surface of the substrate, and fixing the nanowires to the substrate.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: July 31, 2018
    Assignee: SOL VOLTAICS AB
    Inventors: Tommy Mikael Garting, Maria Huffman, Lars Göran Stefan Ulvenlund, Johan Eric Borgström, Umear Naseem
  • Patent number: 10037885
    Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: July 31, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 10032627
    Abstract: A method includes forming a first semiconductor stack using an epitaxial growth process, the first semiconductor stack comprising a first plurality of semiconductor layers alternating with a second plurality of semiconductor layers, the first plurality of semiconductor layers comprising a first semiconductor material and the second plurality of semiconductor layers comprising a second semiconductor material that is different than the first semiconductor material. The method further includes patterning the first semiconductor stack to form a set of semiconductor stack features, forming isolation features between the semiconductor stack features, removing at least one of the semiconductor stack features, thereby forming at least one trench, and forming, within the trench, a second semiconductor stack using an epitaxial growth process, the second semiconductor stack having different characteristics than the first semiconductor stack.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: July 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tung Ying Lee, Shao-Ming Yu
  • Patent number: 10026825
    Abstract: A semiconductor may include a semiconductor substrate including a first region and a second region disposed at opposite sides of the first region, a first trench formed in the first region, a buffer layer filling a portion of the first trench, a first semiconductor layer formed on the buffer layer, a second semiconductor layer forming a hetero-junction with the first semiconductor layer on the first semiconductor layer of the first region and a gate electrode formed on the second semiconductor layer of the first region.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: July 17, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jae Hoon Lee