Abstract: A biosensor comprising a substrate, a gate electrode provided on the substrate, an insulating layer provided on the gate electrode, a source electrode and a drain electrode, provided on the insulating layer, respectively, an n-type channel provided between the source electrode and the drain electrode, and a quantum dot layer provided on the n-type channel and provided so as to have electronic transition energy capable of resonating with vibration energy of a target biological material.

Abstract: A carbon nanotube (CNT) single ion memory (or memory device) may include a mobile ion conductor with a CNT on one side and an ion drift electrode (IDE) on the other side. The mobile ion conductor may be used as a transport medium to shuttle ions to and from the CNT and the IDE. The IDE may move the ions towards or away from the CNT.

Abstract: Devices comprising germanium nanosheets are described herein. Methods of forming such germanium nanosheets and devices including such germanium nanosheets are also described.

Abstract: Gate all-around devices are disclosed in which an angled channel comprising a semiconducting nanostructure is located between a source and a drain. The angled channel has an axis that is oriented at an angle to the top surface of the substrate at an angle in a range of about 1° to less than about 90°. The gate all-around device is intended to meet design and performance criteria for the 7 nm technology generation.

Abstract: In order to obtain a carbon nanotube array including no m-CNTs through simple steps using a mechanism that is different from thermocapillary flow, there are provided a process for producing a carbon nanotube array including (A) a step of preparing a carbon nanotube array in which m-CNTs and s-CNTs are horizontally aligned; (B) a step of forming an organic layer on the carbon nanotube array; (C) a step of applying voltage to the carbon nanotube array in a long axis direction of the carbon nanotubes constituting the carbon nanotube array in the air; and (D) a step of removing the organic layer, and a carbon nanotube array obtained by the process.

Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.

Abstract: A quantum dot manufacturing method comprises (a) dispersing, in a solvent, nano-seed particles whose crystal planes are exposed, and (b) growing semiconductor layers on the exposed crystal planes of the nano-seed particles in the solvent.

Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.

Abstract: A method for forming a nanodevice sensing chip includes forming nanodevices having a sensing region capable of producing localized Joule heating. Individual nanodevice is electrical-biased in a chemical vapor deposition (CVD) system or an atomic layer deposition (ALD) system enabling the sensing region of the nanodevice produce localized Joule heating and depositing sensing material only on this sensing region. A sensing chip is formed via nanodevices with sensing region of each nanodevice deposited various materials separately. The sensing chip is also functioned under device Joule self-heating to interact and detect the specific molecules.

Abstract: The present invention provides VFET device designs for top contact resistance measurement. In one aspect, a method of forming a VFET test structure includes: etching fins in a substrate (for active and sensing devices); forming bottom source/drains at a base of the fins; forming a STI region that isolates the bottom source/drains of the active device from that of the sensing device; forming a gate surrounding each of the fins; forming top source/drains over the gate, wherein the top source/drains of the active device and that of the sensing device are merged; and forming contacts to i) the bottom source/drains of the active device, ii) the top source/drains of the active device, and iii) the bottom source/drains of the sensing device. A test structure formed by the method as well as techniques for use thereof for measuring contact resistance are also provided.

Abstract: Novel and useful quantum structures having a continuous well with control gates that control a local depletion region to form quantum dots. Local depleted well tunneling is used to control quantum operations to implement quantum computing circuits. Qubits are realized by modulating gate potential to control tunneling through local depleted region between two or more sections of the well. Complex structures with a higher number of qdots per continuous well and a larger number of wells are fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. Combining a number of elementary quantum structure, a quantum computing machine is realized. An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device.

Abstract: FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.

Abstract: Provided herein are wafers that can be used to align carbon nanotubes, as well as methods of making and using the same. Such wafers include alignment areas that have four sides and a surface charge, where the alignment areas are surrounded by areas that have a surface charge of a different polarity. Methods of the disclosure may include depositing and selectively etching a number of hardmasks on a substrate. The described methods may also include depositing a carbon nanotube on such a wafer.

Abstract: The present invention provides a Gate-All-Around nano-sheet complementary inverter, comprising: P-type semiconductor transistors and N-type semiconductor transistors, wherein the P-type semiconductor transistors comprise P-type semiconductor nano-sheet channels, a first gate dielectric layer fully surrounding the P-type semiconductor nano-sheet channels, a first gate electrode layer fully surrounding the first gate dielectric layer, a first source region and a first drain region, connected to two ends of the P-type semiconductor nano-sheet channel respectively, the N-type semiconductor transistors comprise N-type semiconductor nano-sheet channels, a second gate dielectric layer fully surrounding the N-type semiconductor nano-sheet channels, a second gate electrode layer fully surrounding the second gate dielectric layer, a second source region and a second drain region, connected to two ends of the N-type semiconductor nano-sheet channel respectively; and a common electrode fully surrounding the first gate el

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin has a first side face and a second side face, and the fin includes a quantum well layer; and a gate above the fin, wherein the gate extends down along the first side face.

Abstract: In a standard cell including nanowire FETs, pads connected to nanowires are arranged at a predetermined pitch in X direction along which the nanowires extend. A cell width of the standard cell is an integral multiplication of the pitch. In a case where the standard cell is arranged to constitute the layout of a semiconductor integrated circuit device, the pads are regularly arranged in the X direction.

Abstract: An I/O device nanosheet material stack of suspended semiconductor channel material nanosheets is provided above a semiconductor substrate. A physically exposed portion of each suspended semiconductor channel material nanosheet is thinned to increase the inter-nanosheet spacing between each vertically stacked semiconductor channel material nanosheet. An I/O device functional gate structure is formed wrapping around the thinned portion of each suspended semiconductor channel material nanosheet.

Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. A mask pattern is formed over the sacrificial layer. The sacrificial layer and the source/drain structure are patterned by using the mask pattern as an etching mask, thereby forming openings adjacent to the patterned sacrificial layer and source/drain structure. A dielectric layer is formed in the openings. After the dielectric layer is formed, the patterned sacrificial layer is removed to form a contact opening over the patterned source/drain structure. A conductive layer is formed in the contact opening.

Abstract: A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.

Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.

Abstract: Systems, apparatuses and methods may provide for technology that assigns a plurality of data portions associated with a workload to a plurality of cores, wherein each data portion from the plurality of data portions is only modifiable by a respective one of the plurality of cores. The technology may further pass a message between the plurality of cores to modify one or more of the data portions in response to an identification that the one or more of the data portions are unmodifiable by one or more of the plurality of cores.

Abstract: A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of example, a first metal portion is formed within the insulating layer. In various embodiments, a first lateral surface of the first metal portion is exposed. After exposure of the first lateral surface of the first metal portion, a first graphene layer is formed on the exposed first lateral surface. In some embodiments, the first graphene layer defines a first vertical plane parallel to the exposed first lateral surface. Thereafter, in some embodiments, a first nanobar is formed on the first graphene layer, where the first nanobar extends in a first direction normal to the first vertical plane defined by the first graphene layer.

Abstract: A method for programming a non-volatile resistive memory including a plurality of non-volatile resistive memory cells, each memory cell being able to switch in a reversible manner between a low resistance state in which the memory cell has an electrical resistance value lower than a first resistance threshold; and a high resistance state in which the memory cell has an electrical resistance value greater than the first resistance threshold; the programming method including determining the first resistance threshold carried out periodically during the lifetime of the resistive memory.

Abstract: A circuit is disclosed that includes a first electrode, a second electrode and a plurality of quantum dot devices disposed between the first electrode and the second electrode. An impedance is coupled to the second electrode and has a value selected to conduct or block conduction of current when a coherent electron conduction band is formed by one or more of the quantum dot devices, such as with quantum dot devices in an adjacent circuit.

Abstract: The method for fabricating a field-effect transistor comprises a step of producing a sacrificial gate and first and second spacers covering first, second and third parts of successive first to fifth semiconductor nanowires of a stack. The fabricating method comprises a step of forming a channel area of the transistor, which channel area is compressively stressed and distinct from the second part of the third nanowire. The channel area is connected to a source electrode of the transistor by the first part of the second nanowire, and to a drain electrode of the transistor by the third part of the second nanowire.

Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A source/drain region is connected with a channel layer, and a gate structure extends across the channel layer. The channel layer is composed of a two-dimensional material.

Abstract: A semiconductor device includes a source/drain feature disposed over a substrate. The source/drain feature includes a first nanowire, a second nanowire disposed over the first nanowire, a cladding layer disposed over the first nanowire and the second nanowire and a spacer layer extending from the first nanowire to the second nanowire. The device also includes a conductive feature disposed directly on the source/drain feature such that the conductive feature physically contacts the cladding layer and the spacer layer.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a plurality of first gates disposed on the quantum well stack; a plurality of pairs of spacers, each pair of spacers disposed on opposites sides of an associated first gate, wherein each spacer in a pair has a curved surface that curves away from the associated first gate; and a plurality of second gates disposed on the quantum well stack, wherein the curved surface of each spacer is adjacent to one of the second gates such that at least a portion of each second gate is shaped complementarily to the curved surface of an adjacent spacer.

Abstract: A method of forming a semiconductor device that includes providing a first stack of nanosheets having a first thickness and a second stack of nanosheets having a second thickness; and forming a oxide layer on the first and second stack of nanosheets. The oxide layer fills a space between said nanosheets in the first stack, and is conformally present on the nanosheets in the second stack. The method further includes forming a work function metal layer on the first and second stack of nanosheets. In some embodiments, the work function metal layer is present on only exterior surfaces of the first stack to provide a single gate structure and is conformally present about an entirety of the nanosheets in the second stack to provide a multiple gate structure.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; and one or more gates disposed on the fin. In some such embodiments, the one or more gates may include first, second, and third gates. Spacers may be disposed on the sides of the first and second gates, such that a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate. The third gate may be disposed on the fin between the first and second gates and extend between the first and second spacers.

Abstract: An enhancement mode GaN transistor is provided, which includes a GaN layer, a quantum well structure, a gate, a source a drain and a first barrier layer. The quantum well structure is disposed on the upper surface of the GaN layer. The gate is disposed on the quantum well structure. The source is disposed on one end of the upper surface of the GaN layer. The drain is disposed on the other end of the upper surface of the GaN layer. The first barrier layer is disposed on the upper surface of the GaN layer and extends to the lateral surfaces of the quantum well structure.

Abstract: Example embodiments relate to germanium nanowire fabrication. One embodiment includes a method of forming a semiconductor device that includes at least one Ge nanowire. The method includes providing a semiconductor structure that includes at least one, the at least one fin including a stack of at least one Ge layer alternative with SiGe layers. The method also includes at least partially oxidizing the SiGe layer into SiGeOx. Further, the method includes capping the fin with a dielectric material. In addition, the method includes annealing. Still further, the method includes selectively removing the dielectric material and the SiGeOx.

Abstract: In a standard cell including nanowire FETs, pads connected to nanowires are arranged at a predetermined pitch in X direction along which the nanowires extend. A cell width of the standard cell is an integral multiplication of the pitch. In a case where the standard cell is arranged to constitute the layout of a semiconductor integrated circuit device, the pads are regularly arranged in the X direction.

Abstract: A method for forming three-dimensional magnetic memory arrays by forming crystalized silicon structures from amorphous structures in the magnetic memory array, wherein the temperature needed to crystalize the amorphous silicon is lower than the temperature budget of the memory element so as to avoid damage to the memory element. An amorphous silicon is deposited, followed by a layer of Ti or Co. An annealing process is then performed which causes the Ti or Co to form TiSi2 or CoSi2 and also causes the underlying amorphous silicon to crystallize.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a gate above the fin; and a material on side faces of the fin; wherein the fin has a width between its side faces, and the fin is strained in the direction of the width.

Abstract: A back-illuminated single-photon avalanche diode (SPAD) image sensor includes a sensor wafer stacked vertically over a circuit wafer. The sensor wafer includes one or more SPAD regions, with each SPAD region including an anode gradient layer, a cathode region positioned adjacent to a front surface of the SPAD region, and an anode avalanche layer positioned over the cathode region. Each SPAD region is connected to a voltage supply and an output circuit in the circuit wafer through inter-wafer connectors. Deep trench isolation elements are used to provide electrical and optical isolation between SPAD regions.

Abstract: A device includes a first semiconductor layer; a portion of a second semiconductor layer disposed on the first semiconductor layer; and a third semiconductor layer including a first region disposed on the portion of the second semiconductor layer and a second region disposed on the first semiconductor layer. A thickness of the first region is less than a predefined thickness. The device also includes an etch stop layer disposed on the third semiconductor layer; a plurality of distinct portions of a fourth semiconductor layer disposed on the etch stop layer and exposing one or more distinct portions of the etch stop layer over the portion of the second semiconductor layer; and a plurality of distinct portions of a superconducting layer disposed on the plurality of distinct portions of the fourth semiconductor layer and the exposed one or more distinct portions of the etch stop layer.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphed barrier layer. The present disclosure provides a method of forming a graphed barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphed barrier layers can be selected by varying the thickness of the amorphous carbon layer.

Abstract: A vertical transistor device includes a vertically oriented channel semiconductor structure, a bottom source/drain (S/D) region, a top source/drain (S/D) region, and a gate structure positioned around the vertically oriented channel semiconductor structure, above the bottom source/drain (S/D) region, and below the top source/drain (S/D) region. The gate structure includes a gate electrode and a gate insulation layer positioned between the gate electrode and at least a portion of the vertically oriented channel semiconductor structure. A top spacer is positioned between the gate electrode and at least a portion of the top source/drain (S/D) region, a bottom spacer is positioned between the gate electrode and at least a portion of the bottom source/drain (S/D) region, and a gate cap is positioned around an outer perimeter surface of the gate structure, wherein the top spacer, the bottom spacer, and the gate cap all include a same insulating material.

Abstract: A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer.

Abstract: A method for producing the photoelectric conversion element includes, in carbon nanotubes including semiconducting carbon nanotubes having different chiralities from each other and metallic carbon nanotubes, changing a chirality distribution in the semiconducting carbon nanotubes, separating the carbon nanotubes into the semiconducting carbon nanotubes and the metallic carbon nanotubes after changing the chirality distribution, covering the semiconducting carbon nanotubes with a polymer after performing separating, and forming a photoelectric conversion film including the semiconducting carbon nanotubes between a pair of electrodes after performing covering with the polymer.

Abstract: Nanoscale field-emission devices are presented, wherein the devices include at least a pair of electrodes separated by a gap through which field emission of electrons from one electrode to the other occurs. The gap is dimensioned such that only a low voltage is required to induce field emission. As a result, the emitted electrons energy that is below the ionization potential of the gas or gasses that reside within the gap. In some embodiments, the gap is small enough that the distance between the electrodes is shorter than the mean-free path of electrons in air at atmospheric pressure. As a result, the field-emission devices do not require a vacuum environment for operation.

Abstract: The present invention provides VFET device designs for top contact resistance measurement. In one aspect, a method of forming a VFET test structure includes: etching fins in a substrate (for active and sensing devices); forming bottom source/drains at a base of the fins; forming a STI region that isolates the bottom source/drains of the active device from that of the sensing device; forming a gate surrounding each of the fins; forming top source/drains over the gate, wherein the top source/drains of the active device and that of the sensing device are merged; and forming contacts to i) the bottom source/drains of the active device, ii) the top source/drains of the active device, and iii) the bottom source/drains of the sensing device. A test structure formed by the method as well as techniques for use thereof for measuring contact resistance are also provided.

Abstract: A semiconductor structure includes a nanosheet stack disposed on a base. The nanosheet stack includes one or more first nanosheet layers and one or more second nanosheet layers. Each of the one or more first nanosheet layers includes a first material and each of the one or more second nanosheet layers includes a second material different from the first material. Each of the one or more first nanosheet layers further includes outer portions of a third material converted from the first material. The outer portions are inner spacers.

Abstract: Embodiments are directed to a method of fabricating a semiconductor device. A non-limiting example of the method includes performing fabrication operations to form a nanosheet field effect transistor device on a substrate. The fabrication operations include, forming a channel stack over the substrate, wherein the channel stack include stacked and spaced apart channel nanosheets. A metal gate is formed adjacent to end regions of the channel stack and around and between the stacked and spaced apart channel nanosheets. A permanent dummy gate is formed above the channel stack.

Abstract: A stacked vertical field effect transistor that has enhanced drive current is provided. The stacked vertical field effect transistor includes a lower functional gate structure located adjacent sidewall surfaces of a lower channel portion of a semiconductor channel material pillar. An upper functional gate structure is located above the lower functional gate structure and adjacent sidewall surfaces of an upper channel portion of the semiconductor channel material pillar. A bottom source/drain region is located beneath the lower functional gate structure, a middle source/drain region is located between the lower functional gate structure and the upper functional gate structure, and a top source/drain region is located above the upper functional gate structure.

Abstract: A semiconductor device includes: a substrate; a p-type GaN layer that is formed above the substrate, and includes GaN containing p-type impurities; and a Ti film formed on a surface of the p-type GaN layer. The Ti film includes a Ti film containing no nitrogen and a nitrogen-containing Ti film that is less chemically active than such Ti film. The nitrogen-containing Ti film continuously surrounds an outer periphery of the Ti film containing no nitrogen in a planar view.

Abstract: A method of forming a fin field effect transistor device is provided. The method includes forming a plurality of vertical fins on a substrate. The method further includes forming a bottom source/drain layer adjacent to the plurality of vertical fins, and growing a doped layer on the bottom source/drain layer and sidewalls of the plurality of vertical fins. The method further includes forming a dummy gate liner on the doped layer and the bottom source/drain layer, and forming a dummy gate fill on the dummy gate liner. The method further includes forming a protective cap layer on the dummy gate fill, and removing a portion of the protective cap layer to expose a top surface of the plurality of vertical fins.

Abstract: Described herein is a device that includes an alkyl ammonium metal halide perovskite layer, and a nanostructured semiconductor layer in physical contact with the alkyl ammonium metal halide perovskite layer. The alkyl ammonium metal halide perovskite layer may include methyl ammonium cations. The alkyl ammonium metal halide perovskite layer may include anions of at least one of chlorine, bromine, astatine, and/or iodine. The alkyl ammonium metal halide perovskite layer may include cations of a metal in a 2+ valence state. The metal may include at least one of lead, tin, and/or germanium.

Abstract: Transistor devices having an indium-containing ternary or greater III-V compound active channels, and processes for the fabrication of the same, may be formed that enables improved carrier mobility when fabricating fin shaped active channels, such as those used in tri-gate or gate all around (GAA) devices. In one embodiment, an indium-containing ternary or greater III-V compound may be deposited in narrow trenches on a reconstructed upper surface of a sub-structure, which may result in a fin that has indium rich side surfaces and an indium rich bottom surface. These indium rich surfaces will abut a gate oxide of a transistor and may result in high electron mobility and an improved switching speed relative to conventional homogeneous compositions of indium-containing ternary or greater III-V compound active channels.