Abstract: According to one embodiment, a semiconductor memory device is disclosed. The device includes MOSFET1 and MOSFET2 arranged in a first direction, variable resistive element (hereafter R1) above MOSFET1 and MOSFET2, a lower end of the R1 being connected to drains of MOSFET1 and MOSFET2, MOSFET3 and MOSFET4 arranged in the first direction, variable resistive element (hereafter R2) above MOSFET3 and MOSFET4, and a lower end of the R2 being connected to drains of MOSFET3 and MOSFET4. The device further includes first wiring line extending in the first direction and connected to sources of MOSFET1 and MOSFET2, second wiring line extending in the first direction and connected to sources of MOSFET3 and MOSFET4, upper electrode connecting upper end of the R1 and upper end of the R2, and third wiring line extending in the first direction and connected to the upper electrode.

Abstract: Provided is an electronic device that generates an output signal corresponding to an input signal, comprising a signal processing section that receives the input signal and outputs the output signal corresponding to the input signal, and a floating electrode that accumulates a charge by being irradiated by an electron beam. The signal processing section adjusts electric characteristics of the output signal according to a charge amount accumulated in the floating electrode, and includes a transistor formed on the semiconductor substrate between an input terminal that receives the input signal and an output terminal that outputs the output signal.

Abstract: The present invention provides the multifunctional biological and biochemical sensor technology based on the integration of ZnO nanotips with bulk acoustic wave (BAW) devices, particularly, quartz crystal microbalance (QCM) and thin film bulk acoustic wave resonator (TFBAR). ZnO nanotips provide giant effective surface area and strong bonding sites. Furthermore, the controllable wettability of ZnO nanostructured surface dramatically reduces the liquid consumption and enhances the sensitivity of the biosensor device.

Abstract: The infrared sensor (1) includes a base (10), and an infrared detection element (3) formed over a surface of the base (10). The infrared detection element (3) includes an infrared absorption member (33) in the form of a thin film configured to absorb infrared, a temperature detection member (30) configured to measure a temperature difference between the infrared absorption member (33) and the base (10), and a safeguard film (39). The infrared element (3) is spaced from the surface of the base (10) for thermal insulation. The temperature detection member (30) includes a p-type polysilicon layer (35) formed over the infrared absorption member (33) and the base (10), an n-type polysilicon layer (34) formed over the infrared absorption member (33) and the base (10) without contact with the p-type polysilicon layer (35), and a connection layer (36) configured to electrically connect the p-type polysilicon layer (35) to the n-type polysilicon layer (34).

Abstract: The present invention relates to a photodiode of an image sensor using a three-dimensional multi-layer substrate, and more particularly, to a method of implementing a buried type photodiode and a structure thereof, and a trench contact method for connecting a photodiode in a multi-layer substrate and a transistor for signal detection.

Abstract: A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantilever

Abstract: In certain embodiments, a field effect transistor (FET) can include a substrate, a source electrode, a drain electrode, a ferroelectric material layer, a first gate electrode, and a second gate electrode to maintain an optimal polarization state of the ferroelectric material layer. In other embodiments, a FET can include a film, first and second gates on the film, a ferroelectric material layer covering the film and gates, an insulating layer substantially covering the ferroelectric material layer, a source and a drain on the insulating layer, and a pentacene layer.

Abstract: In the method for manufacturing the infrared image sensor, first, a thermal insulation layer (33) is made by forming a silicon dioxide film (31) on a first area (A1) followed by forming a silicon nitride film (32) on the silicon dioxide film (31). The silicon dioxide film (31) has compression stress. The first area (A1) is reserved in a surface of a silicon substrate (1) for forming an infrared detection element (3). The silicon nitride film (32) has tensile stress. Next, a well region (41) is formed in a second area (A2) reserved in the surface of the silicon substrate (1) for forming a MOS transistor (4). After that, a gate insulation film (45) of the MOS transistor (4) is formed by means of thermal oxidation of the surface of the silicon substrate (1). Thereafter, a temperature detection element (36) is formed on the thermal insulation layer (33). Subsequently, a drain region (43) and a source region (44) of the MOS transistor (4) are formed in the well region (41).

Abstract: A semiconductor device with an integrated circuit on a semiconductor substrate comprises a Hall effect sensor in a first active region and a lateral high voltage MOS transistor in a second active region. The semiconductor device of the present invention is characterized in that the structure of the integrated Hall effect sensor is strongly related with the structure of a high-voltage DMOS transistor. The integrated Hall effect sensor is in some features similar to a per se known high-voltage DMOS transistor having a double RESURF structure. The control contacts of the Hall effect sensor correspond to the source and drain contacts of the high-voltage DMOS transistor. The semiconductor device of the present invention allows a simplification of the process integration.

Abstract: An image sensor includes a charge storage portion for storing and transferring signal charges, a first electrode for forming an electric field storing the signal charges in the charge storage portion, a charge increasing portion for increasing the signal charges stored in the charge storage portion and a second electrode for forming another electric field increasing the signal charges in the charge increasing portion, wherein the quantity of the signal charges storable in the charge storage portion is not less than the quantity of the signal charges storable in the charge increasing portion.

Abstract: The invention relates to an electronic device having a semiconductor die comprising at least one RF-transistor (RFT) occupying a total RF-transistor active area (ARFT) on the die (DS). The total RF-transistor active area (ARFT) includes at least one transistor channel (C) having a channel width (W) and a channel length (L), and at least one bias cell (BC) for biasing the RF-transistor (RFT). The total bias cell active area (ABC) includes at least one transistor channel (C) having a channel width (W) and a channel length (L). The at least one bias cell (BC) occupies a total bias cell active area (ABC) on the die (SD). The total RF-transistor active area (ARFT) is substantially greater than the total bias cell active area (ABC). The total bias cell active area (ABC) has a common centre of area (COABC). The total RF-transistor active area (ARFT) has a common centre of area (COARF).

Abstract: Provided is a method of detecting the presence of a target bio-molecule or a concentration of the bio-molecule using a field effect transistor. The method includes: contacting a first sample having a first target bio-molecule with a reference electrode of a field effect transistor; measuring a first electric signal change of the field effect transistor; contacting a second sample with a sensing surface of the same field effect transistor; measuring a second electric signal change of the field effect transistor; and comparing the first electric signal with the second electric signal.

Abstract: A flexible display substrate includes: a thin film transistor on the flexible substrate, the thin film transistor including a gate electrode, a gate insulating layer insulating the gate electrode, a channel layer on the gate insulating layer, a source electrode connected with the channel layer, and a drain electrode connected with the channel layer; a first stress absorbing layer below the thin film transistor; a first protection layer on the first stress absorbing layer; a second stress absorbing layer on the thin film transistor; a second protection layer on the second stress absorbing layer; and a pixel electrode on the second protection layer, the pixel electrode being connected with the drain electrode.

Abstract: A single chip wireless sensor comprises a microcontroller connected by a transmit/receive interface to a wireless antenna. The microcontroller is also connected to an 8 kB RAM, a USB interface, an RS232 interface, 64 kB flash memory, and a 32 kHz crystal. The device senses humidity and temperature, and a humidity sensor is connected by an 18 bit ?? A-to-D converter to the microcontroller and a temperature sensor is connected by a 12 bit SAR A-to-D converter to the microcontroller. The device is an integrated chip manufactured in a single process in which both the electronics and sensor components are manufactured using standard CMOS processing techniques, applied to achieve both electronic and sensing components in an integrated process.

Abstract: An MEMS sensor constructed on a base chip and having a capacitive mode of operation is disclosed. The MEMS sensor has a patterned layer construction applied on the base chip. A cutout is produced in the layer construction, the moveable electrode, for example a membrane, being arranged in said cutout. The cutout is spanned by a covering layer, which bears on the layer construction around the cutout and comprises the back electrode.

Abstract: A package of a MEMS microphone is suitable for being mounted on a printed circuit board. The package includes a substrate, at least one MEMS microphone, and a conductive sealing element. The MEMS microphone is arranged on the substrate, and electrically connected to a conductive layer on a bottom surface of the substrate. The conductive sealing element is arranged on the substrate and around the MEMS microphone for connecting the printed circuit board, and constructs an acoustic housing with the printed circuit board and the substrate. The acoustic housing has at least one acoustic hole passing through the substrate. The acoustic hole has a metal layer on the inner wall thereof for connecting the conductive layer on the bottom surface of the substrate to another conductive layer on the top surface of the substrate.

Abstract: A light-receiving element includes: a first-conductivity-type semiconductor region configured to be formed over an element formation surface; a second-conductivity-type semiconductor region configured to be formed over the element formation surface; an intermediate semiconductor region configured to be formed over the element formation surface between the first-conductivity-type semiconductor region and the second-conductivity-type semiconductor region, and have an impurity concentration lower than impurity concentrations of the first-conductivity-type semiconductor region and the second-conductivity-type semiconductor region. The light-receiving element further includes: a first electrode configured to be electrically connected to the first-conductivity-type semiconductor region; a second electrode configured to be electrically connected to the second-conductivity-type semiconductor region; and a control electrode configured to be formed in an opposed area that exists on the element formation surface.

Abstract: A semiconductor device which detects a power level of a radio-frequency signal includes: a switch FET including: a semiconductor layer; a source electrode and a drain electrode; a first gate electrode; a second gate electrode formed between the first gate electrode and the drain electrode and on the semiconductor layer, each of the first gate electrode and the second gate electrode being in Schottky contact with the semiconductor layer, and the source electrode receiving the radio-frequency signal; a resistor having one end electrically connected to the first gate electrode and an other end electrically connected to the drain electrode via a capacitor; and a power detection terminal electrically connected to a connecting point between the resistor and the capacitor.

Abstract: A process is provided for fabricating rounded three-dimensional germanium active channels for transistors and sensors. For forming sensors, the process comprises providing a crystalline silicon substrate; depositing an oxide mask on the crystalline silicon substrate; patterning the oxide mask with trenches to expose linear regions of the silicon substrate; epitaxially grow germanium selectively in the trenches, seeded from the silicon wafer; optionally etching the SiO2 mask partially, so that the cross section resembles a trapezoid on a stem; and annealing at an elevated temperature. The annealing process forms the rounded channel. For forming transistors, the process further comprises depositing and patterning a gate oxide and gate electrode onto this structure to form the gate stack of a MOSFET device; and after patterning the gate, implanting dopants into the source and drain located on the parts of the germanium cylinder on either side of the gate line.

Abstract: An electrochromic display is disclosed which comprises an array-side substrate (10) wherein a TFT (14) and a pixel electrode (15) connected with the TFT (14) are formed, a color filter-side substrate (50) wherein a counter electrode (53) is formed, and an electrolyte layer (80) injected between the array-side substrate (10) and the color filter-side substrate (50). In this electrochromic display, the TFT (14) is formed to have an area not less than 30% of the area of the pixel, thereby supplying a larger current. Consequently, oxidation-reduction reaction in the electrochromic phenomenon proceeds at a higher rate, thereby enabling a high-speed response.

Abstract: A method for producing a device including at least one integrated circuit and at least one N/MEMS. The method produces the N/MEMS in at least one upper layer arranged at least above a first section of a substrate, produces the integrated circuit in a second section of the substrate and/or in a semiconductor layer arranged at least above the second section of the substrate, and further produces a cover encapsulating the N/MEMS from at least one layer used for production of a gate in the integrated circuit and/or for producing at least one electrical contact of the integrated circuit.

Abstract: The present invention provides an InSb-based switching device operating at room temperature by using a magnetic field controlled avalanche process for applying to magneto-logic elements. A switching device of one embodiment includes a p-type semiconductor layer; an n-type semiconductor layer; and contact layers disposed on one of the p-type and n-type semiconductor layers, the p-type semiconductor layer being in contact with the n-type semiconductor layer such that a current can be applied through the contact layers to the p-type and n-type semiconductor layers to cause a current flow from one of the contact layers to the p-type and n-type semiconductor layers and from the p-type and n-type semiconductor layers to the other of the contact layers, whereby the current flow can be controlled by an intensity of a magnetic field applied to the p-type and n-type semiconductor layers substantially perpendicularly thereto.

Abstract: A display device including a first substrate, a first subpixel electrode, a second subpixel electrode corresponding to the first substrate, a second substrate and a common electrode formed on the second substrate is provided. The first subpixel electrode and the second subpixel electrode are formed on the first substrate. The second subpixel electrode is spaced apart from the first subpixel electrode. The common electrode has a first cutout and a second cutout. The first cutout is disposed over the first subpixel electrode and the second cutout is disposed over the second subpixel electrode. At least a portion of the first cutout has a first width and at least a portion of the second cutout has a second width different from the first width. The first width is larger than the second width in one embodiment. This structure enhances the aperture ratio and the brightness of the display device. Failures such as a residual image, stain or fingerprint may be reduced and the picture quality is improved.

Abstract: A sensor is disclosed. A representative sensor includes a silicon substrate having a porous silicon region. A portion of the porous silicon region has a front contact is disposed thereon. The contact resistance between the porous silicon region and the front contact is between about 10 ohms and 100 ohms.

Abstract: A commercially mass-produced ultra-miniaturized solid state system for using an ultraminiaturized atomic or molecular integrated circuit with gigabit memory and picosecond speed to automatically perform self-optimizing tasks selected from the group consisting of searching, tracking, teletraining, telelearning, telemedical diagnosis or treatment, and implanting knowledge or skill

Abstract: A magnetoresistive memory element has a free layer, and a write current path aligned with a free layer plane. The memory element has a pinned layer with a magnetization direction aligned with that of the free layer. A barrier layer is disposed between the free layer and the pinned layer. The free, barrier and pinned layers together form a layer stack that has a read current path that extends through the layer stack and that is not aligned with the write current path in the free layer.

Abstract: The invention relates to an electronic device having a semiconductor die comprising at least one RF-transistor (RFT) occupying a total RF-transistor active area (ARFT) on the die (DS). The total RF-transistor active area (ARFT) includes at least one transistor channel (C) having a channel width (W) and a channel length (L), and at least one bias cell (BC) for biasing the RF-transistor (RFT). The total bias cell active area (ABC) includes at least one transistor channel (C) having a channel width (W) and a channel length (L). The at least one bias cell (BC) occupies a total bias cell active area (ABC) on the die (SD). The total RF-transistor active area (ARFT) is substantially greater than the total bias cell active area (ABC). The total bias cell active area (ABC) has a common centre of area (COABC). The total RF-transistor active area (ARFT) has a common centre of area (COARF).

Abstract: MEMS devices (such as interferometric modulators) may be fabricated using a sacrificial layer that contains a heat vaporizable polymer to form a gap between a moveable layer and a substrate. One embodiment provides a method of making a MEMS device that includes depositing a polymer layer over a substrate, forming an electrically conductive layer over the polymer layer, and vaporizing at least a portion of the polymer layer to form a cavity between the substrate and the electrically conductive layer.

Abstract: Provided are a thermistor with 3 terminals, a thermistor-transistor including the thermistor, a circuit for controlling heat of a power transistor using the thermistor-transistor, and a power system including the circuit. The circuit includes: a thermistor-transistor which comprises a thermistor having a resistance decreasing with an increase in temperature and a control transistor connected to the thermistor; and at least one power transistor which is connected to a driving device to control a supply of power to the driving device, wherein the thermistor-transistor is adhered to one of a surface and a heat-emitting part of the at least one power transistor and is connected to one of a base, a gate, a collector, and a drain of the at least one power transistor to decrease or block a current flowing in the at least one power transistor when the temperature of the at least one power transistor rises, so as to prevent the power transistor from heating up.

Abstract: The invention concerns a sensor with silicon-containing components from whose sensitive detection element electrical signals relevant to a present analyte can be read out by means of a silicon semiconductor system. The invention is characterized in that the silicon-containing components are covered with a layer made of hydrophobic material in order to prevent unwanted signals caused by moisture.

Abstract: A sensor comprising a semiconductor film having a plurality of mesopores and containing an oxide, and electrodes electrically connected to the semiconductor film, wherein at least part of surfaces in the mesopores is coated with an organic material.

Abstract: A device including a transistor that includes a source region; a drain region; and a channel region, wherein the channel region electrically connects the source region and the drain region along a channel axis; and a memory cell, wherein the memory cell is disposed adjacent the drain region so that the channel axis runs through the memory cell.

Abstract: Embodiments relate to an image sensor having a gate spacer and a fabricating method by which damage in a photodiode area can be prevented. Embodiments relate to a method of fabricating an image sensor including forming a gate electrode over a substrate having a prescribed photodiode area. A first oxide layer, a nitride layer, and a second oxide layer may be formed over the substrate including the gate electrode. A photoresist pattern may be formed over the substrate to open the photodiode area centering on the gate electrode. A transformed nitride layer may be formed by selectively carrying out nitridation on the second oxide layer formed over the photodiode area centering on the gate electrode using the photoresist pattern as a mask. The photoresist mask pattern may be removed. A spacer may be formed over one side of the gate electrode by carrying out blank etch on the first oxide layer, the nitride layer, the transformed nitride layer, and the second oxide layer.

Abstract: The present invention is a biosensor apparatus that includes a substrate, a source on one side of the substrate, a drain spaced from the source, a conducting channel between the source and the drain, an insulator region, and receptors on a gate region for receiving target material. The receptors are contacted for changing current flow between the source and the drain. The source and the drain are relatively wide compared to length between the source and the drain through the conducting channel.

Abstract: An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the electromigration problem that is exhibited by prior art interconnect structures, are provided. In accordance with the present invention, a grain growth promotion layer, which promotes the formation of a conductive region within the interconnect structure that has a bamboo microstructure and an average grain size of larger than 0.05 microns is utilized. The inventive structure has improved performance and reliability.

Abstract: A semiconductor device using a MEMS technology according to an example of the present invention comprises a cavity, a lower electrode provided in a lower part of the cavity, an actuator provided in an upper part or inside of the cavity, an upper electrode connected to the actuator, and a conductive layer in contact with the lower electrode outside the cavity via a contact hole whose bottom face is provided above an upper face of the lower electrode in the cavity.

Abstract: Neutron detectors including one or more gamma shields over memory dies and methods of making the neutron detectors are provided. The neutron detectors can contain two or more memory dies, neutron-reactant layers over the two or more memory dies, and one or more gamma shields over at least a portion of or an entire of the two or more memory dies. By containing the gamma shield over the at least a portion of or an entire of the two or more memory dies, the neutron detector can detect and discriminate neutrons in the presence of gamma rays.

Abstract: A device capable of exhibiting the extraordinary magnetoresistance (EMR) effect includes an elongate channel formed of silicon. A conductor comprising heavily doped silicon is connected to the channel along one side of the channel so as to provide a shunt. A gate arrangement including a gate electrode is provided on the channel. Applying a bias of appropriate polarity and sufficient magnitude to the gate electrode results in the formation of an inversion layer in the channel.

Abstract: A magnetoresistance device has a channel extending between first and second ends in a first direction comprising non-ferromagnetic semiconducting material, such as silicon, a plurality of leads connected to and spaced apart along the channel, a gate structure for applying an electric field to the channel in a second direction which is substantially perpendicular to the first direction so as to form an inversion layer in the channel and a face which lies substantially in a plane defined by the first and second directions and which is configured such that an edge of the channel runs along the face.

Abstract: A cooling device for an electrical power unit of electrically operated vehicles, comprising at least one power section and at least one control section. A first cooling circuit containing a heat exchanger with a low coolant temperature is provided mainly for cooling elements of the control sections, and a further cooling circuit with a higher coolant temperature is provided mainly for cooling elements of the power sections.

Abstract: A single chip wireless sensor (1) comprises a microcontroller (2) connected by a transmit/receive interface (3) to a wireless antenna (4). The microcontroller (2) is also connected to an 8 kB RAM (5), a USB interface (6), an RS232 interface (8), 64 kB flash memory (9), and a 32 kHz crystal (10). The device (1) senses humidity and temperature, and a humidity sensor (11) is connected by an 18 bit ?? A-to-D converter (12) to the microcontroller (2) and a temperature sensor (13) is connected by a 12 bit SAR A-to-D converter (14) to the microcontroller (2). The device (1) is an integrated chip manufactured in a single process in which both the electronics and sensor components are manufactured using standard CMOS processing techniques, applied to achieve both electronic and sensing components in an integrated process.

Abstract: By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.

Abstract: A single chip wireless sensor (1) comprises a microcontroller (2) connected by a transmit/receive interface (3) to a wireless antenna (4). The microcontroller (2) is also connected to an 8 kB RAM (5), a USB interface (6), an RS232 interface (8), 64 kB flash memory (9), and a 32 kHz crystal (10). The device (1) senses humidity and temperature, and a humidity sensor (11) is connected by an 18 bit ?? A-to-D converter (12) to the microcontroller (2) and a temperature sensor (13) is connected by a 12 bit SAR A-to-D converter (14) to the microcontroller (2). The device (1) is an integrated chip manufactured in a single process in which both the electronics and sensor components are manufactured using standard CMOS processing techniques, applied to achieve both electronic and sensing components in an integrated process.

Abstract: A magnetic tunnel junction paired to a semiconductor field-effect transistor is described. In one embodiment, there is a circuit that comprises at least one semiconductor field-effect transistor and a magnetic tunnel junction coupled to the at least one semiconductor field-effect transistor. The magnetic tunnel junction has a control line that is configured to control operational characteristics of the at least one semiconductor field-effect transistor.

Abstract: Example embodiments provide a unit pixel, an image sensor containing unit pixels, and a method of fabricating unit pixels. The unit pixel may include a semiconductor substrate, photoelectric transducers formed within the semiconductor substrate, multi-layered wiring layers formed on a frontside of the semiconductor substrate, inner lenses formed on a backside of the semiconductor substrate corresponding to the photoelectric transducers, and microlenses formed above the inner lenses.

Abstract: A transistor (1) has a FET (2) and a temperature sensing diode (4) integrated within it. Gate drive circuit (12) is arranged to switch off FET (2) and in this case biasing circuit (14) drives a constant current through the diode (4). The voltage across the diode (4) is measured by voltage sensor (15) which provides a measure of the temperature of the FET.

Abstract: Disclosed is an image sensor. The image sensor includes a semiconductor substrate including a lower interconnection, a plurality of upper interconnection sections protruding upward from the semiconductor substrate, a first trench disposed between the upper interconnection sections such that the upper interconnection sections are spaced apart from each other, a bottom electrode disposed on an outer peripheral surfaces of the upper interconnection sections, a first conductive layer disposed on an outer peripheral surface of the bottom electrode, an intrinsic layer disposed on the semiconductor substrate including the first conductive layer and the first trench, and having a second trench on the first trench, a second conductive layer disposed on the intrinsic layer and having a third trench on the second trench, a light blocking part disposed in the third trench, and a top electrode disposed on the light blocking part and the second conductive layer.

Abstract: An image sensor includes a charge storage portion for storing and transferring signal charges, a first electrode for forming an electric field storing the signal charges in the charge storage portion, a charge increasing portion for increasing the signal charges stored in the charge storage portion and a second electrode for forming another electric field increasing the signal charges in the charge increasing portion, wherein the quantity of the signal charges storable in the charge storage portion is not less than the quantity of the signal charges storable in the charge increasing portion.

Abstract: A gas-sensing semiconductor device is fabricated on a silicon substrate having a thin silicon oxide insulating layer in which a resistive heater made of a CMOS compatible high temperature metal is embedded. The high temperature metal is tungsten. The device includes at least one sensing area provided with a gas-sensitive layer separated from the heater by an insulating layer. As one of the final fabrication steps, the substrate is back-etched so as to form a thin membrane in the sensing area. Except for the back-etch and the gas-sensitive layer formation, that are carried out post-CMOS, all other layers, including the tungsten resistive heater, are made using a CMOS process employing tungsten metallisation. The device can be monolithically integrated with the drive, control and transducing circuitry using low cost CMOS processing. The heater, the insulating layer and other layers are made within the CMOS sequence and they do not require extra masks or processing.

Abstract: A semiconductor power transistor includes a drift region of a first conductivity type and a well region of a second conductivity type in the drift region such that the well region and the drift region form a pn junction therebetween. A first highly doped silicon region of the first conductivity type is in the well region, and a second highly doped silicon region is in the drift region. The second highly doped silicon region is laterally spaced from the well region such that upon biasing the transistor in a conducting state, a current flows laterally between first and second highly doped silicon regions through the drift region. Each of a plurality of trenches extending into the drift region perpendicular to the current flow includes a dielectric layer lining at least a portion of the trench sidewalls and at least one conductive electrode.