Physical Deformation (e.g., Strain Sensor, Acoustic Wave Detector) Patents (Class 257/254)
  • Patent number: 10175133
    Abstract: A sensor comprises a sensor layer comprising a ceramic material; an adhesion layer comprising chromium, the adhesion layer adhered to one or more portions of a liquid facing surface of the sensor layer; and an isolator film comprising a polymer, the isolator film overlaying a liquid facing surface of the adhesion layer. The isolator film may be used to protect the sensor from corrosive and high temperature fluids, for example to protect the sensor from long term exposure to hot water between 85° C. and 100° C.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: January 8, 2019
    Assignee: Entegris, Inc.
    Inventors: Richard A. Cooke, George Gonnella, Sung In Moon, Charles W. Extrand, John E. Pillion
  • Patent number: 10170262
    Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are provided. The method of forming a MEMS structure includes forming fixed actuator electrodes and a contact point on a substrate. The method further includes forming a MEMS beam over the fixed actuator electrodes and the contact point. The method further includes forming an array of actuator electrodes in alignment with portions of the fixed actuator electrodes, which are sized and dimensioned to prevent the MEMS beam from collapsing on the fixed actuator electrodes after repeating cycling. The array of actuator electrodes are formed in direct contact with at least one of an underside of the MEMS beam and a surface of the fixed actuator electrodes.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher V. Jahnes, Anthony K. Stamper
  • Patent number: 10152164
    Abstract: A touch screen, a touch driving circuit and a touch driving method are provided in the disclosure. The touch driving circuit includes multiple cascading shifting registers and selection outputting circuits each connected to a respective shifting register. At least one of the selection outputting circuits is connected to multiple touch electrodes; each of the touch electrodes is connected to one of the selection outputting circuits; and when the shifting register is being scanned and the selection outputting circuit connected to the shifting register is connected to multiple touch electrodes, the selection outputting circuit provides touch driving signals with different frequencies for the touch electrodes connected to the selection outputting circuit simultaneously. The touch driving circuit can simultaneously drive multiple touch electrodes to perform touch detections, thus improving the efficiency of the touch detection.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: December 11, 2018
    Assignees: XIAMEN TIANMA MICRO-ELECTRONICS CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventor: Yizhi Yang
  • Patent number: 10147577
    Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are provided. The method of forming a MEMS structure includes forming fixed actuator electrodes and a contact point on a substrate. The method further includes forming a MEMS beam over the fixed actuator electrodes and the contact point. The method further includes forming an array of actuator electrodes in alignment with portions of the fixed actuator electrodes, which are sized and dimensioned to prevent the MEMS beam from collapsing on the fixed actuator electrodes after repeating cycling. The array of actuator electrodes are formed in direct contact with at least one of an underside of the MEMS beam and a surface of the fixed actuator electrodes.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: December 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher V. Jahnes, Anthony K. Stamper
  • Patent number: 10094724
    Abstract: A pressure sensor which detects variation in pressures, the pressure sensor including a cantilever which is bent according to a pressure difference between the inside and the outside of a cavity in a sensor main body, and an intra-lever gap which is formed on a proximal end portion of the cantilever. The proximal end portion is partitioned into a first support portion and a second support portion by an intra-lever gap in a second direction orthogonal to a first direction in which the proximal end portion and a distal end portion are connected to each other in plan view. A doped layer which is provided on a portion of the first and second support portions forms a first displacement detection portion and a second displacement detection portion. Lengths of the first and second displacement detection portions are shorter than those of the first and second supports along the second direction.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: October 9, 2018
    Assignees: SEIKO INSTRUMENTS INC., THE UNIVERSITY OF TOKYO
    Inventors: Isao Shimoyama, Kiyoshi Matsumoto, Hidetoshi Takahashi, Minh-Dung Nguyen, Takeshi Uchiyama, Manabu Oumi, Yoko Shinohara, Masayuki Suda
  • Patent number: 10096579
    Abstract: Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: October 9, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jaspreet S. Gandhi, Michel Koopmans
  • Patent number: 10054507
    Abstract: An electric device for detecting pressure and a pressure sensor includes an electric current channel arranged to conduct an electric current, wherein the electric current channel is disposed adjacent or proximate to a pressure sensitive structure. Upon the pressure sensitive structure being subjected to a change of an external pressure, the pressure sensitive structure is arranged to manipulate a first electrical characteristic of the electric current channel.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: August 21, 2018
    Assignee: City University of Hong Kong
    Inventors: A. L. Roy Vellaisamy, Qijun Sun, Jiaqing Zhuang
  • Patent number: 9941402
    Abstract: A semiconductor device includes a guard structure located laterally between first and second active areas of a semiconductor substrate. The guard structure includes a first doping region at a front side surface of the substrate and a wiring structure electrically connecting the first doping region to a highly doped portion of a common doping region. The common doping region extends from a backside surface of the substrate to at least a part of the front side surface in contact with the wiring structure. An edge termination doping region laterally surrounds the first and second active areas. The edge termination doping region and the first doping region have a first conductivity type, and the common doping region has a second conductivity type. A resistive connection between the edge termination doping region and the first doping region is present at least during reverse operating conditions of the semiconductor device.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: April 10, 2018
    Assignee: Infineon Technologies AG
    Inventors: Adrian Finney, Dietmar Kotz, Radu Eugen Cazimirovici, Thomas Ostermann
  • Patent number: 9927911
    Abstract: A touch display panel, a fabrication method thereof, a touch display apparatus are provided. The touch display panel includes touch driving electrodes touch driving electrode wires touch driving electrode connection wires. Each column of touch driving electrodes include touch driving electrode blocks, each of the touch driving electrode blocks which is connected with one touch driving electrode wire, different columns of touch driving electrode blocks are connected with different touch driving electrode wires. Each of the touch driving electrode blocks includes a plurality of interruptedly distributed touch driving electrode units that are electrically connected by the touch driving electrode connection wires.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: March 27, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yingming Liu, Xue Dong, Haisheng Wang, Xiaochuan Chen, Xiaoliang Ding, Shengji Yang, Weijie Zhao, Hongjuan Liu, Liguang Deng, Huizhong Zhu, Changfeng Li, Wei Liu, Lei Wang
  • Patent number: 9919917
    Abstract: Disclosed herein an inertial sensor and a method of manufacturing the same. An inertial sensor 100 according to a preferred embodiment of the present invention is configured to include a plate-shaped membrane 110, a mass body 120 that includes an adhesive part 123 disposed under a central portion 113 of the membrane 110 and provided at the central portion thereof and a patterning part 125 provided at an outer side of the adhesive part 123 and patterned to vertically penetrate therethrough, and a first adhesive layer 130 that is formed between the membrane 110 and the adhesive part 123 and is provided at an inner side of the patterning part 125. An area of the first adhesive layer 130 is narrow by isotropic etching using the patterning part 125 as a mask, thereby making it possible to improve sensitivity of the inertial sensor 100.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: March 20, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jong Woon Kim, Won Kyu Jeung
  • Patent number: 9919918
    Abstract: The present disclosure provides a wafer-level bonding packaging method, including: providing a plurality of first wafers and a plurality of second wafers, a to-be-bonded surface of a first wafer being a first to-be-bonded surface, a to-be-bonded surface of a second wafer being a second to-be-bonded surface, and the first to-be-bonded surface including a first region and a second region; forming at least one first bonding structure on the second region; forming at least one second bonding structure on a second to-be-bonded surface, the at least one second bonding structure corresponding to the at least one first bonding structure; and forming a supporting layer on the first region, a height of supporting layer being greater than a height of the first bonding structure and less than a sum of the height of the first bonding structure and a height of the second bonding structure.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: March 20, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Wei Xu
  • Patent number: 9888324
    Abstract: The invention relates to a capacitive MEMS microphone and a method for manufacturing the same. The microphone includes: a substrate; a first dielectric supporting layer on the substrate; a movable sensitive layer formed on the first dielectric supporting layer and having a movable diaphragm extending within the air; a backplate disposed over the movable sensitive layer and spaced from the movable diaphragm; a chamber recessed from and extending through the substrate and the first dielectric supporting layer; and an impact resisting device connecting to the movable diaphragm. The impact resisting device is exposed downwardly and disposed above the chamber. The movable sensitive layer has a number of anchors formed around the movable diaphragm, a number of flexible beams each of which is employed to connect one of the anchors to the movable diaphragm, and a bonding portion connecting to the anchor.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: February 6, 2018
    Assignee: Memsensing Microsystems (Suzhou, China) Co., Ltd.
    Inventors: Wei Hu, Gang Li
  • Patent number: 9798429
    Abstract: This disclosure generally provides an input device that includes a multi-layered capacitive sensor which includes a first layer disposed over a second layer that contains a plurality of sensor electrodes coupled to respective traces. The first and second layers form a capacitive sensing stack where the first layer is between the second layer and a touch surface for interacting with the input object. The first and second layers may be disposed on either the same substrate or different substrates in the stack. In one embodiment, the first layer includes electrically floating electrodes and at least one guard electrode. These components may align with respective components in the second layer. For example, the electrically floating electrodes in the first layer may at least partially cover the sensor electrodes in the second layer.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: October 24, 2017
    Assignee: SYNAPTICS INCORPORATED
    Inventors: Adam Schwartz, Joseph Kurth Reynolds, Bob Lee Mackey, Petr Shepelev
  • Patent number: 9779976
    Abstract: Provided is a thermal type airflow volume meter improving measurement accuracy, a method for manufacturing the same, and an adhesive sheet for use therein, the adhesive sheet divided into at least two or more per adherend and having a thickness of approximately 0.1 mm or less is divided to correspond to a shape of the adherend and generates or increases adhesion or stickiness by external energy.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: October 3, 2017
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Satoshi Ikeo, Toshifumi Sagawa, Ryosuke Doi, Hiroshi Kikuchi, Hideki Mukuno
  • Patent number: 9761566
    Abstract: A method includes forming a semiconductor device comprising a semiconductor die surrounded by a molding material, wherein a contact metal of the semiconductor device has an exposed edge, placing the semiconductor device into a tray having an inner wall and an outer wall, wherein the inner wall is underneath the semiconductor device and between an outer edge of the semiconductor device and an outer edge of bumps of the semiconductor device, depositing a metal shielding layer on the semiconductor device and the tray, wherein the metal shielding layer is in direct contact with the exposed edge of the contact metal and separating the semiconductor device from the tray.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: September 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Po-Hao Tsai, Jing-Cheng Lin, Li-Hui Cheng
  • Patent number: 9756430
    Abstract: A method of fabricating a micro-electrical-mechanical system (MEMS) transducer comprises the steps of forming a membrane on a substrate, and forming a back-volume in the substrate. The step of forming a back-volume in the substrate comprises the steps of forming a first back-volume portion and a second back-volume portion, the first back-volume portion being separated from the second back-volume portion by a step in a sidewall of the back-volume. The cross-sectional area of the second back-volume portion can be made greater than the cross-sectional area of the membrane, thereby enabling the back-volume to be increased without being constrained by the cross-sectional area of the membrane. The back-volume may comprise a third back-volume portion. The third back-volume portion enables the effective diameter of the membrane to be formed more accurately.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: September 5, 2017
    Assignee: Cirrus Logic, Inc.
    Inventors: Anthony Bernard Traynor, Richard Ian Laming, Tsjerk H. Hoekstra
  • Patent number: 9748162
    Abstract: A chip package and a method for forming the same are provided. The method includes: providing a first chip, wherein the first chip comprises a first surface and a second surface, and a first plurality of pads are disposed on the first surface; providing a second chip, wherein the second chip comprises a third surface and a fourth surface, a second plurality of pads are disposed on the third surface; combining the second surface of the first chip and the third surface of the second chip, wherein the second plurality of pads are out of the combination area of the first chip and the second chip; and forming a first insulation layer, wherein the first insulation layer covers the first chip, and is combined with the second chip. Processes of the method are simple, and the chip package is small.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: August 29, 2017
    Assignee: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Junjie Li, Ying Yang, Qiong Yu, Wei Wang
  • Patent number: 9735772
    Abstract: An integrated circuit includes at least one integrated cell disposed at a location of the integrated circuit. The at least one integrated cell may have two integrated devices coupled to at least one site of the integrated cell and a multiplexer, and the two integrated devices respectively oriented in two different directions of orientation. A first integrated device of the two integrated devices that is oriented in one of the two directions of orientation is usable. The integrated circuit may include a controller configured to detect the direction of orientation which, having regard to the disposition of the integrated cell at the location, may allow the first integrated device to be usable, and to control the multiplexer to couple the first integrated device electrically to the at least one site.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: August 15, 2017
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Alexandre Dray, Emmanuel Josse
  • Patent number: 9731960
    Abstract: A semiconductor device includes a substrate structure. The substrate structure includes a protruding engagement member having an inner periphery defining a groove and an outer periphery, an oxide layer on the protruding engagement member, and a bonding material layer on the oxide layer. The semiconductor device also includes a micro-electromechanical system (MEMS) substrate having a bonging pad. The bonding pad of the MEMS substrate is bonded to the bonding material layer of the substrate structure.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: August 15, 2017
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Lushan Jiang, Xiaojun Chen, Xuanjie Liu, Liangliang Guo, Junde Ma
  • Patent number: 9725298
    Abstract: A method of fabricating a semiconductor device comprises forming a dielectric layer above a substrate, the dielectric layer including a fixed dielectric portion and a proof mass portion, forming a source region and a drain region in the substrate, forming a gate electrode in the proof mass portion, and releasing the proof mass portion, such that the proof mass portion is movable with respect to the fixed dielectric portion and the gate electrode is movable with the proof mass portion relative to the source region and the drain region.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: August 8, 2017
    Assignee: Robert Bosch GmbH
    Inventors: Ando Feyh, Po-Jui Chen, Markus Ulm
  • Patent number: 9726618
    Abstract: A sensing system which comprises a material (30) formed of a matrix and a plurality of non-insulating particles (40) substantially equally spaced within the matrix such that the material has coherent electrical periodicity in at least one dimension; and a receiver (10), the receiver arranged to receive a source RF signal and a returned RF signal, the source RF signal being reflected by the non-insulating particles to produce the returned RF signal. A change in the position of one or more of the non-insulating particles causes the returned RF signal to change, such that a change in a property of the material can be determined from the returned RF signal.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: August 8, 2017
    Assignee: PARAMATA LTD.
    Inventors: Christopher Robin Lowe, Karishma Jain, Adrian Carl Stevenson
  • Patent number: 9691437
    Abstract: A microelectronic package has terminals at a surface of a substrate having first and second half areas, each half area extending from a diagonal that bisects the first surface and a respective opposite corner of the first surface. Terminals for carrying data and address information in the first half area provide first memory channel access to a first memory storage array, and terminals for carrying data and address information in the second half area provide second memory channel access to a second memory storage array. The package may include first and second microelectronic elements overlying a same surface of the substrate which may be stacked in transverse orientations.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: June 27, 2017
    Assignee: Invensas Corporation
    Inventors: Zhuowen Sun, Yong Chen
  • Patent number: 9689757
    Abstract: A strain transmitter for detecting strain of a structure includes a strain body, which has a strain axis with fastening devices for fastening the strain body on a structure, and a measurement element, which is arranged centrally between the fastening devices on the strain axis. The measurement element includes a metal sheet. The entire surface of a statically measuring, piezo-resistant silicon chip, which is connected to a full bridge and emits a voltage in the strained state proportional to the level of strain, is applied to the metal sheet. The measurement element includes a printed circuit board, and electric contacts are guided from the silicon chip along the printed circuit board.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: June 27, 2017
    Assignee: KISTLER HOLDING AG
    Inventor: Thomas Cadonau
  • Patent number: 9650241
    Abstract: A method for forming a MEMS device includes coupling a MEMS substrate and a base substrate. The MEMS substrate and the base substrate contain at least two enclosures. One enclosures has a first vertical gap between the bonding surface of the MEMS substrate and the bonding surface of the base substrate that is less than a second vertical gap between the bonding surface of the MEMS substrate and the bonding surface of the base substrate than another of the enclosures to provide a height difference between the first vertical gap and the second vertical gap. The method includes bonding the bonding surfaces of the one of the two enclosures at a first pressure to provide a first sealed enclosure. The method includes bonding the bonding surfaces of other of the two enclosures at a second pressure to provide a second sealed enclosure.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: May 16, 2017
    Assignee: INVENSENSE, INC.
    Inventors: Cerina Zhang, Martin Lim
  • Patent number: 9646637
    Abstract: A thin-film piezoelectric material element includes a laminated structure part having a lower electrode film, a piezoelectric material film laminated on the lower electrode film and an upper electrode film laminated on the piezoelectric material film. The thin-film piezoelectric material element includes a surface layer insulating film disposed on side surfaces of the laminated structure part and a top surface of the upper electrode film, and has a through hole formed on a top disposed part disposed on the top surface. The surface layer insulating film has a long-side disposed part disposed outside than the top disposed part, the long-side disposed part has a long-side width, along with the long-side direction, formed shorter than the through hole.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: May 9, 2017
    Assignee: SAE MAGNETICS (H.K.) LTD.
    Inventors: Wei Xiong, Atsushi Iijima
  • Patent number: 9630831
    Abstract: The present disclosure provides a CMOS structure, including a substrate, a metallization layer over the substrate, a sensing structure over the metallization layer, and a signal transmitting structure adjacent to the sensing structure. The sensing structure includes an outgassing layer over the metallization layer, a patterned outgassing barrier over the outgassing layer; and an electrode over the patterned outgassing barrier. The signal transmitting structure electrically couples the electrode and the metallization layer.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: April 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jung-Huei Peng, Chia-Hua Chu, Fei-Lung Lai, Shiang-Chi Lin
  • Patent number: 9617143
    Abstract: A method of forming a semiconductor device comprises bonding a capping wafer and a base wafer to form a wafer package. The base wafer comprises a plurality of chip package portions. The capping wafer comprises a plurality of isolation trenches. Each isolation trench of the plurality of isolation trenches is configured to substantially align with a corresponding chip package portion of the plurality of chip package portions. The method also comprises separating the wafer package into a plurality of chip packages. Each chip package of the plurality of chip packages comprises at least one chip package portion of the plurality of chip package portions.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: April 11, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-wen Cheng, Jung-Huei Peng, Shang-Ying Tsai, Hung-Chia Tsai, Yi-Chuan Teng
  • Patent number: 9595577
    Abstract: A vertical semiconductor device includes a semiconductor body having semiconductor portions of semiconductor elements of the vertical semiconductor device, a front side contact on a front surface of the semiconductor body and a back side contact on an opposite back surface of the semiconductor body, and a trench structure extending from the front surface into the semiconductor body. The trench structure includes an etch stop layer lining an inner surface of the trench structure and surrounding a void within the trench structure.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: March 14, 2017
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Anton Mauder
  • Patent number: 9590167
    Abstract: A piezoelectronic transistor device includes a first piezoelectric (PE) layer, a second PE layer, and a piezoresistive (PR) layer arranged in a stacked configuration, wherein an electrical resistance of the PR layer is dependent upon an applied voltage across the first and second PE layers by an applied pressure to the PR layer by the first and second PE layers. A piezoelectronic logic device includes a first and second piezoelectric transistor (PET), wherein the first and second PE layers of the first PET have a smaller cross sectional area than those of the second PET, such that a voltage drop across the PE layers of the first PET creates a first pressure in the PR layer of the first PET that is smaller than a second pressure in the PR layer of the second PET created by the same voltage drop across the PE layers of the second PET.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: March 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce G. Elmegreen, Glenn J. Martyna, Dennis M. Newns
  • Patent number: 9548359
    Abstract: A method for forming a semiconductor device includes providing a semiconductor structure, which includes a semiconductor substrate and a first mask layer on the substrate. The first mask layer is used to form a plurality of first trenches that extends into the substrate and extends laterally in a first direction and do not intersect each other. The first trenches are then filled with a fill material. Next, a second mask layer is formed on the semiconductor structure filled with the fill material. The second mask layer is then used to form a second plurality of trenches in the semiconductor substrate that extend laterally in a second direction and do not intersect each other. Each of the second trenches intersects at least one of the first plurality of trenches. Next, the fill material is removed to form a plurality of vertical pillars defined by intersecting first trenches and second trenches.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: January 17, 2017
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporaiton
    Inventor: Zhongshan Hong
  • Patent number: 9511994
    Abstract: A micro-electro-mechanical system device is disclosed. The micro-mechanical system device comprises a first silicon substrate comprising: a handle layer comprising a first surface and a second surface, the second surface comprises a cavity; an insulating layer deposited over the second surface of the handle layer; a device layer having a third surface bonded to the insulating layer and a fourth surface; a piezoelectric layer deposited over the fourth surface of the device layer; a metal conductivity layer disposed over the piezoelectric layer; a bond layer disposed over a portion of the metal conductivity layer; and a stand-off formed on the first silicon substrate; wherein the first silicon substrate is bonded to a second silicon substrate, comprising: a metal electrode configured to form an electrical connection between the metal conductivity layer formed on the first silicon substrate and the second silicon substrate.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: December 6, 2016
    Assignee: INVENSENSE, INC.
    Inventors: Julius Ming-Lin Tsai, Michael J. Daneman
  • Patent number: 9493346
    Abstract: An integrated circuit (IC) structure is provided. The IC structure includes an IC substrate including active devices which are coupled together through a conductive interconnect structure arranged thereover. The conductive interconnect structure includes a series of horizontal conductive layers and dielectric regions arranged between neighboring horizontal conductive layers. The conductive interconnect structure includes an uppermost conductive horizontal region with a planar top surface region. A MEMS substrate is arranged over the IC substrate and includes a flexible or moveable structure that flexes or moves commensurate with a force applied to the flexible or moveable structure. The active devices of the IC substrate are arranged to establish analysis circuitry to facilitate electrical measurement of a capacitance between the uppermost conductive horizontal region and the flexible or moveable structure.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: November 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Cheng Shen, Yi-Hsien Chang, Yi Heng Tsai, Tzu-Heng Wu, Chun-Ren Cheng, Chun-Wen Cheng
  • Patent number: 9472633
    Abstract: Embodiments include but are not limited to apparatuses and systems including a microelectronic device including a gate, a source pad and a drain pad arranged such that the gate is separated from the source pad and the drain pad by air, and an insulating layer coupled with a portion of the gate such that at least a portion of the insulating layer is separated from the source pad and the drain pad by the air. Methods for making the same also are described.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: October 18, 2016
    Assignee: Qorvo US, Inc.
    Inventors: Michael Schuette, Andrew Ketterson
  • Patent number: 9450066
    Abstract: Methods for forming a vertically movable gate field effect transistor (VMGFET) on a silicon-on-insulator (SOI) wafer are described. The methods include providing a process of making VMGFET devices without critical alignment of masks between sequential etch and diffusion steps. The oxide layer of the SOI wafer is used for a self-limiting etch stop layer and for a sacrificial layer to form an insulating layer between a gate electrode and a substrate. The proper location of the gate electrode with respect to the source and drain junctions is insured by using a silicon gate structure as a mask layer for the diffusion process for defining the source and drain junctions.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: September 20, 2016
    Assignee: Texas State University
    Inventors: In-Hyouk Song, Byoung Hee You, Heung Seok Kang, Kang-Hee Lee
  • Patent number: 9448655
    Abstract: The present disclosure relates to a touch sensor and touch sensitive display having a plurality of first and second conductive lines arranged substantially orthogonally with a sensing material to sense a change in capacitance between them. The first and second conductive lines and the sensing material defining an array of sensitive transistors.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: September 20, 2016
    Assignee: Honeywell International Inc.
    Inventors: Viorel Georgel Dumitru, Stefan Dan Costea, Ion Georgescu, Mihai Brezeanu, Bogdan-Catalin Serban
  • Patent number: 9442027
    Abstract: An elastic body load cell including a first beam and a second beam opposite the first beam, a base end and a load receiving end positioned opposite the base end. The first and second beams are connected to the base end and to the load receiving end via flexure points providing elastic deformation sections. A cavity comprising a flexible wall and sensor means is defined in the first and/or second beams with the flexible wall and sensor means placed between the flexure points. The sensor means measures elastic deformation of the elastic body in response to a load. The load cell further includes a lever having a first end connected to the flexible wall, and a second end connected to the opposite beam, the base end or the load receiving end, to transform movement of the second end into deformations of the flexible wall in response to the load.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: September 13, 2016
    Inventor: Nils Aage Juul Eilersen
  • Patent number: 9435699
    Abstract: The invention relates to a method for producing a micro-electromechanical device in a material substrate suitable for producing integrated electronic components, in particular a semiconductor substrate, wherein a material substrate (12,14,16) is provided on which at least one surface structure (26) is to be formed during production of the device. An electronic component (30) is formed in the material substrate (12,14,16) using process steps of a conventional method for producing integrated electronic components. A component element (44) defining the position of the electronic component (30) and/or required for the function of the electronic component (30) is selectively formed on the material substrate (12,14,16) from an etching stop material acting as an etching stop in case of etching of the material substrate (12,14,16) and/or in case of etching of a material layer (52) disposed on the material substrate (12,14,16).
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: September 6, 2016
    Assignee: ELMOS Semiconductor AG
    Inventor: Arnd Ten-Have
  • Patent number: 9417721
    Abstract: A TFT touch display device includes a plurality of mutually vertical control lines and sensor lines and a plurality of TFTs. Each TFT is disposed at an intersection of one of the plurality of control line and one of the plurality of sensor line. The TFT is connected to a corresponding control line, a corresponding sensor line, and a power source. When there is an object approaching to the TFT, the TFT is turned on and a back-channel current is generated. A control unit is connected to the plurality of control lines to respectively provide a control signal to the plurality of control lines. A current sensing unit is connected to the plurality of sensor lines to respectively sense a current generated by the TFTs.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: August 16, 2016
    Assignee: INNOLUX CORPORATION
    Inventors: Yu-Cheng Tsai, Tsau-Hua Hsieh, Chao-Liang Lu, Jian-Jung Shih
  • Patent number: 9403677
    Abstract: The micro-electromechanical semiconductor component is provided with a semiconductor substrate (4, 5), a reversibly deformable bending element (8a) made of semiconductor material, and at least one transistor that is sensitive to mechanical stresses, said transistor being designed as an integrated component in the bending element (8a). The transistor is arranged in an implanted active region pan (78a) that is made of a semiconductor material of a first conducting type and is introduced in the bending element (8a). Two mutually spaced, implanted drain and source regions (79, 80) made of a semiconductor material of a second conducting type are designed in the active region pan (78a), a channel region extending between said two regions. Implanted feed lines made of a semiconductor material of the second conducting type lead to the drain and source regions (79, 80). The upper face of the active region pan (78a) is covered by a gate oxide (81a).
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: August 2, 2016
    Assignee: ELMOS Semiconductor AG
    Inventor: Michael Doelle
  • Patent number: 9403676
    Abstract: The semiconductor component, in particular for use as a component that is sensitive to mechanical stresses in a micro-electromechanical semiconductor component, for example a pressure or acceleration sensor, is provided with a semiconductor substrate (1,5), in the upper face of which an active region (78a,200) made of a material of a first conductivity type is introduced by ion implantation. A semiconducting channel region having a defined length (L) and width (B) is designed within the active region (78a, 200). In the active region (78a,200), each of the ends of the channel region located in the longitudinal extension is followed by a contacting region (79, 80) made of a semiconductor material of a second conductivity type.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: August 2, 2016
    Assignee: ELMOS Semiconductor AG
    Inventor: Arnd Ten Have
  • Patent number: 9404934
    Abstract: The first buffer portion provides a first base portion and a first outer wall provided on a peripheral edge of the first base portion. The second buffer portion provides a second base portion which provides a mounting surface outside to a measurement target, and a second outer wall provided on a peripheral edge of the second base portion. The buffer body provides the first base portion and a top surface of the second outer wall abutting against each other. A housing portion for the sensor portion is provided inside. A holding portion which holds the sensor portion is provided at least at a part of the top surface of at least one of the first buffer portion and the second buffer portion. The sensor portion is held by the holding portion.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: August 2, 2016
    Assignee: Seiko Epson Corporation
    Inventor: Kazumasa Mizuta
  • Patent number: 9400224
    Abstract: A pressure sensor and a manufacturing method of the same are provided. The pressure sensor includes a substrate, a dielectric oxide layer, a first electrode, a dielectric connection layer, and a second electrode. The dielectric oxide layer is formed on the substrate. The first electrode is formed on the dielectric oxide layer. The dielectric connection layer is formed on the first electrode. The second electrode is formed on the dielectric connection layer. The second electrode comprises a patterned conductive layer and a dielectric layer. The patterned conductive layer has a plurality of holes, and the dielectric layer is formed on the patterned conductive layer and covers the inner walls of the plurality of holes. The first electrode, the dielectric connection layer, and the second electrode define a first chamber between the first electrode and the second electrode.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: July 26, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Jien-Ming Chen, Chin-Wen Huang, Chin-Hung Wang, Jing-Yuan Lin, Yu-Sheng Hsieh
  • Patent number: 9392376
    Abstract: A MEMS device includes a MEM-CMOS module having a CMOS chip and a MEMS chip. The MEMS chip includes a port exposed to the environment. The MEMS device further includes a printed circuit board (PCB) with an aperture, wherein the MEMS-CMOS module is directly mounted on the PCB.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: July 12, 2016
    Assignee: INVENSENSE, INC.
    Inventors: Aleksey S. Khenkin, Anthony D. Minervini
  • Patent number: 9379033
    Abstract: A sensor package is disclosed. One embodiment provides a sensor device having a carrier, a semiconductor sensor mounted on the carrier and an active surface. Contact elements are electrically connecting the carrier with the semiconductor sensor. A protective layer made of an inorganic material covers at least the active surface and the contact elements.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: June 28, 2016
    Assignee: Infineon Technologies AG
    Inventors: Ralf Wombacher, Horst Theuss
  • Patent number: 9341901
    Abstract: A display device is provided that inhibits color mixture between adjacent subpixels and allows for obtaining a high-quality image. The display device includes a display area on which a light-blocking metal layer, a black matrix, and a plurality of subpixels are arranged, wherein the plurality of subpixels are arranged adjacent to one another via a black matrix as seen vertically from above, the black matrix and the light-blocking metal layer are arranged to overlap each other as seen vertically from above, and the light-blocking metal layer 130 is arranged on the bank of an organic flattened film.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: May 17, 2016
    Assignee: Japan Display Inc.
    Inventors: Noriyoshi Kanda, Shigesumi Araki, Mitsutaka Okita, Hirohisa Miki
  • Patent number: 9299848
    Abstract: A semiconductor device with a reduced area is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor includes a first conductor and a second conductor arranged with a distance therebetween, a first insulator over the first conductor and the second conductor, a semiconductor over the first insulator, a second insulator over the semiconductor, a third conductor over the second insulator, and a fourth conductor and a fifth conductor that are in contact with the semiconductor. The first conductor includes a region not overlapping with the third conductor with the semiconductor therebetween, the first conductor includes a region overlapping with the second conductor with the semiconductor therebetween, and one of a source electrode and a drain electrode of the second transistor is electrically connected to the third conductor of the first transistor.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: March 29, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kiyoshi Kato
  • Patent number: 9294035
    Abstract: An embodiment includes an oscillator comprising an amplifier formed on a substrate; a multiple gate resonant channel array, formed on the substrate, including: (a) transistors including fins, each of the fins having a channel between source and drain nodes, coupled to common source and drain contacts; and (b) common first and second tri-gates coupled to each of the fins and located between the source and drain contacts; wherein the fins mechanically resonate at a first frequency when one of the first and second tri-gates is periodically activated to produce periodic downward forces on the fins. Other embodiments include a non planar transistor with a channel between the source and drain nodes and a tri-gate on the fin; wherein the fin mechanically resonates when the first tri-gate is periodically activated to produce periodic downward forces on the fin. Other embodiments are described herein.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Raseong Kim, Rajashree Baskaran, Rajeev K. Dokania, Ian A. Young
  • Patent number: 9284183
    Abstract: A micromechanical device and a method for forming the device is disclosed, wherein the micromechanical device has a laterally movable mechanically active element that has a quiescent position in which it is in physical contact with a second structural element. The device is fabricating by disposing the mechanically active element on a first substrate and disposing the second structural element on a second substrate. After the two substrates are aligned and joined such that both the mechanically active element and the second structural element are in contact and affixed to one of the substrates, the other substrate is removed leaving all structural elements disposed on a single substrate.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: March 15, 2016
    Assignee: HT MicroAnalytical, Inc.
    Inventor: Todd Richard Christenson
  • Patent number: 9238579
    Abstract: A semiconductor device. The device including a substrate having electrical traces, at least one of a MEMS die and a semiconductor chip mounted on the substrate, and a spacer. The spacer has a first end connected to the substrate and includes electrical interconnects coupled to the electrical traces. The at least one MEMS die and a semiconductor chip are contained within the spacer. The spacer and substrate form a cavity which contains the at least one MEMS die and a semiconductor chip. The cavity forms an acoustic volume when the semiconductor device is mounted to a circuit board via a second end of the spacer.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 19, 2016
    Assignee: Robert Bosch GmbH
    Inventors: Eric Ochs, Jay S. Salmon
  • Patent number: 9227840
    Abstract: A micro-electro mechanical apparatus having a PN-junction is provided. The micro-electro mechanical apparatus includes a movable mass, a conductive layer, and an electrode. The movable mass includes a P-type semiconductor layer and an N-type semiconductor layer. The PN-junction is formed between the P-type semiconductor layer and the N-type semiconductor layer. The micro-electro mechanical apparatus is capable of eliminating abnormal voltage signal when an alternating current passes through the conductive layer. The micro-electro mechanical apparatus is adapted to measure acceleration and magnetic field. The micro-electro mechanical apparatus can be other types of micro-electro mechanical apparatus such as micro-electro mechanical scanning micro-mirror.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: January 5, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Chung-Yuan Su, Chin-Fu Kuo, Chih-Yuan Chen, Chao-Ta Huang