Abstract: Systems, methods, and apparatus related to dynamically determining read voltages used in memory devices. In one approach, a memory device has a memory array including memory cells. One or more resistors are formed as part of the memory array. A memory controller increments a counter as write operations are performed on the memory cells. When the counter reaches a limit, a write operation is performed on the resistors. The write operation applies voltages to the resistors similarly as applied to the memory cells over time during normal operation. When performing a read operation, a current is applied to one or more of the resistors to determine a boost voltage. When reading the memory cells, a read voltage is adjusted based on the boost voltage. The memory cells are read using the adjusted read voltage.

Abstract: An image sensor compensates for noise. The image sensor includes a pixel array that includes a common monitor output line, a first monitoring pixel outputting a first monitoring signal, a second monitoring pixel outputting a second monitoring signal, and an active pixel configured to output a sensing signal based on an incident light. The image circuit also includes a binning circuit that receives the first and second monitoring signals through the common monitor output line and generates an average monitoring signal by performing binning on the first and second monitoring signals, and an analog-to-digital converter that detects an alternating current (AC) component of the average monitoring signal and couples the sampled AC component of the average monitoring signal to the sensing signal, thereby compensating for noise.

Abstract: An image sensor chip-scale package includes a pixel array, a cover glass covering the pixel array, a dam, and an adhesive layer. The pixel array is embedded in a substrate top-surface of a semiconductor substrate. The semiconductor substrate includes a plurality of conductive pads in a peripheral region of the semiconductor substrate surrounding the pixel array. The dam at least partially surrounds the pixel array and is located (i) between the cover glass and the semiconductor substrate, and (ii) on a region of the substrate top-surface between the pixel array and the plurality of conductive pads. The adhesive layer is (i) located between the cover glass and the semiconductor substrate, (ii) at least partially surrounding the dam, and (iii) configured to adhere the cover glass to the semiconductor substrate.

Abstract: An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers directly into the at least one charge carrier storage region based upon times at which the charge carriers are produced.

Abstract: An image sensor includes unit pixels, and from among the unit pixels, a first unit pixel and a second unit pixel that are adjacent to each other each include a first tap having a first photo gate, to which a first signal having a first phase difference with respect to an optical signal is applied, and a second tap having a second photo gate, to which a second signal having a second phase difference with respect to the optical signal is applied. A location of the first tap in the first unit pixel and a location of the first tap in the second unit pixel, and a location of the second tap in the first unit pixel and a location of the second tap in the second unit pixel are symmetrical with each other based on one point between the first unit pixel and the second unit pixel.

Abstract: The method for manufacturing a display panel includes: forming a thin film transistor (TFT), a first signal line, a second signal line, a third signal line, and a first insulation layer on a substrate, in which the first signal line is coupled to one of the gate and the source of the TFT, the second signal line is coupled to the other of the gate and the source, and the third signal line is electrically connected to the first signal line through a via of the first insulation layer; forming a second insulation layer on the TFT, the first signal line, the second signal line, the third signal line, and the first insulation layer; and forming a first transparent conductive layer on the second insulation layer with an electrode covering at least part of the third signal line.

Abstract: Building programmable resistive devices in contact holes at the crossover of a plurality of conductor lines in more than two vertical layers is disclosed. There are plurality of first conductor lines and another plurality of second conductor lines that can be substantially perpendicular to each other, though in two different vertical layers. A diode and/or a programmable resistive element can be fabricated in the contact hole between the first and second conductor lines. The programmable resistive element can be coupled to another programmable resistive device or shared between two programmable devices whose diodes conducting currents in opposite directions and/or coupled to a common conductor line. The programmable resistive memory can be configured to be programmable by applying voltages to conduct current flowing through the programmable resistive element to change its resistance for a different logic state.

Abstract: The present disclosure relates to a display substrate comprising a substrate; a data line disposed over the substrate; a first insulating layer disposed on the data line; a second insulating layer disposed on the first insulating layer; a first transparent electrode disposed on the second insulating layer. The present disclosure further relates to a manufacturing method of a display substrate and a display device.

Abstract: As a display device has higher definition, the number of pixels is increased and thus, the number of gate lines and signal lines is increased. When the number of gate lines and signal lines is increased, it is difficult to mount IC chips including driver circuits for driving the gate lines and the signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided on the same substrate, and at least part of the driver circuit comprises a thin film transistor including an oxide semiconductor sandwiched between gate electrodes. A channel protective layer is provided between the oxide semiconductor and a gate electrode provided over the oxide semiconductor. The pixel portion and the driver circuit are provided on the same substrate, which leads to reduction of manufacturing cost.

Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.

Abstract: The present disclosure provides a thin film transistor, a method for manufacturing the same, a thin film transistor assembly, an array substrate and a display apparatus. The thin film transistor comprises: a substrate; a gate electrode, a gate insulation portion, a semiconductor portion, a source electrode and a drain electrode, the gate insulation portion separating the semiconductor portion from the gate electrode, and the source electrode and the drain electrode being connected to the semiconductor portion, wherein a projection of the gate electrode onto the substrate and that of the semiconductor portion onto the substrate are not overlapped with each other.

Abstract: A solid-state imaging element that includes a plurality of semiconductor layers stacked, a plurality of stack-connecting parts for electrically connecting the plurality of semiconductor layers, a pixel array part in which pixel cells that include a photoelectric conversion part and a signal output part are arrayed in a two-dimensional shape, and an output signal line through which signals from the signal output part of the pixel cells are propagated, in which the plurality of semiconductor layers includes at least a first semiconductor layer and a second semiconductor layer, and, in the first semiconductor layer, the plurality of pixel cells are arrayed in a two-dimensional shape, the signal output part of a pixel group formed with the plurality of pixel cells shares an output signal line wired from the stack-connecting parts, and the output signal line has a separation part which can separate each output signal line.

Abstract: To provide a semiconductor device with small parasitic capacitance. Alternatively, to provide a semiconductor device with low power consumption. The semiconductor device includes a transistor and a capacitor. The transistor includes a first conductor, a first insulator over the first conductor, a semiconductor including a region overlapping with the first conductor with the first insulator interposed therebetween, a second insulator over the semiconductor, a second conductor including a region overlapping with the semiconductor with the second insulator interposed therebetween, and a third conductor and a fourth conductor including a region in contact with a top surface of the semiconductor. The capacitor includes a layer formed from the same layer as the first conductor and a layer formed from the same layer as the third conductor and the fourth conductor.

Abstract: Dark current of FD is eliminated in an image sensor, and conversion efficiency of converting electric charge to voltage is improved. A pixel circuit includes a photoelectric conversion portion, a control transistor, and an electric charge accumulation portion. The photoelectric conversion portion converts light incident along an optical axis to electric charge. The control transistor controls output voltage according to input voltage. The electric charge accumulation portion accumulates electric charge in a region positioned between the control transistor and the photoelectric conversion portion on the optical axis, and supplies a voltage according to the amount of accumulated electric charge as the input voltage to the control transistor.

Abstract: An object is to provide an imaging device with high efficiency of transferring charge corresponding to imaging data. The imaging device includes first to fifth conductors, first and second insulators, an oxide semiconductor, a photoelectric conversion element, and a transistor. The first conductor is in contact with a bottom surface and a side surface of the first insulator. The first insulator is in contact with a bottom surface of the oxide semiconductor. The oxide semiconductor is in contact with bottom surfaces of the second and third conductors and the second insulator. Each of the second and third conductors is in contact with the bottom surface and a side surface of the second insulator. The second insulator is in contact with bottom surfaces of the fourth and fifth conductors. The first conductor has regions overlapped by the fourth and fifth conductors. The second conductor has a region overlapped by the fourth conductor. The third conductor has a region overlapped by the fifth conductor.

Abstract: The present technology relates to an image sensor and an electronic apparatus which can make the image sensor a smaller without degrading performance of the image sensor. The image sensor includes a pixel array unit in which pixels including photoelectric conversion elements are arranged in a two dimensional manner, a row circuit configured to control row scanning of the pixel array unit, and a column processing unit configured to convert an analog signal read out from the pixel array unit into a digital signal. The pixel array unit is disposed on a first-layer substrate, and the row circuit and the column processing unit are disposed on different substrates which are underlying layers of the first-layer substrate and which are laminated on the first-layer substrate. The present technology is applicable to the image sensor.

Abstract: A step for forming an island-shaped semiconductor layer of a semiconductor device used in a display device is omitted in order to manufacture the semiconductor device with high productivity and low cost. The semiconductor device is manufactured through four photolithography processes: four steps for forming a gate electrode, for forming a source electrode and a drain electrode, for forming a contact hole, and for forming a pixel electrode. In the step for forming the contact hole, a groove portion in which a semiconductor layer is removed is formed, whereby formation of a parasitic transistor is prevented. An oxide semiconductor is used as a material of the semiconductor layer in which a channel is formed, and an oxide semiconductor having a higher insulating property than the semiconductor layer is provided over the semiconductor layer.

Abstract: An image sensor, in particular a CMOS image sensor, for electronic cameras includes a plurality of light-sensitive pixels arranged in rows and columns for generating exposure-dependent pixel signals. A plurality of column lines, at least one precharge circuit for charging or discharging the column lines and at least one column readout circuit for reading out the pixel signals of the respective column are associated with a respective column. The image sensor has at least one switching device which is adapted to couple, in a first switch state, one of the column lines of a respective column to the precharge circuit and another one of the column lines of the respective column to the column readout circuit.

Abstract: A method for manufacturing a dual gate oxide semiconductor TFT substrate utilizes a halftone mask to implement a photo process, which not only accomplishes patterning to an oxide semiconductor layer but also obtains an oxide conductor layer with ion doping. The method implements patterning to a bottom gate isolation layer and a top gate isolation layer at the same time with one photolithographic process. The method implements patterning to second and third metal layers at the same time to obtain a first source, a first drain, a second source, a second drain, a first top gate and a second top gate with one photolithographic process. The method implements patterning to a second flat layer, a passivation layer and a top gate isolation layer at the same time with one photolithographic process. The number of photolithographic processes involved is reduced to nine so as to simplify the manufacturing process.

Abstract: A liquid crystal display includes a first substrate in which a pixel region is defined by a gate line and a data line intersecting the gate line, the pixel region being arranged in a matrix with other pixel regions, a pixel electrode disposed in the pixel region, and a shielding electrode disposed between the pixel electrode and another pixel electrode, wherein the shielding electrode is electrically connected to the data line and a different voltage from a voltage applied to the data line is applied to the shielding electrode.

Abstract: An image-capturing device includes an image sensor. The image sensor includes an upper layer pixel group and a lower layer pixel group that receives the light fluxes from the subject that have passed through each pixel in the upper layer pixel group. The lower layer pixel group includes fourth, fifth and sixth pixels having fourth, fifth and sixth spectral sensitivities, respectively, that are complementary to first, second, and third spectral sensitivities, respectively, of the upper layer pixel group, being arranged in a two-dimensional pattern. Positions of first, second and third pixels in the upper layer pixel group and positions of the fourth, fifth and sixth pixels in the lower layer pixel group are determined such that the fourth, fifth and sixth pixels receive light fluxes that pass through the first, second and third pixels, respectively.

Abstract: A TFT device including: a gate electrode; a channel layer above the gate electrode; a channel protection layer on the channel layer; an electrode pair on the channel protection layer composed of a source electrode and a drain electrode that are spaced away from one another, a part of each of the source electrode and the drain electrode in contact with the channel layer through the channel protection layer; and a passivation layer extending over the gate electrode, the channel layer, the electrode pair, and the channel protection layer. The channel layer is made of an oxide semiconductor. The TFT device has a first sub-layer made of one of silicon nitride and silicon oxynitride and in which Si—H density is no greater than 2.3×1021 cm?3. The first sub-layer is included in at least one of the channel protection layer and the passivation layer.

Abstract: Each unit pixel includes a photoelectric converter formed above a semiconductor region, an amplifier transistor formed in the semiconductor region, and including a gate electrode connected to the photoelectric converter, a reset transistor configured to reset a potential of the gate electrode, and an isolation region formed in the semiconductor region between the amplifier transistor and the reset transistor to electrically isolate the amplifier transistor from the reset transistor. The amplifier transistor includes a source/drain region. The source/drain region has a single source/drain structure.

Abstract: The present invention provides a manufacture method of an oxide semiconductor TFT substrate and a structure thereof.

Abstract: To provide a semiconductor device with small parasitic capacitance. Alternatively, to provide a semiconductor device with low power consumption. The semiconductor device includes a transistor and a capacitor. The transistor includes a first conductor, a first insulator over the first conductor, a semiconductor including a region overlapping with the first conductor with the first insulator interposed therebetween, a second insulator over the semiconductor, a second conductor including a region overlapping with the semiconductor with the second insulator interposed therebetween, and a third conductor and a fourth conductor including a region in contact with a top surface of the semiconductor. The capacitor includes a layer formed from the same layer as the first conductor and a layer formed from the same layer as the third conductor and the fourth conductor.

Abstract: A light sensing circuit for solving the problem of low reliability in illumination detection includes a photo transistor having a gate, a drain and a source; a first transistor electrically connecting between the gate and source of the photo transistor; a first capacitor electrically connecting between the gate and the drain of the photo transistor; a second transistor electrically connecting with the drain of the photo transistor, the first capacitor, and a data signal; a second capacitor electrically connecting between the source of the photo transistor and a ground contact; a third transistor electrically connecting with the photo transistor, the first transistor, and the second capacitor; and a switch adapted to alternatively connect the third transistor with a buffer or a zero signal. A control method of the above light sensing circuit is also disclosed. Therefore, the above identified problem can be surely solved.

Abstract: A solid-state imaging element that includes a plurality of semiconductor layers stacked, a plurality of stack-connecting parts for electrically connecting the plurality of semiconductor layers, a pixel array part in which pixel cells that include a photoelectric conversion part and a signal output part are arrayed in a two-dimensional shape, and an output signal line through which signals from the signal output part of the pixel cells are propagated, in which the plurality of semiconductor layers includes at least a first semiconductor layer and a second semiconductor layer, and, in the first semiconductor layer, the plurality of pixel cells are arrayed in a two-dimensional shape, the signal output part of a pixel group formed with the plurality of pixel cells shares an output signal line wired from the stack-connecting parts, and the output signal line has a separation part which can separate each output signal line.

Abstract: A super junction semiconductor device is formed by forming at least a portion of a drift layer on a doped layer of a first conductivity type, implanting first dopants of a first conductivity type and second dopants of a second conductivity type into the drift layer using one or more implant masks with openings to form stripe-shaped first implant regions of the first conductivity type and stripe-shaped second implant regions of the second conductivity type in alternating order, and performing a heat treatment for controlling a diffusion of dopants from the implant regions to form stripe-shaped first regions of the first conductivity type and stripe-shaped second regions of the second conductivity type.

Abstract: A display device is provided including a display region arranged with a plurality of the pixels in a matrix, the plurality of pixels including a light emitting region, a first light shielding layer, and a second light shielding layer, wherein the first light shielding layer includes a plurality of first apertures opening the light emitting region, and a plurality of second apertures opening a non-light emitting region between the plurality of the pixels, and the second light shielding layer is arranged below the first light shielding layer and includes a plurality of third apertures opening the light emitting region, the second light shielding layer being arranged with a light shielding region below the second apertures.

Abstract: The present invention relates to a device and detector for monitoring a plurality of discrete fluorescence signals, in particular for DNA sequencing by use of fluorescently labeled nucleotides. The particular detector (118) is proposed comprising a plurality of pixels (130) for individually detecting said fluorescence signals from the plurality of fluorescent signal sources (104), wherein each pixel (130) comprises a predetermined number of at least two detection elements (D1, Dn) for detecting a received fluorescent signal and for generating detection signals. Further, a signal conversion circuit (140) is provide for receiving said detection signals from said at least two detection elements (D1, Dn) and for generating a pixel output signal indicating which of said at least two detection elements (D1, Dn) generated the strongest detection signal.

Abstract: Techniques described herein generally relate to digital imaging systems, methods and devices. In some example embodiments, a low light adaptive photoelectric imaging device may include a photoelectric transducer configured to receive and convert incident light into an electric charge that varies in response to an intensity of the received incident light. Some example imaging devices may also include circuitry coupled to the photoelectric transducer and configured to electrically float a potential at one or more terminals of the photoelectric transducer effective to cause the photoelectric transducer to amplify the electric charge according to a gain function that non-linearly varies relative to the intensity of the received incident light.

Abstract: A photoelectric conversion apparatus has multiple photoelectric converting units disposed in a semiconductor substrate, and isolation portions disposed in the semiconductor substrate. Each photoelectric converting unit includes a second semiconductor region, a third semiconductor region, disposed below the second semiconductor region and a fourth semiconductor region disposed below the third semiconductor region.

Abstract: Embodiments of the present invention provide an array substrate, a manufacturing method thereof and a display device. The manufacturing method of an array substrate, comprising: forming a gate electrode on a base substrate by a first patterning process, and then depositing a gate insulating layer on the base substrate on which the gate electrode is formed; forming source and drain electrodes on the base substrate obtained after the above step, by a second patterning process; forming an active layer formed of a graphene layer, and a protective layer disposed on the active layer, on the base substrate obtained after the above steps, by a third patterning process; and forming a planarizing layer on the base substrate, obtained after the above steps, by a fourth patterning process, in which the planarizing layer is provided with a through hole through which the source or drain electrode is exposed.

Abstract: The invention describes image sensor array pixels with global and rolling shutter capabilities that utilize multiple BCMD transistors for storing and sensing charge for a single photodiode. This configuration improves the Dynamic Range (DR) of the sensor, by allowing sensing different image signals from a single pixel without saturation, a low level signal with long integration time followed by a high level signal with short integration time. Signal processing circuits can process these signals into a single Wide Dynamic Range (WDR) output. Further disclosed are pixels that use multiple-gate BCMD transistors for charge storage and sensing having multiple concentric gates, which allows changing the conversion gain of the BCMD transistors. Variable conversion gain is a useful feature when building WDR sensors since low conversion gain and high well capacity allows detection of high level signals and, at the same time, low level signals with high conversion gain and low noise.

Abstract: An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.

Abstract: A semiconductor structure having: a silicon structure; and a plurality of laterally spaced PiN diodes formed in the silicon structure; and a surface of the silicon structure configured to reduce reverse bias leakage current through the PiN diodes. In one embodiment, a gate electrode structures is disposed on a surface of the silicon structure, the gate electrode structure having portions disposed between adjacent pairs of the diodes, the gate structure being biased to prevent leakage current through the diodes.

Abstract: A method of manufacturing an array substrate for a fringe field switching mode liquid crystal display includes: forming an auxiliary insulating layer on a second passivation layer and having a first thickness; forming first and second photoresist patterns on the auxiliary insulating layer and having second and third thicknesses, respectively, the second thickness greater than the third thickness; etching the auxiliary insulating layer, the second passivation layer and a first passivation layer to form a drain contact hole; performing an ashing to remove the second photoresist pattern and expose the auxiliary insulating layer therebelow; performing a dry etching to remove the auxiliary insulating layer not covered by the first photoresist pattern and expose the first passivation layer and to form an insulating pattern below the first photoresist pattern, the insulating pattern and the first photoresist pattern forming an undercut shape; forming a transparent conductive material layer having a fourth thickness

Abstract: As a display device has higher definition, the number of pixels is increased and thus, the number of gate lines and signal lines is increased. When the number of gate lines and signal lines is increased, it is difficult to mount IC chips including driver circuits for driving the gate lines and the signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided on the same substrate, and at least part of the driver circuit comprises a thin film transistor including an oxide semiconductor sandwiched between gate electrodes. A channel protective layer is provided between the oxide semiconductor and a gate electrode provided over the oxide semiconductor. The pixel portion and the driver circuit are provided on the same substrate, which leads to reduction of manufacturing cost.

Abstract: An integrated circuit device includes a semiconductor substrate and a first transistor and a second transistor constructed in the semiconductor substrate. The first transistor has a first operating voltage higher than a second operating voltage of a second transistor. The first transistor includes a first drain structure, a first source structure, an isolation structure and a first gate structure. The first source structure includes a high voltage first-polarity well region, a first-polarity body region, a heavily doped first-polarity region, a second-polarity grade region and a heavily doped second-polarity region. The heavily doped second-polarity region is surrounded by the second-polarity grade region. The second-polarity grade region is surrounded by the first-polarity body region. The second transistor includes a second drain structure, a second source structure, a second gate structure and a first-polarity drift region.

Abstract: A thin film transistor array panel and a manufacturing method capable of forming an insulating layer made of different materials for a portion contacting an oxide semiconductor and a second portion without an additional process. The thin film transistor array panel includes: a gate electrode; a source electrode and a drain electrode spaced apart from each other, each of the source and drain electrodes comprising a lower layer and an upper layer; an insulating layer disposed between the gate electrode and the source and drain electrodes; a semiconductor, the source electrode and the drain electrode being electrically connected to the semiconductor; a first passivation layer contacting the lower layer of the source and drain electrodes but not contacting the upper layer of the source and drain electrodes; and a second passivation layer disposed on the upper layer of the source and drain electrodes.

Abstract: A global shutter pixel cell includes a serially connected anti-blooming (AB) transistor, storage gate (SG) transistor and transfer (TX) transistor. The serially connected transistors are coupled between a voltage supply and a floating diffusion (FD) region. A terminal of a photodiode (PD) is connected between respective terminals of the AB and the SG transistors; and a terminal of a storage node (SN) diode is connected between respective terminals of the SG and the TX transistors. A portion of the PD region is extended under the SN region, so that the PD region shields the SN region from stray photons. Furthermore, a metallic layer, disposed above the SN region, is extended downwardly toward the SN region, so that the metallic layer shields the SN region from stray photons. Moreover, a top surface of the metallic layer is coated with an anti-reflective layer.

Abstract: A low noise infrared photodetector has an epitaxial heterostructure that includes a photodiode and a transistor. The photodiode includes a high sensitivity narrow bandgap photodetector layer of first conductivity type, and a collection well of second conductivity type in contact with the photodetector layer. The transistor includes the collection well, a transfer well of second conductivity type that is spaced from the collection well and the photodetector layer, and a region of first conductivity type between the collection and transfer wells.

Abstract: An array comprises a plurality of pixels logically arranged in rows and columns. The pixels comprise a photoreceptor (11) for converting impinging radiation into electronic charge, a transfer element (12) for transferring the electronic charge towards a sense node, a reset transistor (13) for resetting the sense node (16), means for converting the electronic charge onto the sense node (16) into a voltage, and for outputting the voltage as a pixel signal, and means adapted for biasing the sense nodes at a low voltage lower than a reset voltage which is meant to initialize the photoreceptor, during integration of impinging radiation on the photoreceptors. The means for converting and outputting comprise a source follower (14) for converting the electronic charge, and a select transistor (15) for outputting the voltage as a pixel signal, and the reset transistor of at least one pixel is coupled with one main electrode to the gate of the reset transistor of another pixel.

Abstract: A wiring substrate includes an insulating layer having a first surface on which a projecting part is formed, and an electrode pad being formed on the projecting part and including a first electrode pad surface and a second electrode pad surface on a side opposite to the first electrode pad surface. The first electrode pad surface is exposed from the projecting part of the insulating layer. The second electrode pad surface is covered by the insulating layer. A cross-section of the projecting part is a tapered shape. One side of the cross-section toward the first electrode pad surface is narrower than another side of the cross-section toward the first surface of the insulating layer.

Abstract: A pixel structure, a method of manufacturing the pixel structure, and an active device matrix substrate are provided. The pixel structure includes a first patterned metal layer having a common line and a gate; a first insulation layer; a semiconductor pattern; a second patterned metal layer having a source and a drain both electrically connected to the semiconductor pattern; a second insulation layer having a contact opening exposing the drain; and an electrode layer having a common electrode, and a pixel electrode connected to the drain through the contact opening. The common line, the first insulation layer, and the pixel electrode constitute a first storage capacitor. The common line, the drain, and the common electrode constitute a sandwich structure. The common line, the first insulation layer, and the drain constitute a second storage capacitor. The drain, the second insulation layer, and the common electrode constitute a third storage capacitor.

Abstract: The invention describes the solid-state image sensor array and in particular describes in detail the junction gate BCMD pixel sensor array that can be used in the back side illuminated mode as well as in the front side illuminated mode. The pixels generally do not need addressing transistors and the reset is accomplished in a vertical direction to the junction gate, so no additional reset transistor is needed for this purpose. As a result of this innovation the pixel maintains large charge storage capacity when its size is reduced, has low noise due to the nondestructive charge readout, and no RTS noise. The pixel interface generated dark current is also drained to the gate, so the image sensor array operates with very low dark current noise even at high temperatures. The junction gate also serves as a drain for the overflow charge.

Abstract: A solid-state image pickup device includes an element isolation insulating film electrically isolating pixels on the surface of a well region; a first isolation diffusion layer electrically isolating the pixels under the element isolation insulating film; and a second isolation diffusion layer electrically isolating the pixels under the first isolation diffusion layer, wherein a charge accumulation region is disposed in the well region surrounded by the first and second isolation diffusion layers, the inner peripheral part of the first isolation diffusion layer forms a projecting region, an impurity having a conductivity type of the first isolation diffusion layer and an impurity having a conductivity type of the charge accumulation region are mixed in the projecting region, and a part of the charge accumulation region between the charge accumulation region and the second isolation diffusion layer is abutted or close to the second isolation diffusion layer under the projecting region.

Abstract: Although an organic resin substrate is highly effective at reducing the weight and improving the shock resistance of a display device, it is required to improve the moisture resistance of the organic resin substrate for the sake of maintaining the reliability of an EL element. Hard carbon films are formed to cover a surface of the organic resin substrate and outer surfaces of a sealing member. Typically, DLC (Diamond like Carbon) films are used as the carbon films. The DLC films have a construction where carbon atoms are bonded into an SP3 bond in terms of a short-distance order, although the films have an amorphous construction from a macroscopic viewpoint. The DLC films contain 95 to 70 atomic % carbon and 5 to 30 atomic % hydrogen, so that the DLC films are very hard and minute and have a superior gas barrier property and insulation performance.

Abstract: A semiconductor device includes an interlayer insulating film containing Si, O, C, and H, an under-bump metal film disposed over the interlayer insulating film and containing Ni, and a bump electrode disposed over the under-bump metal film. In the interlayer insulating film, a ratio of a peak height of Si—CH3 near a wave number 1270 cm?1 to a peak height of Si—O near a wave number 1030 cm?1 obtained by Fourier-transform infrared spectroscopy (FTIR) is 0.15 or greater and 0.27 or less. A ratio of a peak height of Si—CH2—Si near a wave number 1360 cm?1 to the peak height of Si—CH3 near the wave number 1270 cm?1 is 0.031 or greater.

Abstract: A flat panel display includes; a first substrate, a white reflective layer disposed on the first substrate, a pixel electrode disposed on the white reflective, a second substrate disposed facing the first substrate, a common electrode disposed on the second substrate, and an electrooptic layer disposed between the pixel electrode and the common electrode, wherein the white reflective layer includes at least one of TiO2 and BaSO4.