Light Responsive Or Combined With Light Responsive Device Patents (Class 257/257)
  • Patent number: 10317767
    Abstract: The subject matter presented herein relates to a method for producing a backplane for electro-optic displays. The method may include providing a substrate coated with a first conductive material on a first side and a second conductive material on a second side, the second side being positioned opposite from the first side, patterning the first conductive material by cutting through the first conductive material, wherein the patterning of the first conductive material creates electrical isolated conductive segments to be controlled by a driver circuit and creating a plurality of vias on the substrate, the plurality of vias extending through the substrate and providing electrical conductivity between the first and second sides. The method may further include creating a plurality of conductive traces on the second side of the substrate by patterning the second conductive material by locally align the vias to the driver circuit.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: June 11, 2019
    Assignee: E Ink Corporation
    Inventors: Richard J. Paolini, Jr., George G. Harris, Keith A. Jacobsen, Henry Ware Gale
  • Patent number: 10270436
    Abstract: Techniques are provided that pumping of deep traps in GaN electronic devices using photons from an on-chip photon source. In various embodiments, a method for optical pumping of deep traps in GaN HEMTs is provided using an on-chip integrated photon source that is configured to generate photons during operation of the HEMT. In an aspect, the on-chip photon source is a SoH-LED. In various additional embodiments, an integration scheme is provided that integrates the photon source into the drain electrode of a HEMT, thereby converting the conventional HEMT with an ohmic drain to a transistor with hybrid photonic-ohmic drain (POD), a POD transistor or PODFET for short.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: April 23, 2019
    Assignee: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Jing Chen, Baikui Li, Xi Tang
  • Patent number: 10262947
    Abstract: A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect an additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: April 16, 2019
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Ilyas Mohammed, Craig Mitchell, Belgacem Haba, Piyush Savalia
  • Patent number: 10177247
    Abstract: A precursor cell for a transistor having a foundation structure, a mask structure, and a gallium nitride (GaN) PN structure is provided. The mask structure is provided over the foundation structure to expose a first area of a top surface of the foundation structure. The GaN PN structure resides over the first area and at least a portion of the mask structure and has a continuous crystalline structure with no internal regrowth interfaces. The GaN PN structure comprises a drift region over the first area, a control region laterally adjacent the drift region, and a PN junction formed between the drift region and the control region. Since the drift region and the control region form the PN junction having no internal regrowth interfaces, the GaN PN structure has a continuous crystalline structure with reduced regrowth related defects at the interface of the drift region and the control region.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: January 8, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Jinqiao Xie, Xing Gu, Edward A. Beam, III
  • Patent number: 9881938
    Abstract: According to one embodiment, a substrate for display device includes an insulating substrate and a conductive film formed on at least one main surface of the insulating substrate. As to the substrate in an etching process in which a fluoric acid solution containing 10% or more hydrogen fluoride is used, a first etching rate of the conductive film is substantially the same as a second etching rate of the insulating substrate, or the first etching rate is greater than the second etching rate.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: January 30, 2018
    Assignee: Japan Display Inc.
    Inventors: Takaaki Kamimura, Noriyuki Hirata
  • Patent number: 9793141
    Abstract: This method concerns the protection against humidity of a device including a first and a second electronic components respectively having two opposite surfaces, the surfaces: being separated by a non-zero distance shorter than 10 micrometers; having an area greater than 100 mm2; being connected by an assembly of electrical interconnection elements spaced apart from one another by a space void of matter. This method includes applying a deposit of thin atomic layers onto the device to form a layer of mineral material covering at least the interconnection elements, the layer of mineral material having a permeability to water vapor smaller than or equal to 10?3 g/m2/day.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: October 17, 2017
    Assignees: Commissariat A L'Energie Atomique Et Aux Energies Alternatives, Thales
    Inventors: Francois Marion, Tony Maindron
  • Patent number: 9761447
    Abstract: The invention provides a method for manufacturing a TFT substrate and a TFT substrate manufactured thereof. In the above TFT substrate, the low temperature poly-silicon layer is produced by solid phase crystallization, the cost of production is under budget, and the TFT substrate is a double-grid structure that can guarantee the electrical characteristics of the thin film transistor and better the capacity of drive, and leakage phenomenon caused by groove light seldom happens.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: September 12, 2017
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xingyu Zhou, Yuanchun Wu
  • Patent number: 9755061
    Abstract: A semiconductor device includes: a nitride semiconductor multilayer; an insulating film disposed on the nitride semiconductor multilayer; and a gate electrode disposed on the insulating film, wherein the nitride semiconductor multilayer has a first oxidized region near an interface with a region of the insulating film below the gate electrode, the first oxidized region having an oxygen concentration higher than an oxygen concentration of a region near an interface with a region of the insulating film other than below the gate electrode.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: September 5, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Naoya Okamoto
  • Patent number: 9671887
    Abstract: According to one embodiment, a sensor-equipped display device includes a display panel, a first driver, and a second driver. The display panel includes a first electrode, a second electrode and a detection electrode. The first driver delivers a common driving signal to the first electrode and the second electrode at a time of display driving, and selectively writes a write signal to one of the first electrode and the second electrode at a time of sensing driving. The second driver reads, from the detection electrode, a read signal indicative of a variation of a sensor signal occurring between the one of the first electrode and the second electrode, on one hand, and the detection electrode, on the other hand, at the time of the sensing driving.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: June 6, 2017
    Assignee: Japan Display Inc.
    Inventor: Naosuke Furutani
  • Patent number: 9621776
    Abstract: An imaging element includes: a plurality of pixels configured to receive light from outside and generate and output an imaging signal depending on an amount of the light received; a first transfer line connected to the pixel; a second transfer line; a column selection switch configured to select one pixel column and output the imaging signal to the second transfer line; a column source follower including a gate to which the imaging signal transferred by the first transfer line is input, a drain end being connected to a power supply voltage, and a source end being connected to the column selection switch; a constant current source configured to drive the column source follower and read out the imaging signal to the second transfer line; and a current generating unit configured to flow a predetermined current to the source end side of the column source follower.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: April 11, 2017
    Assignee: OLYMPUS CORPORATION
    Inventors: Makoto Ono, Nana Akahane, Masashi Saito, Yoshio Hagihara, Susumu Yamazaki
  • Patent number: 9607884
    Abstract: Manufacturing stability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes the steps of: forming an etching stopper film over a first interlayer insulating film; forming an inorganic insulating film over the etching stopper film; forming a resist film over the inorganic insulating film; selectively etching the etching stopper film and the inorganic insulating film by using the resist film as a mask to form a first opening in the etching stopper film and to form a second opening in the inorganic insulating film; removing the resist film by O2 plasma ashing; forming a second interlayer insulating film over the inorganic insulating film; and etching the second interlayer insulating film to form a wiring groove that is coupled to the second opening, and etching a portion located under the first opening of the first interlayer insulating film to form a via hole.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: March 28, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takayuki Gotou
  • Patent number: 9601299
    Abstract: A photocathode is formed on a monocrystalline silicon substrate having opposing illuminated (top) and output (bottom) surfaces. To prevent oxidation of the silicon, a thin (e.g., 1-5 nm) boron layer is disposed directly on the output surface using a process that minimizes oxidation and defects, and a low work-function material layer is then formed over the boron layer to enhance the emission of photoelectrons. The low work-function material includes an alkali metal (e.g., cesium) or an alkali metal oxide. An optional second boron layer is formed on the illuminated (top) surface, and an optional anti-reflective material layer is formed on the boron layer to enhance entry of photons into the silicon substrate. An optional external potential is generated between the opposing illuminated (top) and output (bottom) surfaces. The photocathode forms part of novel sensors and inspection systems.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: March 21, 2017
    Assignee: KLA-Tencor Corporation
    Inventors: Yung-Ho Alex Chuang, John Fielden
  • Patent number: 9559028
    Abstract: A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device (1D) includes, a substrate (100D), which includes a main surface (101D) and a recess (108D) depressed from the main surface (101D), and includes a semiconductor material; a wiring layer (200D) in which at least a portion thereof is formed on the substrate (100D); one or more first elements (370D) accommodated in the recess (108D); a sealing resin (400D) covering at least a portion of the one or more first elements (370D) and filled in the recess (108D); and a plurality of columnar conductive portions (230D) penetrating through the sealing resin (400D) in the depth direction of the recess (108D), and respectively connected with the portion of the wiring layer (200D) that is formed at the recess (108D).
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: January 31, 2017
    Assignee: ROHM CO., LTD
    Inventors: Hirofumi Takeda, Yoshihisa Takada
  • Patent number: 9524970
    Abstract: Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: December 20, 2016
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 9524994
    Abstract: An image sensor with an array of pixels is provided. In order to achieve high image quality, it may be desirable to improve well capacity of individual pixels within the array. When forming each pixel, multiple n-type compartments having p-type isolation regions interposed between compartments may be formed. These compartments may have higher dopant concentrations due to lateral depletion that may occur within multiple PN-NP back to back junctions to assist full depletion at pinning-voltage. Compartments may allow distributing a moderately higher electric-field over a larger portion of the photodiode while lowering peak electric-fields that contribute to dark-current. Compartments will thereby improve the well capacity of the photodiode while preventing additional noise that may degrade the quality of the image signal. The quantity, doping, and depth of these compartments may be selected to maximize well capacity while minimizing effects on operating voltage, manufacturing cost, and power consumption.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: December 20, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Raminda Madurawe
  • Patent number: 9478579
    Abstract: An example imaging sensor system includes a backside-illuminated CMOS imaging array formed in a first semiconductor layer of a first wafer. The CMOS imaging array includes an N number of pixels, where each pixel includes a photodiode region. The first wafer is bonded to a second wafer at a bonding interface between a first metal stack of the first wafer and a second metal stack of the second wafer. A storage device is disposed in a second semiconductor layer of the second wafer. The storage device includes at least N number of storage cells, where each of the N number of storage cells are configured to store a signal representative of image charge accumulated by a respective photodiode region. Each storage cell includes a circuit element that is sensitive to light-induced leakage.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: October 25, 2016
    Assignee: OmniVision Technologies, Inc.
    Inventors: Tiejun Dai, Guannho George Tsau
  • Patent number: 9431573
    Abstract: Devices incorporating a single to a few-layer MoS2 channels in combination with optimized substrate, dielectric, contact and electrode materials and configurations thereof, exhibit light emission, photoelectric effect, and superconductivity, respectively.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: August 30, 2016
    Assignee: Georgetown University
    Inventors: Makarand Paranjape, Paola Barbara, Amy Liu, Marcio Fontana
  • Patent number: 9287502
    Abstract: Resistance variable memory cell structures and methods are described herein. One or more resistance variable memory cell structures include a first electrode common to a first and a second resistance variable memory cell, a first vertically oriented resistance variable material having an arcuate top surface in contact with a second electrode and a non-arcuate bottom surface in contact with the first electrode; and a second vertically oriented resistance variable material having an arcuate top surface in contact with a third electrode and a non-arcuate bottom surface in contact with the first electrode.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: March 15, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Eugene P Marsh, Timothy A. Quick
  • Patent number: 9236947
    Abstract: A thin-film Light Emitting Diode (LED) and methods of manufacturing the same are disclosed. Specifically, the thin-film LED is provided with an epitaxial layer having a proton implantation that controls the size of the active volume. Controlling the size of the active volume enables the thin-film LED to enjoy decreased rise and fall times, thereby achieving a thin-film LED that is useable for transmission in high transmission rate communication systems.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: January 12, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Nikolaus W. Schunk
  • Patent number: 9123547
    Abstract: A stacked semiconductor device includes a first substrate. A multilayer interconnect is disposed over the first substrate. Metal sections are disposed over the multilayer interconnect. First bonding features are over the metal sections. A second substrate has a front surface. A cavity extends from the front surface into a depth D in the second substrate. The cavity has an interior surface. A stop layer is disposed over the interior surface of the cavity. A movable structure is disposed over the front surface of the second substrate and suspending over the cavity. The movable structure includes a dielectric membrane, metal units over the dielectric membrane and a cap dielectric layer over the metal units. Second bonding features are over the cap dielectric layer and bonded to the first bonding features. The second bonding features extend through the cap dielectric layer and electrically coupled to the metal units.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hua Chu, Chun-Wen Cheng
  • Patent number: 9049756
    Abstract: Multiple control modules (14, 16, 18) provide various power control functions including occupancy sensing, ambient light level sensing, manual touch switch (push button) preset stations, light dimming and power control relay switching. The control modules (14, 16, 18) are interconnected in a conventional four-wire local area network for executing different power control functions in response to remote wireless commands as well as preset manual switch commands at the wall box level. The local area network (12) supplies DC operating power and communicates programming command and control module status information signals to all network control modules (14, 16, 18). One or more control modules (14, 16, 18) include an infrared signal sensor, a laser signal sensor, a signal decoder, a data microcontroller, a parameter lookup table and multiple light emitting diodes (LEDs).
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: June 2, 2015
    Assignee: Koninklijke Philips N.V.
    Inventors: Donald Louis Klusmann, Michael Shawn Murphy
  • Patent number: 8981431
    Abstract: A semiconductor light emitting device including: a substrate made of GaAs; and a semiconductor layer formed on the substrate, in which part of the substrate on a side opposite to the semiconductor layer is removed by etching so that the semiconductor light emitting device has a thickness of not more than 60 ?m.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: March 17, 2015
    Assignee: Rohm Co., Ltd.
    Inventors: Tadahiro Hosomi, Kentaro Mineshita
  • Patent number: 8975637
    Abstract: A thin film diode (100A) includes a semiconductor layer (130) having first, second, and third semiconductor regions, a first insulating layer (122) formed on the semiconductor layer (130), and a second insulating layer (123) formed on the first insulating layer (122). The first semiconductor region (134A) contains an impurity of a first-conductivity type at a first concentration; the second semiconductor region (135A) contains an impurity of a second-conductivity type different from the first conductivity type at a second concentration; and the third semiconductor region (133A) contains the first-conductivity type impurity at a third concentration lower than the first concentration, or contains the second-conductivity type impurity at a third concentration lower than the second concentration. The first semiconductor region (134A) conforms to an aperture pattern in the second insulating layer (123), or the second semiconductor region (135A) conforms to an aperture pattern in the second insulating layer (123).
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: March 10, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Matsukizono, Tomohiro Kimura, Hiroyuki Ogawa
  • Patent number: 8970516
    Abstract: This disclosure provides systems, methods and apparatus for combining devices deposited on a first substrate, with integrated circuits formed on a second substrate such as a semiconducting substrate or a glass substrate. The first substrate may be a glass substrate. The first substrate may include conductive vias. A power combiner circuit may be deposited on a first side of the first substrate. The power combiner circuit may include passive devices deposited on at least the first side of the first substrate. The integrated circuit may include a power amplifier circuit disposed on and configured for electrical connection with the power combiner circuit, to form a power amplification system. The conductive vias may include thermal vias configured for conducting heat from the power amplification system and/or interconnect vias configured for electrical connection between the power amplification system and a conductor on a second side of the first substrate.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: March 3, 2015
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Justin Phelps Black, Ravindra V. Shenoy, Evgeni Petrovich Gousev, Aristotele Hadjichristos, Thomas Andrew Myers, Jonghae Kim, Mario Francisco Velez, Je-Hsiung Jeffrey Lan, Chi Shun Lo
  • Patent number: 8969980
    Abstract: A micro-electromechanical system (MEMS) device includes a housing and a base. The base includes a port opening extending therethrough and the port opening communicates with the external environment. The MEMS die is disposed on the base and over the opening. The MEMS die includes a diaphragm and a back plate and the MEMS die, the base, and the housing form a back volume. At least one vent extends through the MEMS die and not through the diaphragm. The at least one vent communicates with the back volume and the port opening and is configured to allow venting between the back volume and the external environment.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: March 3, 2015
    Assignee: Knowles Electronics, LLC
    Inventor: Sung Bok Lee
  • Patent number: 8962419
    Abstract: A process of forming a CMOS integrated circuit by forming a first stressor layer over two MOS transistors of opposite polarity, removing a portion of the first stressor layer from the first transistor, and forming a second stressor layer over the two transistors. A source/drain anneal is performed, crystallizing amorphous regions of silicon in the gates of the two transistors, and subsequently removing the stressor layers. A process of forming a CMOS integrated circuit by forming two transistors of opposite polarity, forming a two stressor layers over the transistors, annealing the integrated circuit, removing the stressor layers, and siliciding the transistors. A process of forming a CMOS integrated circuit with an NMOS transistor and a PMOS transistor using a stress memorization technique, by removing the stressor layers with wet etch processes.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: February 24, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Russell Carlton McMullan, Dong Joo Bae
  • Patent number: 8952400
    Abstract: A light emitting diode is disclosed. The disclosed light emitting diode includes a light emitting structure including a first-conductivity-type semiconductor layer, an active layer, and a second-conductivity-type semiconductor layer. The first-conductivity-type semiconductor layer, active layer, and second-conductivity-type semiconductor layer are disposed to be adjacent to one another in a same direction. The active layer includes well and barrier layers alternately stacked at least one time. The well layer has a narrower energy bandgap than the barrier layer. The light emitting diode also includes a mask layer disposed in the first-conductivity-type semiconductor layer, a first electrode disposed on the first-conductivity-type semiconductor layer, and a second electrode disposed on the second-conductivity-type semiconductor layer. The first-conductivity-type semiconductor layer is formed with at least one recess portion.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: February 10, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventors: Myung Hoon Jung, Hyun chul Lim, Sul Hee Kim, Rak Jun Choi
  • Patent number: 8907385
    Abstract: A backside illumination image sensor structure comprises an image sensor formed adjacent to a first side of a semiconductor substrate, wherein a first dielectric layer formed over the first side of the semiconductor substrate and an interconnect layer formed over the first dielectric layer. The image sensor structure further comprises a backside illumination film formed over a second side of the semiconductor substrate and a first silicon halogen compound layer formed between the second side of the semiconductor substrate and the backside illumination film.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Chin-Nan Wu, Chun-Che Lin
  • Patent number: 8896083
    Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 25, 2014
    Assignee: Board of Regents, The University of Texas System
    Inventors: Yeul Na, Krishna C. Saraswat
  • Patent number: 8878264
    Abstract: A global shutter pixel cell includes a serially connected anti-blooming (AB) transistor, storage gate (SG) transistor and transfer (TX) transistor. The serially connected transistors are coupled between a voltage supply and a floating diffusion (FD) region. A terminal of a photodiode (PD) is connected between respective terminals of the AB and the SG transistors; and a terminal of a storage node (SN) diode is connected between respective terminals of the SG and the TX transistors. A portion of the PD region is extended under the SN region, so that the PD region shields the SN region from stray photons. Furthermore, a metallic layer, disposed above the SN region, is extended downwardly toward the SN region, so that the metallic layer shields the SN region from stray photons. Moreover, a top surface of the metallic layer is coated with an anti-reflective layer.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: November 4, 2014
    Assignee: Aptina Imaging Corporation
    Inventors: Sergey Velichko, Jingyi Bai
  • Patent number: 8860122
    Abstract: A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source and drain regions. A gate stack is above the substrate over the channel region and between the pair of source and drain regions. The gate stack includes a high dielectric constant blocking region.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: October 14, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Igor Polishchuk, Sagy Levy
  • Patent number: 8860096
    Abstract: An SRAM cell of a semiconductor device includes a load transistor, a driver transistor and an access transistor. First source/drains of the load, driver and access transistors are connected to a node. A power line, a ground line and a bit line are electrically connected to second source/drains of the load transistor, the driver transistor and the access transistor. The power line, the ground line and the bit line are disposed at substantially the same level to extend in a first direction. A word line is electrically connected to a gate of the access transistor to extend in a second direction perpendicular to the first direction. The word line is disposed at a different level from the level of the power line, the ground line and the bit line.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: October 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: OhKyum Kwon, Byungsun Kim, Taejung Lee
  • Patent number: 8853747
    Abstract: A package is made of a transparent substrate having an interferometric modulator and a back plate. A non-hermetic seal joins the back plate to the substrate to form a package, and a desiccant resides inside the package. A method of packaging an interferometric modulator includes providing a transparent substrate and manufacturing an interferometric modulator array on a backside of the substrate. A back plate includes a curved portion relative to the substrate. The curved portion is substantially throughout the back plate. The back plate is sealed to the backside of the substrate with a back seal in ambient conditions, thereby forming a package.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: October 7, 2014
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Lauren Palmateer, Brian J. Gally, William J. Cummings, Manish Kothari, Clarence Chui
  • Patent number: 8835197
    Abstract: The present invention provides an active matrix organic light-emitting diode and a manufacturing method thereof. The active matrix organic light-emitting diode includes an organic light-emitting diode body and a thin-film transistor electrically connected to the organic light-emitting diode body. The thin-film transistor is formed on a substrate and includes semiconductor layer formed on the substrate, a gate insulation layer formed on the semiconductor layer, a gate terminal formed on the gate insulation layer, a protection layer formed on the gate terminal, and a source terminal and a drain terminal formed on the protection layer. The light-emitting diode body includes an anode formed on the protection layer and electrically connected to the thin-film transistor, an organic light emission layer formed on the anode, and a cathode formed on the organic light emission layer. The organic light-emitting diode body is arranged to be positioned above the thin-film transistor in an alternate manner.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: September 16, 2014
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Yuanchun Wu
  • Patent number: 8823127
    Abstract: A multijunction photovoltaic (PV) cell includes a bottom flexible substrate and a bottom metal layer located on the bottom flexible substrate. The multijunction photovoltaic cell also includes a semiconductor layer located on the bottom metal layer and a stack having a plurality of junctions located on the semiconductor layer, each of the plurality of junctions having a respective bandgap. The pluralities of junctions are ordered from the junction having the smallest bandgap being located on the substrate to the junction having the largest bandgap being located on top of the stack.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Norma Sosa Cortes, Keith E. Fogel, Devendra Sadana, Davood Shahrjerdi
  • Patent number: 8816357
    Abstract: An optical printer head has an array of lenses that project light emitted by an array of LEDs onto a charged photosensitive drum to form a latent image on the drum surface. A resin film adhered to the exposed surfaces of the lenses prevents chemical reaction between nitric acid, formed as a consequence of ozone produced during electric charging of the photosensitive drum, and alkali components on the surfaces of the lenses thereby preventing clouding of the lens surfaces and dimming of the projected light. The resin film has a thickness of 10 to 100 microns and may be formed of polyvinyl chloride, polyethylene terephthalate or polymethyl meta acrylate.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: August 26, 2014
    Assignee: Seiko I Infotech Inc.
    Inventors: Kazuya Utsugi, Toshikazu Suzuki
  • Patent number: 8809834
    Abstract: Apparatuses capable of and techniques for detecting long wavelength radiation are provided.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: August 19, 2014
    Assignee: University of Seoul Industry Cooperation Foundation
    Inventor: Doyeol Ahn
  • Patent number: 8802481
    Abstract: Apparatuses capable of and techniques for detecting the visible light spectrum are provided.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: August 12, 2014
    Assignee: University of Seoul Industry Cooperation Foundation
    Inventor: Doyeol Ahn
  • Patent number: 8797633
    Abstract: The present invention is directed to a display device assembly which comprises a display device and a luminance enhancement structure. The luminance enhancement structure is directly laminated onto an ITO layer with an adhesive. The assembly of the present invention provides improved performance of the luminance enhancement structure.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: August 5, 2014
    Assignee: SiPix Imaging, Inc.
    Inventors: Robert A. Sprague, Bryan Hans Chan, Craig Lin
  • Patent number: 8766330
    Abstract: Devices incorporating a single to a few-layer MoS2 channels in combination with optimized substrate, dielectric, contact and electrode materials and configurations thereof, exhibit light emission, photoelectric effect, and superconductivity, respectively.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: July 1, 2014
    Assignee: Georgetown University
    Inventors: Makarand Paranjape, Paola Barbara, Amy Liu, Marcio Fontana
  • Patent number: 8766306
    Abstract: A light emitting device and a method for manufacturing the light emitting device are disclosed. In one example, the light emitting device includes a transparent substrate, partially transparent an anode layer or layer assembly arranged on said substrate, a light emitting layer arranged on said anode layer, and a transparent cathode layer arranged on said light emitting layer, wherein said anode layer or layer assembly includes a first surface facing said transparent substrate and a second surface facing said light emitting layer and is positioned opposite to said first surface, said first surface includes a transparent conductive material, said second surface includes first and second domains, said first domains are conductive and non-transparent, said second domains are transparent and electrically isolating, and said first domains are in direct contact with said light emitting layer and are arranged to allow electrical contact between said first surface and said light emitting layer.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: July 1, 2014
    Assignee: Koninklijke Philips N.V.
    Inventors: Herbert Lifka, Sören Hartmann, Herbert Friedrich Boerner, Christoph Rickers
  • Patent number: 8691633
    Abstract: A semiconductor device is provided that includes a substrate, a static random access memory (SRAM) unit cell formed in the substrate, a first metal layer formed over the substrate the first metal layer providing local interconnection to the SRAM unit cell, a second metal layer formed over the first metal layer, the second metal layer including: a bit line and a complementary bit line each having a first thickness and a Vcc line disposed between the bit line and the complementary bit line, and a third metal layer formed over the second metal layer, the third metal layer including a word line having a second thickness greater than the first thickness.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 8680586
    Abstract: A semiconductor light emitting device including: a substrate made of GaAs; and a semiconductor layer formed on the substrate, in which part of the substrate on a side opposite to the semiconductor layer is removed by etching so that the semiconductor light emitting device has a thickness of not more than 60 ?m.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: March 25, 2014
    Assignee: ROHM Co., Ltd.
    Inventors: Tadahiro Hosomi, Kentaro Mineshita
  • Patent number: 8674515
    Abstract: A structure of connecting at least two integrated circuits in a 3D arrangement by a metal-filled through silicon via which simultaneously connects a connection pad in a first integrated circuit and a connection pad in a second integrated circuit.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Subramanian S. Iyer, Steven J. Koester, Huilong Zhu
  • Patent number: 8659110
    Abstract: A single-junction photovoltaic cell includes a doped layer comprising a dopant diffused into a semiconductor substrate; a patterned conducting layer formed on the doped layer; a semiconductor layer comprising the semiconductor substrate located on the doped layer on a surface of the doped layer opposite the patterned conducting layer; and an ohmic contact layer formed on the semiconductor layer.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Devendra Sadana, Davood Shahrjerdi, Norma E. Sosa Cortes, Brent A. Wacaser
  • Patent number: 8648397
    Abstract: A switching element (a semiconductor device) (18) having a top gate electrode (21) and a bottom gate electrode (23) is provided with a silicon layer (a semiconductor layer) (SL) that is arranged between the top gate electrode (21) and the bottom gate electrode (a light-shielding film) (23) and that has a source region (24), a drain region (28), a channel region (26), and low-concentration impurity regions (25, 27). Furthermore, the bottom gate electrode (23) is arranged so as to overlap the channel region (26), a part of the low-concentration impurity region (25), which is adjacent to the source region (24), and a part of the low-concentration impurity region (27), which is adjacent to the drain region (28). The bottom gate electrode (23) is controlled so as to have a prescribed potential.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: February 11, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Seiji Kaneko, Hidehito Kitakado
  • Patent number: 8614756
    Abstract: An apparatus for acquiring an i-bit digital code by a first stage AD conversion and a j-bit digital code by a second stage AD conversion includes a comparing unit which compares a reference signal and an analog signal in the first stage AD conversion; and an amplifying unit for outputting an amplified residual signal acquired by amplifying a difference between the analog signal and an analog signal corresponding to the i-bit digital code. The comparing unit compares the amplified residual signal and the reference signal in the second stage AD conversion.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: December 24, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Daisuke Yoshida
  • Patent number: 8610048
    Abstract: A method for producing a photosensitive integrated circuit including producing circuit control transistors, producing, above the control transistors, and between at least one upper electrode and at least one lower electrode, at least one photodiode, by amorphous silicon layers into which photons from incident electromagnetic radiation are absorbed, producing at least one passivation layer, between the lower electrode and the control transistors, and producing, between the control transistors and the external surface of the integrated circuit, a reflective layer capable of reflecting photons not absorbed by the amorphous silicon layers.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 17, 2013
    Assignee: STMicroelectronics S.A.
    Inventors: Jerome Alieu, Simon Guillaumet, Christophe Legendre, Hughes Leininger, Jean-Pierre Oddou, Marc Vincent
  • Patent number: 8598567
    Abstract: Photoconductive optoelectronic devices, such as photodetectors and photovoltaics, are provided. The devices are sensitized to a particular wavelength (or range of wavelengths) of electromagnetic radiation such that the devices provide increased performance efficiency (e.g., external quantum efficiency) at the wavelength. The devices include a photoconductive semiconductor layer spanning an electrode gap between two electrodes to provide a photoconductive electrical conduit. Abutting the semiconductor layer is a plurality of plasmonic nanoparticles. The improved efficiency of the devices results from wavelength-dependent plasmonic enhancement of device photosensitivity by the plasmonic nanoparticles.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: December 3, 2013
    Assignee: University of Washington through its Center for Commercialization
    Inventors: Ludan Huang, Lih Y. Lin
  • Patent number: 8587038
    Abstract: According to one embodiment, an electric component includes: a first insulating layer formed on a first wire; a second wire and a functional element formed on the first insulating layer; a second insulating layer formed on the first insulating layer; and a connection wire that connects the second wire and the first wire. In the connection wire, a first via, a second via, and an inter-via wire are integrally formed of the same material. The first via is formed in the second insulating layer. The second via is formed in the first and second insulating layers.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: November 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihiro Kojima