Abstract: Electromagnetic energy is detected with high efficiency in the spectral range having wavelengths of about 1–2 microns by coupling an absorber layer having high quantum efficiency in the spectral range having wavelengths of about 1–2 microns to an intrinsic semiconducting blocking region of an impurity band semiconducting device included in a solid state photon detector.

Abstract: The invention relates to a semiconductor device including a plurality of thin film transistors provided on a base member having a curved surface. The surface may be bent in either a convex shape or a concave shape. All channel length directions of the plurality of thin film transistors may also be aligned in the same direction. Further, the channel length direction may be different from the direction in which the base member is bent. A pixel portion and a driver circuit portion may also be provided on the base member. The invention also includes a method of manufacturing a semiconductor device including forming a layer to be peeled including an element of a substrate, bonding a support member to the layer to be peeled, and bonding a transfer body to the layer to be peeled.

Abstract: A transistor having at least one of a source electrode and a drain electrode being formed of a porous film is described. The transistor maintains its characteristics even after being subjected to a high temperature and high humidity environment. The transistor may be used in a circuit board, a display and electronic equipment.

Abstract: Embodiments of the invention provide an image sensor having an improved dynamic range. A pixel cell comprises at least one transistor structure. The transistor structure comprises at least one semiconductor channel region, at least one gate for controlling the channel region, and first and second leads respectively coupled to a source region on one side of the at least one channel region and a drain region on an opposite side of the at least one channel region. The transistor structure has at least two threshold voltages associated with the at least one channel region, and an I-V characteristic of the transistor structure is determined at least in part by the threshold voltages.

Abstract: There is provided an electro-optical device including, above a substrate, data lines extending in a first direction, scanning lines extending in a second direction and intersecting the data lines, pixel electrodes and thin film transistors disposed so as to correspond to intersection regions of the data lines and the scanning lines; and storage capacitors electrically connected to the thin film transistors and the pixel electrodes, the thin film transistors including semiconductor layers having channel regions which extend in a longitudinal direction and channel adjacent regions which extend further from the channel regions in the longitudinal direction, and the scanning lines including light-shielding parts disposed at sides of the channel regions.

Abstract: Methods and apparatuses are disclosed relating to blocking ultraviolet electromagnetic radiation from a semiconductor. Ultraviolet electromagnetic radiation, such as ultraviolet electromagnetic radiation generated by a plasma process, which may otherwise damage a semiconductor can be blocked from one or more layers below an ultraviolet blocking layer.

Abstract: The invention provides an active matrix type electro-optical device and an electronic apparatus using the same capable of preventing interference of light due to contact holes and interference of reflecting light from light-reflecting film. In a thin film transistor (TFT) array substrate of a reflective active matrix type electro-optical device, a light-reflecting film can be formed in a contact hole, but positions of the contact holes for electrically connecting a pixel electrode to a drain electrode, and irregular pattern for scattering light formed on the surface of the reflection film by a lower side irregularity-formation film are different in each of pixels formed in a matrix.

Abstract: On a transparent electrically insulating substrate, formed are a scanning line, and a gate electrode of a switching element, further formed are a gate insulating film, a semiconductor layer, an n+-Si layer to be formed into a source electrode and a drain electrode. After the patterning of the foregoing structure, the dielectric film is formed, and the portion corresponding to the contact hole is removed by etching, and photosensitive resin is applied to form the interlayer insulating film. Then, the transparent electrode is extended from the pixel electrode over the switching element, whereon a conversion layer and a gold layer for use in electrode are vapor-deposited. In this structure, an increase in capacitor between the pixel electrode and the signal line can be suppressed by the interlayer insulating film, and the transparent electrode functions as a top gate and release excessive electric charge.

Abstract: The present invention provides a semiconductor device wherein the area of a peripheral circuit region with respect to a pixel region is reduced, and provides a manufacturing method of the semiconductor device. A semiconductor device according to the present invention is characterized by having a pixel region 1, peripheral circuit regions 2a to 2c arranged in at least a part of the periphery of the pixel region, and a wiring formed in the peripheral circuit region, and by having a wiring multilayered with two or more layers. At least one layer of the multilyered wiring is formed from a low resistance material. Transistors are formed in the peripheral circuit region, and the multilayer wiring with two or more layers is formed on the upper side of the transistors.

Abstract: A pixel cell comprises a photo-conversion device for generating charge and a gate controlled charge storage region for storing photo-generated charge under control of a control gate. The charge storage region can be a single CCD stage having a buried channel to obtain efficient charge transfer and low charge loss. The charge storage region is adjacent to a gate of a transistor. The transistor gate is adjacent to the photo-conversion device and, in conjunction with the control gate, transfers photo-generated charge from the photo-conversion device to the charge storage region.

Abstract: An active pixel includes a a photosensitive element formed in a semiconductor substrate. A transfer transistor is formed between the photosensitive element and a floating diffusion and selectively operative to transfer a signal from the photosensitive element to the floating diffusion. The floating diffusion is formed from an n-type implant with a dosage in the range of 5e13 to 5e14 ions/cm2. Finally, an amplification transistor is controlled by the floating diffusion.

Abstract: An organic electroluminescent display device includes a first substrate, a second substrate spaced apart and facing the first substrate, a switching thin film transistor disposed on an inner surface of the first substrate, a driving thin film transistor electrically connected to the switching thin film transistor, a connecting electrode electrically connected to the driving thin film transistor, a first electrode disposed on an inner surface of the second substrate, a partition wall disposed on the first electrode and having a transmissive hole corresponding to a pixel region between the first and second substrates, an organic layer disposed within the transmissive hole on the first electrode, and a second electrode disposed on the organic layer, wherein the second electrode is electrically connected to the driving thin film transistor through the connecting electrode.

Abstract: A thin film transistor display includes a driving circuit and an active matrix. The driving circuit comprises a first thin film transistor structure. The first thin film transistor structure includes a first gate, source and drain regions, a first LDD region, a second LDD region and a first channel region between the first and the second LDD regions. The first gate region is disposed over the first channel region, and partially or completely overlies the first and the second LDD regions. The active matrix is controlled by the driving circuit and comprises a second thin film transistor structure. The second thin film transistor structure includes a second gate, source and drain regions, a third LDD region, a fourth LDD region and a second channel region between the third and the fourth LDD regions. The second gate region is disposed over the second channel region and substantially overlaps with neither of the first and the second LDD regions.

Abstract: The invention relates to an avalanche radiation detector comprising a semiconductor substrate (HK) with a front side (VS) and a back side (RS), an avalanche region (AB) which is arranged in the semiconductor substrate (HK) on the front side (VS) of the semiconductor substrate (HK) and a control electrode (R) for adjusting the electric field strength in the avalanche region (AB). It is proposed that the control electrode (R) is also arranged on the front side of the semiconductor substrate (HK).

Abstract: Magnetoresistive random access memory (MRAM) is used to provide in-pixel memory circuits for display devices. A memory circuit (25) comprises memory elements, for storing a drive setting, and a read-out circuit, for example a flip-flop circuit (64), for reading-out the stored drive setting. The memory elements comprise two MRAMs (60, 62), each coupled to a respective input of the flip-flop circuit (64). A drive circuit (26) is coupled to the read-out circuit and a pixel display electrode (27) for driving the pixel display electrode (27) dependent upon the read-out drive setting with drive current that does not pass through the MRAMs (60, 62). A display device (1) is provided comprising a plurality of pixels (20) each associated with one such memory circuit (25) and drive circuit (26).

Abstract: A gate length L of a second TFT (21) is set longer than the gate length L of a peripheral TFT. This arrangement makes it possible to accurately control even a small current, using the second TFT (21).

Abstract: An interconnect architecture for connecting a plurality of closely-spaced electrical elements on a first integrated circuit fabricated structure with operative circuits on a second integrated circuit fabricated structure. In one embodiment, the first integrated circuit fabricated structure comprises a plurality of photo sensors. Conductive interconnect elements on the first integrated circuit fabricated structure provide electrical connection between individual photo sensors and the operative circuitry on the second integrated circuit fabricated structure.

Abstract: CMOS and CCD imaging devices comprising different in-pixel capacitors and peripheral capacitors and methods of formation are disclosed. The capacitors used in periphery circuits have different requirements from the capacitors used in the pixel itself. Dual stack capacitors comprising two dielectric layers may be provided to achieve low leakage and high capacitance. A single masking step may be provided such that one region has a dual dielectric capacitor and a second region has a single dielectric capacitor. A different dielectric may also be provided in one region compared to another region wherein the inter-electrode insulator comprises a single dielectric in both regions.

Abstract: The solid-state imaging device according to the present invention comprises: a plurality of light-sensitive elements 1 arranged in a matrix form at regular spacings in a photoreceiving region provided on a semiconductor substrate; a plurality of detecting electrodes provided on the semiconductor substrate corresponding to the plurality of the light-sensitive elements for detecting an electrical charge generated by each light-sensitive element; a light-shielding film 58 coating the plurality of detecting electrodes and having an aperture 65 over each light-sensitive element; and a plurality of reflecting walls 62, which are formed in a grid pattern over the light-shielding film so as to partition the apertures individually over the respective light-sensitive elements, for reflecting a portion of light entering the semiconductor substrate from above onto the aperture on each light-sensitive element.

Abstract: A charge-coupled device for forming an electronic representation of an image from incident light, the charge-coupled device includes a substrate of a first type; a photosensitive area of a second type disposed in the substrate for receiving the incident light which is converted to a charge packet; a transfer mechanism for activating transfer of the charge packet through the charge-coupled device; an output mechanism for receiving the transferred charge packet; a reset operator for resetting the output mechanism to a charge voltage; and a logical element disposed on the substrate that inputs a gate waveform to the reset operator for activating the resetting operation of the reset operator.

Abstract: A programmable sensor array (1) having a plurality of programmable cells (2). Each of the cells (2) comprises a programmable module (4) and a sensor element(6) operatively coupled to the programmable module. There is also an analogue module (8), typically an analogue to digital converter, that provides the operatively coupling of the sensor element (6) to the programmable module (4). The sensor element (6), programmable module (4) and analogue module (8) are in a stacked relationship.

Abstract: A plurality of apertures is formed in at least one first insulating layer disposed over a sensor formed in a semiconductor substrate. A second insulating layer is disposed over the at least one first insulating layer and the plurality of apertures in the at least one first insulating layer. The apertures form hollow regions in the at least one first insulating layer over the sensor, allowing more light or energy to pass through the at least one first insulating layer to the sensor, and increasing the sensitivity of the sensor.

Abstract: A semiconductor integrated circuit having a high withstand voltage TFT and a TFT which is capable of operating at high speed in a circuit of thin film transistors (TFT) and methods for fabricating such circuit will be provided. A gate insulating film of the TFT required to operate at high speed (e.g., TFT used for a logic circuit) is relatively thinned less than a gate insulating film of the TFT which is required to have high withstand voltage (e.g., TFT used for switching high voltage signals).

Abstract: Nanoclusters are blanket deposited on an integrated circuit and then removed from regions where the nanoclusters are not desired. A sacrificial layer is formed in those regions where the nanoclusters are not desired prior to the blanket deposition. The nanoclusters and the sacrificial layer are then removed. In one form, the sacrificial layer includes a deposited nitride containing or oxide containing layer. Alternatively, the sacrificial layer includes at least one of a pad oxide or a pad nitride layer previously used to form isolation regions in the substrate. Nanocluster devices and non-nanocluster devices may then be integrated onto the same integrated circuit. The use of a sacrificial layer protects underlying layers thereby preventing the degradation of performance of the subsequently formed non-nanocluster devices.

Abstract: An organic electroluminescent display device includes a first substrate, a second substrate spaced apart and facing the first substrate, a switching thin film transistor disposed on an inner surface of the first substrate, a driving thin film transistor electrically connected to the switching thin film transistor, a connecting electrode electrically connected to the driving thin film transistor, a first electrode disposed on an inner surface of the second substrate, a partition wall disposed on the first electrode and having a transmissive hole corresponding to a pixel region between the first and second substrates, an organic layer disposed within the transmissive hole on the first electrode, and a second electrode disposed on the organic layer, wherein the second electrode is electrically connected to the driving thin film transistor through the connecting electrode.

Abstract: A semiconductor device including an overcoat layer of a transparent material disposed on a substrate, a projection formed on the overcoat layer, a convex intralayer lens of an inorganic material formed to include the projection as a core and a transparent film with a flat top surface formed on the convex intralayer lens.

Abstract: A solid-state image sensing device includes a plurality of pixels. Each pixel has a photodiode, a first transistor, and a second transistor. The photodiode is constituted by a first-conductivity-type semiconductor region and a second-conductivity-type semiconductor region. The first and second conductivity types are opposite to each other. The first transistor has a first-conductivity-type drain region formed in the second-conductivity-type semiconductor region to transfer signal charge to the drain region. The second transistor has a source region and a drain region which are formed in the second-conductivity-type semiconductor region and which have the first conductivity type. At least one second-conductivity-type potential barrier is provided under the drain region of the first transistor and the source region and/or the drain region of the second transistor.

Abstract: An electro-optical device having a plurality of pixels including a plurality of EL elements, wherein the electro-optical device provides a gray scale display by controlling a period of time at which the plurality of the EL elements emit light in one frame period; the plurality of the EL elements have a first electrode and a second electrode; the first electrode is held at a constant potential; and a potential of the second electrode changes in such a manner that a polarity of an EL driving voltage, which is a difference between the potentials applied to the first and second electrodes, is inverted for each one frame period.

Abstract: On a transparent electrically insulating substrate, formed are a scanning line, and a gate electrode of a switching element, further formed are a gate insulating film, a semiconductor layer, an n+-Si layer to be formed into a source electrode and a drain electrode. After the patterning of the foregoing structure, the dielectric film is formed, and the portion corresponding to the contact hole is removed by etching, and photosensitive resin is applied to form the interlayer insulating film. Then, the transparent electrode is extended from the pixel electrode over the switching element, whereon a conversion layer and a gold layer for use in electrode are vapor-deposited. In this structure, an increase in capacitor between the pixel electrode and the signal line can be suppressed by the interlayer insulating film, and the transparent electrode functions as a top gate and release excessive electric charge.

Abstract: The present invention relates to an organic thin film transistor (OTFT) comprising: a substrate (1), a gate electrode (2) formed on the substrate (1), a gate insulation layer formed on the gate electrode, a source electrode (5) and a drain electrode (6) formed on the gate insulation layer including a first insulation layer (3) and a second insulation layer (4) with different dielectric constants, and an active layer (7) which overlays the source electrode (5) and the drain electrode (6). Without adding the conventional complicated processes like photolithography but adding two simple processes of spin coating or vaporously coating the second insulation film and self-aligned dry RIE, the present invention not only can improve the carrier's injection property so as to improve the OTFT device's properties, but also can block the leakage current of the gate insulation layer and reduce the device's parasitic capacitance.

Abstract: The invention provides an elevated photodiode for image sensors and methods of formation of the photodiode. Elevated photodiodes permit a decrease in size requirement for pixel sensor cells while reducing leakage, image lag and barrier problems typically associated with conventional photodiodes.

Abstract: Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted.

Abstract: A new grid metal design for image sensors is disclosed which is comprised of a semiconductor image sensor chip having a pixel region covering most of the chip and a logic circuit region on the chip periphery. The pixel region contains an array of image pixels where for each image pixel the majority of its area is occupied by a light sensing element and the other image pixel circuit elements are arranged in the periphery of the image pixel without overlapping the image-sensing element. A number of metal levels are of the first type, at which functional metal patterns exist both for the chip peripheral logic circuits and for the pixel circuit elements. A number of metal levels are of the second type, at which functional metal patterns exist only for the chip peripheral logic circuits and dummy metal patterns cover the pixel region except for the light sensing elements.

Abstract: A pixel TFT formed in a pixel region is formed on a first substrate by a channel etch type reverse stagger type TFT, and patterning of a source region and a drain region, and patterning of a pixel electrode are performed by the same photomask. A driver circuit formed by using TFTs having a crystalline semiconductor layer, and an input-output terminal dependent on the driver circuit, are taken as one unit. A plurality of units are formed on a third substrate, and afterward the third substrate is partitioned into individual units, and the obtained stick drivers are mounted on the first substrate.

Abstract: A method is provided to fabricate a LCOS back plane structure. The present invention utilized a HV device such as HV CMOS transistor (high voltage complementary metal oxide semiconductor transistor) and a HV capacitor layer are applied to the substrate. Furthermore, the HV capacitor layer has a higher dielectric layer and coupling ratio to sustain the higher operating voltage, such that the operating capacitance can be raised. Moreover, the HV CMOS transistor is combined with a mirror layer which has a higher reflective property, such that the LCOS back-plate structure has the better contrast and chrominance output in per area unit, when the operating voltage range is increased.

Abstract: In a semiconductor device including bottom-gate-type thin-film transistors, each of which includes a gate electrode provided on an insulating surface of a substrate, a semiconductor layer provided on the gate electrode via a gate insulating layer, a pair of doped semiconductor layers adjacent to the semiconductor layer, and source and drain electrodes consisting of a pair of conductors adjacent to corresponding ones of the pair of doped semiconductor layers, the thickness of portions of the semiconductor layer below the source and drain electrodes is smaller than the thickness of a portion of the semiconductor layer at a gap portion between the source and drain electrodes.

Abstract: An active pixel sensor for producing images from electron-hole producing radiation includes a crystalline semiconductor substrate having an array of electrically conductive diffusion regions, an interlayer dielectric (ILD) layer formed over the crystalline semiconductor substrate and comprising an array of contact electrodes, and an interconnect structure formed over the ILD layer, wherein the interconnect structure includes at least one layer comprising an array of conductive vias. An array of patterned metal pads is formed over the interconnect structure and are electrically connected to an array of charge collecting pixel electrodes. A radiation absorbing structure includes a photoconductive N-I-B-P photodiode layer formed over the interconnect structure, and a surface electrode layer establishes an electrical field across the radiation absorbing structure and between the surface electrode layer and each of the array of charge collecting pixel electrodes.

Abstract: In a solid-state image pick-up device 10 in which a microlens layer 16 is provided on a surface of a semiconductor substrate 11 having photoelectric converting units 12H and 12L for storing an electric charge corresponding to an amount of incident light arranged vertically and horizontally, a microlens 16H to be provided on the microlens layer 16 is disposed on only the photoelectric converting unit 12H to be used as a pixel having a high sensitivity and the microlens layer 16 in a position facing the photoelectric converting unit 12L to be used as a residual pixel having a low sensitivity has a planar structure 16L or a perforated structure 16L.

Abstract: A semiconductor light receiving device is provided, which comprises a semiconductor substrate, a collector region, a base region, and an emitter region, an insulating film covering the surface of the collector region, the base region, and the emitter region, a first metal line on the insulating film at a position corresponding to the base region and being electrically connected to the emitter region, and a second metal line on the insulating film at a position corresponding to a junction portion of the base region and the collector region and being electrically connected to the emitter region. The first metal line has a sloped surface such that incident light falling on the first metal line is reflected and directed toward the surface of the base region.

Abstract: An integrated circuit includes an output buffer operable to drive an output node. The output buffer may comprise a MOSFET having a JFET integrated within a portion of a drain region of the MOSFET. The JFET may comprise a gate of second conductivity formed in semiconductor material of first conductivity type, which is contiguous with the drain region for the MOSFET. A voltage shaping circuit may control a bias of the JFET gate in accordance with the voltage levels of an output node and a predetermined output impedance.

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, and an array formed thereby, whereby each memory cell includes a trench formed into a surface of a semiconductor substrate, spaced apart source and drain regions with a channel region formed therebetween. The drain region is formed underneath the trench, and the channel region includes a first portion that extends substantially vertically along a sidewall of the trench and a second portion that extends substantially horizontally along the surface of the substrate. An electrically conductive floating gate is formed over and insulated from at least a portion of the channel region and a portion of the source region. An electrically conductive control gate is formed having a first portion disposed in the trench and a second portion formed over but insulated from the floating gate.

Abstract: The present invention relates to an AC drive surface discharge type plasma display panel having an isosceles delta array type pixel. The background art has a problem of being apt to cause a wrong writing discharge and having a narrow writing voltage margin. Then, in the present invention, transparent electrodes for X electrode (T3, T4) in first and second pair subpixel regions (PSPR1, PSPR2) of an isosceles delta array type pixel (P1) are provided at portions farther away from a first write electrode (Wj(B)) in an isolated subpixel region (ISPR). Specifically, a central axis of the third transparent electrode (T3) along a vertical direction (v) is positioned closer to an extending portion (WAE) of a second write electrode (Wj(A)) from a vertical direction central axis of the first pair subpixel region (PSPR1).

Abstract: A TFT array panel and a method for fabricating the same is disclosed, wherein an adhesion force between an elongated wire and a TFT array panel pad is improved by increasing the contact area of a bonding pad. The TFT array panel pad includes a first conductive layer formed in a pad region on an insulating substrate. The first conductive layer includes a plurality of conductive islands and holes. A second conductive layer is formed over and covers the first conductive layer.

Abstract: A sensor formed in a substrate of a first conductivity type in a first concentration to express a first intrinsic potential includes CMOS circuitry to control the sensor, a first well of the first conductivity type in a second concentration (greater than the first concentration) formed in the substrate to express a second intrinsic potential, and a photodiode region of a second conductivity type formed in the first well. The first and second intrinsic potentials induce a field between the substrate and the first well that repels photo generated charge from drifting from the substrate into the first well. Alternatively, a sensor formed in a substrate of a first conductivity type includes CMOS circuitry to control the sensor, a first well of a second conductivity type formed in the substrate, a second well of the first conductivity type formed in the first well, and a photodiode region of the second conductivity type formed in the second well.

Abstract: Shift register electrodes are formed in an imaging area and a peripheral area through use of a single layer of conductive film, and a thick insulating film is deposited over those electrodes and planarized. The thick insulating film overlying the shift register electrodes in the peripheral area is kept as it is and on the other hand, the thick insulating film overlying the shift register electrodes is etched to just fill gaps between the shift register electrodes with the film, thereby allowing a light shielding metal layer overlying the shift register electrodes in the peripheral area and insulating films sandwiched therebetween to be formed without discontinuity. Since metal interconnect lines in the peripheral area have a thick and planarized insulating film formed thereunder, parasitic capacitance between diffusion layers/electrodes and the metal interconnect lines can be reduced, leading to reduction in power consumption of image sensor.

Abstract: A semiconductor device comprises a plurality of superposed layers including a predetermined layer provided, in a peripheral part of a chip, with a dummy pattern of a material that is the same as that forming a wiring pattern formed in the same predetermined layer, the dummy pattern being formed on an inner side of a dicing region. The ratio of an area of the dummy pattern in a planar region defined by the inner edge of the dummy pattern, the outer edge of the dicing region and two optional, parallel lines to that of the planar region is 50% or above.

Abstract: A multilayer heterostructure is provided a planarization layer superjacent a semiconductor substrate. The planarization layer comprises tungsten, titanium, tantalum, copper, aluminum, single crystal silicon, polycrystalline silicon, amorphous silicon, borophosphosilicate glass (“BPSG”) or tetraethylorthosilicate (“TEOS”). A barrier film having a structural integrity is superjacent the planarization layer. A second layer is formed superjacent the barrier film. The second layer comprises tungsten, titanium, tantalum, copper, aluminum, borophosphosilicate glass (“BPSG”) or tetraethylorthosilicate (“TEOS”). Heating causes the planarization layer to expand according to a first thermal coefficient of expansion, the second layer to expand according to a second thermal coefficient of expansion, and the structural integrity of the barrier film to be maintained.

Abstract: A monolithic photodetector including a photodiode, a precharge MOS transistor, a control MOS transistor, a read MOS transistor, and a transfer MOS transistor, the photodiode and the transfer transistor being formed in a same substrate of a first conductivity type, the photodiode including a first region of the second conductivity type formed under a second region of the first conductivity type more heavily doped than the first region, and above a third region of the first conductivity type more heavily doped than the substrate, the first region being the source of the second conductivity type of the transfer transistor, the second and third regions being connected to the substrate and being at a fixed voltage.

Abstract: In a solid-state image pick-up device 10 in which a microlens layer 16 is provided on a surface of a semiconductor substrate 11 having photoelectric converting units 12H and 12L for storing an electric charge corresponding to an amount of incident light arranged vertically and horizontally, a microlens 16H to be provided on the microlens layer 16 is disposed on only the photoelectric converting unit 12H to be used as a pixel having a high sensitivity and the microlens layer 16 in a position facing the photoelectric converting unit 12L to be used as a residual pixel having a low sensitivity has a planar structure 16L or a perforated structure 16L.

Abstract: On a transparent electrically insulating substrate, formed are a scanning line, and a gate electrode of a switching element, further formed are a gate insulating film, a semiconductor layer, an n+-Si layer to be formed into a source electrode and a drain electrode. After the patterning of the foregoing structure, the dielectric film is formed, and the portion corresponding to the contact hole is removed by etching, and photosensitive resin is applied to form the interlayer insulating film. Then, the transparent electrode is extended from the pixel electrode over the switching element, whereon a conversion layer and a gold layer for use in electrode are vapor-deposited. In this structure, an increase in capacitor between the pixel electrode and the signal line can be suppressed by the interlayer insulating film, and the transparent electrode functions as a top gate and release excessive electric charge.