With Devices Vertically Spaced In Different Layers Of Semiconductor Material (e.g., "3-dimensional" Integrated Circuit) Patents (Class 257/278)
  • Patent number: 10388780
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a second electrode, and a first layer. The first layer includes at least one selected from the group consisting of silicon nitride, silicon oxide, and silicon oxynitride. The first layer includes a first portion, a second portion, and a third portion. The first portion is provided on the second electrode. The second portion is provided on the first portion. A content of silicon of the second portion is higher than a content of silicon of the first portion. A third portion is provided on the second portion. A content of silicon of the third portion is lower than the content of silicon of the second portion.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: August 20, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Tomotaka Narita
  • Patent number: 10204873
    Abstract: In some examples, a device includes a substrate and a conductive pad extending through the substrate, wherein the substrate is coupled to the conductive pad at an interface and the substrate extends laterally from the interface to define a substrate extension. In some examples, the device also includes a semiconductor die mounted on the first side of the substrate. In some examples, the device includes a breakpoint that defines a torque tolerance that is less than a torque tolerance of the device at other points. In some examples, the device is configured to break at the breakpoint in response to force being applied to the substrate extension on the first side of the substrate.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: February 12, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Chuan Cheah
  • Patent number: 10163930
    Abstract: A semiconductor device includes bit lines extending along a first direction, the bit lines being arranged along a second direction intersecting the first direction, a plurality of channel layers disposed under the bit lines, the plurality of channel layers extending in a third direction perpendicular to a plane extending along the first and second directions and spaced apart along the second direction, so that each channel layer is at least partially overlapped with at least two of the bit lines, and a contact plug extending, from the channel layer, toward one of the bit lines overlapped with the channel layer.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: December 25, 2018
    Assignee: SK Hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10050057
    Abstract: A semiconductor device includes bit lines extending along a first direction, the bit lines being arranged along a second direction intersecting the first direction, a plurality of channel layers disposed under the bit lines, the plurality of channel layers extending in a third direction perpendicular to a plane extending along the first and second directions and spaced apart along the second direction, so that each channel layer is at least partially overlapped with at least two of the bit lines, and a contact plug extending, from the channel layer, toward one of the bit lines overlapped with the channel layer.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 14, 2018
    Assignee: SK Hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 9941275
    Abstract: An Integrated Circuit device, including: a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single crystal transistors, where the second layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of the first transistors that cross the first dice lane, where a plurality of the second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to the plurality of the second transistors that cross the second dice lane, and at least one thermal conducting path from at least one of the second single crystal transistors to an external surface of the device.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: April 10, 2018
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • Patent number: 9917109
    Abstract: A semiconductor device includes a wiring embedded in an insulating layer, an oxide semiconductor layer over the insulating layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate electrode provided to overlap with the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode. The insulating layer is formed so that part of a top surface of the wiring is exposed. The part of the top surface of the wiring is positioned higher than part of a surface of the insulating layer. The wiring in a region exposed from the insulating layer is electrically connected to the source electrode or the drain electrode. The root-mean-square roughness of a region which is part of the surface of the insulating layer and in contact with the oxide semiconductor layer is 1 nm or less.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: March 13, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Teruyuki Fujii, Ryota Imahayashi
  • Patent number: 9905547
    Abstract: A chipset with light energy harvester, includes a substrate, a functional element layer, and a light energy harvesting layer, both are stacked vertically on the substrate, and an interconnects connected between the functional element layer and the light energy harvesting layer.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: February 27, 2018
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Chang-Hong Shen, Jia-Min Shieh, Wen-Hsien Huang, Tsung-Ta Wu, Chih-Chao Yang, Tung-Ying Hsieh
  • Patent number: 9679840
    Abstract: A computer implemented layout method for an integrated circuit (IC) structure and IC structure are provided. The layout method can include placing a circuit cell and an inter-layer via together in a first device layer of the IC structure, and placing a metal pattern in a second device layer of the IC structure. The inter-layer via and the metal pattern may be configured to form a direct connection channel for the circuit cell and the metal pattern.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: June 13, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Lin Chuang, Ching-Fang Chen, Jia-Jye Shen
  • Patent number: 9640445
    Abstract: A method of fabricating a switched-capacitor converter includes providing a semiconductor layer having a top surface and a bottom surface, forming switching elements on the top surface of the semiconductor layer, forming a first insulation layer and first interconnection patterns on the switching elements, forming a second insulation layer over the first insulation layer and the first interconnection patterns, forming a second interconnection pattern over the second insulation layer, forming a third insulation layer over the second insulation layer and the second interconnection pattern, forming third interconnection patterns and a lower interconnection pattern over the bottom surface of the semiconductor layer, forming a capacitor over the lower interconnection pattern, forming a fourth insulation layer over the bottom surface of the semiconductor layer to expose an upper electrode pattern of the capacitor, forming a fifth insulation layer covering the capacitor, and forming pads in the fifth insulation laye
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: May 2, 2017
    Assignee: SK Hynix Inc.
    Inventor: Jae Ho Hwang
  • Patent number: 9601204
    Abstract: A three-dimensional (3D) semiconductor memory device includes a CMOS circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower wiring structure and a memory structure sequentially stacked over the CMOS circuit structure. The memory structure overlaps a first circuit region of the CMOS circuit structure and does not overlap a second circuit region of the CMOS circuit structure, and the plurality of column blocks are contained within the first circuit region of the CMOS circuit structure.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: March 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jintaek Park, Youngwoo Park, Jaeduk Lee
  • Patent number: 9478284
    Abstract: An object of this invention is to provide a semiconductor memory device capable of increasing the read transfer rate by performing the read operation in parallel while suppressing the voltage drop when a large current is passed to a memory chain and reducing a chip area by reducing the number of peripheral circuits to feed power. A semiconductor memory device according to this invention includes upper and lower electrodes in a flat plate shape, first and second select transistors extending in first and second directions respectively, and a wire arranged between the first select transistor and the second select transistor and the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor (see FIG. 2).
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: October 25, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Sasago, Hiroyuki Minemura, Kenzo Kurotsuchi, Seiji Miura, Satoru Hanzawa
  • Patent number: 9177610
    Abstract: An apparatus includes a semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a differential signaling interface.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: November 3, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Manuel Antonio D'Abreu, Stephen Skala, Dimitris Pantelakis, Radhakrishnan Nair, Deepak Pancholi
  • Patent number: 9031684
    Abstract: A method and system for integrated circuit fabrication is disclosed. In an example, the method includes determining a first process parameter of a wafer and a second process parameter of the wafer, the first process parameter and the second process parameter corresponding to different wafer characteristics; determining a variation of a device parameter of the wafer based on the first process parameter and the second process parameter; constructing a model for the device parameter as a function of the first process parameter and the second process parameter based on the determined variation of the device parameter of the wafer; and performing a fabrication process based on the model.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Han Cheng, Chin-Hsiang Lin, Chi-Ming Yang, Chun-Lin Chang, Chih-Hong Hwang
  • Patent number: 8952441
    Abstract: According to one embodiment, a device includes a first fin structure having first to n-th semiconductor layers (n is a natural number equal to or more than 2) stacked in a first direction perpendicular to a surface of a semiconductor substrate, and extending in a second direction parallel to the surface of the semiconductor substrate, first to n-th memory cells provided on surfaces of the first to n-th semiconductor layers in a third direction perpendicular to the first and second directions respectively, and first to n-th select transistors connected in series to the first to n-th memory cells respectively.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiwamu Sakuma, Haruka Kusai, Yasuhito Yoshimizu, Masahiro Kiyotoshi
  • Patent number: 8900921
    Abstract: A semiconductor device has a core semiconductor device with a through silicon via (TSV). The core semiconductor device includes a plurality of stacked semiconductor die and semiconductor component. An insulating layer is formed around the core semiconductor device. A conductive via is formed through the insulating layer. A first interconnect structure is formed over a first side of the core semiconductor device. The first interconnect structure is electrically connected to the TSV. A second interconnect structure is formed over a second side of the core semiconductor device. The second interconnect structure is electrically connected to the TSV. The first and second interconnect structures include a plurality of conductive layers separated by insulating layers. A semiconductor die is mounted to the first interconnect structure. The semiconductor die is electrically connected to the core semiconductor device through the first and second interconnect structures and TSV.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: December 2, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Sun Mi Kim, OhHan Kim, KyungHoon Lee
  • Patent number: 8895370
    Abstract: A vertical conduction power device includes respective gate, source and drain areas formed in an epitaxial layer on a semiconductor substrate. The respective gate, source and drain metallizations are formed by a first metallization level. The gate, source and drain terminals are formed by a second metallization level. The device is configured as a set of modular areas extending parallel to each other. Each modular area has a rectangular elongate source area perimetrically surrounded by a gate area, and a drain area defined by first and second regions. The first regions of the drain extend parallel to one another and separate adjacent modular areas. The second regions of the drain area extend parallel to one another and contact ends of the first regions of the drain area.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 25, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Angelo Magri′
  • Patent number: 8884442
    Abstract: Through the intermetal dielectric (2) and the semiconductor material of the substrate (1) a contact hole is formed, and a contact area of a connection metal plane (3) that faces the substrate is exposed in the contact hole. A metallization (11) is applied, which forms a connection contact (12) on the contact area, a through-contact (13) in the contact hole and a connection contact (20) on a contact area facing away from the substrate and/or on a vertical conductive connection (15) of the upper metal plane (24).
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: November 11, 2014
    Assignee: ams AG
    Inventors: Jochen Kraft, Stefan Jessenig, Günther Koppitsch, Franz Schrank, Jordi Teva, Bernhard Löffler, Jörg Siegert
  • Patent number: 8871626
    Abstract: FinFETS and methods for making FinFETs with a vertical silicide structure. A method includes providing a substrate with a plurality of fins, forming a gate stack above the substrate wherein the gate stack has at least one sidewall and forming an off-set spacer adjacent the gate stack sidewall. The method also includes growing an epitaxial film which merges the fins to form an epi-merge layer, forming a field oxide layer adjacent to at least a portion of the off-set spacer and removing a portion of the field oxide layer to expose a portion of the epi-merge-layer. The method further includes removing at least part of the exposed portion of the epi-merge-layer to form an epi-merge sidewall and an epi-merge spacer region and forming a silicide within the epi-merge sidewall to form a silicide layer and two silicide sidewalls.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Chung-Hsun Lin, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 8803206
    Abstract: A 3D semiconductor device, including: a first layer including first transistors; a second layer including second transistors; where the second transistors are aligned to the first transistors, and a first circuit including at least one of the first transistors, where the first circuit has a first circuit output connected to at least one of the second transistors, and where at least one of the second transistors is connected to a device output, and where the device output includes a contact port for connection to external devices, and where at least one of the second transistors is substantially larger than at least one of the first transistors.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: August 12, 2014
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • Patent number: 8791506
    Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: July 29, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Ted Taylor, Xiawan Yang
  • Patent number: 8766332
    Abstract: A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: July 1, 2014
    Assignee: SanDisk 3D LLC
    Inventors: James M. Cleeves, Roy E. Scheuerlein
  • Patent number: 8754443
    Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device.
    Type: Grant
    Filed: September 15, 2012
    Date of Patent: June 17, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Suraj J. Mathew, Chandra Mouli
  • Patent number: 8735902
    Abstract: Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first direction, from a second surface of the semiconductor. Both arrays may be non-volatile memory arrays. For example, one of the memory arrays may be a NAND flash memory array, while the other may be a one-time-programmable memory array.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: May 27, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, John Zahurak, Siddartha Kondoju, Haitao Liu, Nishant Sinha
  • Patent number: 8697569
    Abstract: A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: April 15, 2014
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Craig Mitchell, Piyush Savalia
  • Publication number: 20140054585
    Abstract: A lateral semiconductor device having a vertical region for providing a protective avalanche breakdown (PAB) is disclosed. The lateral semiconductor device has a lateral structure that includes a conductive substrate, semi-insulating layer(s) disposed on the conductive substrate, device layer(s) disposed on the semi-insulating layer(s), along with a source electrode and a drain electrode disposed on the device layer(s). The vertical region is separated from the source electrode by a lateral region wherein the vertical region has a relatively lower breakdown voltage level than a relatively higher breakdown voltage level of the lateral region for providing the PAB within the vertical region to prevent a potentially damaging breakdown of the lateral region. The vertical region is structured to be more rugged than the lateral region and thus will not be damaged by a PAB event.
    Type: Application
    Filed: August 22, 2013
    Publication date: February 27, 2014
    Applicant: RF Micro Devices, Inc.
    Inventor: Andrew P. Ritenour
  • Patent number: 8633515
    Abstract: Embodiments of a semiconductor structure include a first current electrode region, a second current electrode region, and a channel region. The channel region is located between the first current electrode region and the second current electrode region, and the channel region is located in a fin structure of the semiconductor structure. A carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region. A contact extends into the first current electrode region and is electrically coupled to the first current electrode region.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: January 21, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Marius K. Orlowski, James D. Burnett
  • Patent number: 8624332
    Abstract: A vertical conduction electronic power device includes respective gate, source and drain areas in an epitaxial layer arranged on a semiconductor substrate. The respective gate, source and drain metallizations may be formed by a first metallization level. Corresponding gate, source and drain terminals or pads may be formed by a second metallization level. The power device is configured as a set of modular areas extending parallel to each other, each having a rectangular elongate source area perimetrically surrounded by a narrow gate area. The modular areas are separated from each other by regions with the drain area extending parallel and connected at the opposite ends thereof to a second closed region with the drain area forming a device outer peripheral edge.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: January 7, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Angelo Magrì
  • Patent number: 8574982
    Abstract: A method and circuit for implementing an embedded dynamic random access memory (eDRAM), and a design structure on which the subject circuit resides are provided. The embedded dynamic random access memory (eDRAM) circuit includes a stacked field effect transistor (FET) and capacitor. The capacitor is fabricated directly on top of the FET to build the eDRAM.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Karl Robert Erickson, David Paul Paulsen, John Edward Sheets, II, Kelly L. Williams
  • Patent number: 8513058
    Abstract: a method for producing a semiconductor device provided in such a manner that a first layer and a second layer are laminated to ensure that their TSVs are arranged in almost a straight line, including: first layer production steps including steps of preparing a substrate, forming a transistor of an input/output circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; second layer production steps including steps of preparing a substrate, forming a transistor of a logic circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; a connection step of connecting surfaces of the first layer and the second layer on a side opposite to substrates of the first layer and the second layer to ensure that the TSV of the first layer and the TSV of the second layer are arranged in almost a straight line; and a step of removing the substrate of the
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: August 20, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Iwamatsu, Yuichi Hirano
  • Patent number: 8481372
    Abstract: In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: July 9, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 8476733
    Abstract: A semiconductor device 100 includes: a body region 105 of a first conductivity type placed on a principal surface of a substrate 101; a silicon carbide layer 102 including a drift region 107 of a second conductivity type; a channel layer 115 of the second conductivity type formed by silicon carbide and placed on the body region 105 and the drift region 107 on a surface of the silicon carbide layer 102; a gate insulating film 111 placed on the channel layer 115; a gate electrode 113 insulated from the silicon carbide layer 102 by the gate insulating film 111; a source electrode 116 provided on the silicon carbide layer 102; and a drain electrode 114 provided on a reverse surface of the substrate 101, wherein the source electrode 116 is in contact with the body region 105 and the channel layer 115; and a second conductivity type impurity concentration on a surface of the silicon carbide layer 102 that is in contact with the source electrode 116 is less than or equal to a second conductivity type impurity concen
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: July 2, 2013
    Assignee: Panasonic Corporation
    Inventors: Kunimasa Takahashi, Chiaki Kudou
  • Patent number: 8471306
    Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: June 25, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Timothy Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
  • Patent number: 8427865
    Abstract: There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: April 23, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Akio Shima, Yoshitaka Sasago, Masaharu Kinoshita, Toshiyuki Mine, Norikatsu Takaura, Takahiro Morikawa, Kenzo Kurotsuchi, Satoru Hanzawa
  • Patent number: 8415218
    Abstract: A method of growing an epitaxial silicon layer is provided. The method comprising providing a substrate including an oxygen-terminated silicon surface and forming a first hydrogen-terminated silicon surface on the oxygen-terminated silicon surface. Additionally, the method includes forming a second hydrogen-terminated silicon surface on the first hydrogen-terminated silicon surface through atomic-layer deposition (ALD) epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. The second hydrogen-terminated silicon surface is capable of being added one or more layer of silicon through ALD epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. In one embodiment, the method is applied for making devices with thin-film transistor (TFT) floating gate memory cell structures which is capable for three-dimensional integration.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: April 9, 2013
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fumitake Mieno
  • Patent number: 8314448
    Abstract: Embodiments of a semiconductor structure include a first current electrode region, a second current electrode region, and a channel region. The channel region is located between the first current electrode region and the second current electrode region, and the channel region is located in a fin structure of the semiconductor structure. A carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: November 20, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Marius K. Orlowski, James D. Burnett
  • Patent number: 8283706
    Abstract: A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: October 9, 2012
    Assignee: SanDisk 3D LLC
    Inventors: James M. Cleeves, Roy E. Scheuerlein
  • Patent number: 8264018
    Abstract: Provided is a semiconductor memory device. The semiconductor memory device may include a local bitline extending in a direction substantially vertical to an upper surface of a semiconductor substrate and a local wordline intersecting the local bitline. The local bitline is electrically connected to a bitline channel pillar penetrating a gate of a bitline transistor, and the local wordline is electrically connected to a wordline channel pillar penetrating a gate of a wordline transistor.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: September 11, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong Sik Yoon, Jinshi Zhao, Ingyu Baek, Hyun Jun Sim, Minyoung Park
  • Patent number: 8241989
    Abstract: An integrated circuit with stacked devices. One embodiment provides a surface of a first semiconductor structure of a first crystalline semiconductor material including first and second portions. First structures are formed on the first portions. The second portions remain uncovered. Sacrificial structures of a second, different crystalline material are formed on the second portions. A second semiconductor structure of the first crystalline semiconductor material is formed over the sacrificial structures and over the first structures.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: August 14, 2012
    Assignee: Qimonda AG
    Inventor: Franz Hofmann
  • Patent number: 8207571
    Abstract: A semiconductor device having a non-volatile memory and a method of manufacturing the same are provided. The semiconductor device includes a base material and a stack structure. The stack structure disposed on the base material at least includes a tunneling layer, a trapping layer and a dielectric layer. The trapping layer is disposed on the tunneling layer. The dielectric layer has a dielectric constant and is disposed on the trapping layer. The dielectric layer is transformed from a first solid state to a second solid state when the dielectric layer undergoes a process.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: June 26, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Sheng-Chih Lai, Hang-Ting Lue
  • Patent number: 8169819
    Abstract: There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.
    Type: Grant
    Filed: January 17, 2010
    Date of Patent: May 1, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Akio Shima, Yoshitaka Sasago, Masaharu Kinoshita, Toshiyuki Mine, Norikatsu Takaura, Takahiro Morikawa, Kenzo Kurotsuchi, Satoru Hanzawa
  • Patent number: 8164165
    Abstract: A novel three dimensional wafer stack and the manufacturing method therefor are provided. The three dimensional wafer stack includes a first wafer having a first substrate and a first device layer having thereon at least one chip, a second wafer disposed above the first wafer and having a second substrate, and at least one pedestal arranged between and extending from the first substrate to the second substrate. The pedestal arranged in the device layer is used for preventing the low-k materials existing in the device layer from being damaged by the stresses.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: April 24, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Chi-Shih Chang, Ra-Min Tain, Shyi-Ching Liau, Wei-Chung Lo, Rong-Shen Lee
  • Patent number: 8148759
    Abstract: Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells using one transistor to implement a Ferroelectric FeRAM are described. Top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F2. Using a ferroelectric material as the gate insulator produces a single-transistor FeRAM cell that overcomes the industry-wide Write Disturb problem. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: April 3, 2012
    Assignee: American Semiconductor, Inc.
    Inventors: Dale G. Wilson, Douglas R. Hackler, Sr.
  • Patent number: 8131250
    Abstract: A Self-Synchronized Radio Frequency RF-Interconnect (SSRFI), based on capacitor coupling and peak detection, for vertically interconnecting active device layers in three-dimensional (3D) integrated circuits (IC), as well as wireless communication and RF signal transmission/receiving.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: March 6, 2012
    Assignee: The Regents of the University of California
    Inventors: Qun Gu, Zhiwei Xu, Jenwei Ko, Mau Chung Frank Chang
  • Patent number: 8120040
    Abstract: A device for optical communication including a substrate for mounting an IC chip, and a multilayered printed circuit board. An optical path for transmitting optical signal which penetrates the substrate for mounting an IC chip is formed in the substrate for mounting an IC chip.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: February 21, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Motoo Asai, Hiroaki Kodama, Toyoaki Tanaka
  • Patent number: 8110834
    Abstract: A three-dimensional semiconductor device includes a vertical channel pattern on the substrate, a plurality of cell gate patterns and a select gate pattern stacked on the substrate along the sidewall of the vertical channel pattern, a charge storage pattern between the vertical channel pattern and the cell gate pattern and a select gate pattern between the vertical channel pattern and the select gate pattern. The select gate pattern has a different work function from the cell gate pattern.
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: February 7, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinho Kim, Sunghoi Hur, Hansoo Kim, Younggoan Jang, Sunil Shim
  • Patent number: 8089108
    Abstract: Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F2. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: January 3, 2012
    Assignee: American Semiconductor, Inc.
    Inventors: Dale G. Wilson, Douglas R. Hackler, Sr.
  • Patent number: 8053819
    Abstract: An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Paul W. Coteus, Philip George Emma, Allan Mark Hartstein, Stephen V. Kosonocky, Ruchir Puri, Mark B. Ritter
  • Patent number: 8039900
    Abstract: The stacked semiconductor device includes a semiconductor substrate, a multi-layered insulation layer pattern having at least two insulation layer patterns and an opening, an active layer pattern formed on each of the insulation layer patterns, a first plug including single crystalline silicon-germanium, a second plug including single crystalline silicon, and a wiring electrically connected to the first plug and sufficiently filling up the opening. The insulation layer patterns are vertically stacked on the semiconductor substrate and the opening exposes an upper face of the semiconductor substrate. A side portion of the active layer pattern is exposed by the opening. The first plug is formed on the upper face of the semiconductor substrate to partially fill the opening. The second plug is partially formed on the first plug, and has substantially the same interface as that of the first plug.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: October 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Seok Kim, Kong-Soo Lee, Sang-Jin Park, Sung-Kwan Kang, Ko-Eun Lee
  • Patent number: 7982250
    Abstract: A semiconductor device is demonstrated in which a plurality of field-effect transistors is stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. Each of the plurality of filed-effect transistors has a semiconductor layer which is prepared by a process including separation of the semiconductor layer from a semiconductor substrate followed by bonding thereof over the substrate. Each of the plurality of field-effect transistors is covered with an insulating film which provides distortion of the semiconductor layer. Furthermore, the crystal axis of the semiconductor layer, which is parallel to the crystal plane thereof, is set to a channel length direction of the semiconductor layer, which enables production of the semiconductor device with high performance and low power consumption having an SOI structure.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: July 19, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Atsuo Isobe, Hiromichi Godo, Yutaka Okazaki
  • Patent number: 7964870
    Abstract: To provide a display device capable of reliably forming a resistive element formed on a substrate including pixels. A display device including at least a thin-film transistor and a resistive element on a substrate has a gate electrode, an insulating film, a semiconductor layer and a conductive layer which are sequentially stacked on the substrate, in which the resistive element is formed by using the semiconductor layer formed between end portions of wiring made of the conductive layer as a resistive body, and at least one conductive layer apart from the end portions is formed on the semiconductor layer between the end portions of wiring.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: June 21, 2011
    Assignee: Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Tsuyoshi Uchida, Hiroshi Katayanagi