With Devices Vertically Spaced In Different Layers Of Semiconductor Material (e.g., "3-dimensional" Integrated Circuit) Patents (Class 257/278)
  • Patent number: 6483148
    Abstract: A method of forming a self-aligned elevated transistor using selective epitaxial growth is described. An oxide layer is provided overlying a semiconductor substrate. The oxide layer is etched through to the semiconductor substrate to form a trench having a lower portion contacting the substrate and an upper portion having a width larger than the width of the lower portion. A silicon layer is grown within the trench using selective epitaxial growth wherein the silicon layer fills the lower portion and partially fills the upper portion. Nitride spacers are formed on the sidewalls of the trench. A polysilicon layer is deposited overlying the oxide layer and within the trench and etched back to form a gate electrode within the trench between the nitride spacers. The nitride spacers are etched away where they are not covered by the gate electrode leaving thin nitride spacers on sidewalls of the gate electrode.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: November 19, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Lap Chan, Cher Liang Cha
  • Patent number: 6465834
    Abstract: In the case of a large capacity DRAM (Dynamic Random Access Memory) of a conventional type, since a signal voltage read out from a memory cell is low, the action thereof is apt to be unstable. If a gain is added to a memory cell to obtain a large output voltage, the area for a memory cell becomes large. Accordingly, a memory cell with RAM action being stable and which requires a small area is needed. A memory cell according to the present invention is provided with MOS transistors 2, 3, 4, 5 to read out storage information, transistors 8 and 11b to write storage information, and a capacitor 11a to control the voltage at the storage node. These component parts are assembled to form a 3-dimensional structure.
    Type: Grant
    Filed: March 1, 2000
    Date of Patent: October 15, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Nakazato, Kiyoo Ito
  • Patent number: 6384442
    Abstract: A new method is provided for the creation of openings in a layer of dielectric while at the same time forming a dielectric that forms the dielectric of MIM capacitors. Under the first embodiment of the invention a layer of insulation, such as SixNy or SiON or TaN and TiN, is deposited over the surface of a semiconductor substrate, points of electrical contact have been provided in this semiconductor surface. A layer of IMD is deposited over the layer of insulation, an opening is created in the layer of IMD that aligns with and overlays a contact point over which a MIM capacitor is to be created. Under the second embodiment of the invention, a stack of three layers of a first layer of TaN followed by SiOx or SixNy followed by a second layer of TaN is used as the dielectric layer for the capacitor whereby the first layer of TaN is used as an etch stop for an opening that is etched for the creation of the upper plate of the capacitor.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: May 7, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Sheng-Hsiung Chen
  • Patent number: 6195742
    Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: February 27, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyasu Kanekawa, Hirokazu Ihara, Masatsugu Akiyama, Kiyoshi Kawabata, Hisayoshi Yamanaka, Tetsuya Okishima
  • Patent number: 6172381
    Abstract: An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed and isolated from another polysilicon structure lying in the same elevated plane. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A first transistor is provided which is disposed upon and within a silicon-based substrate. A primary interlevel dielectric is deposited across the transistor and the substrate. Polysilicon may then be deposited across the primary interlevel dielectric and doped using ion implantation. A second transistor may be formed upon and within a portion of the polysilicon layer.
    Type: Grant
    Filed: December 22, 1998
    Date of Patent: January 9, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, Daniel Kadosh
  • Patent number: 5939741
    Abstract: In one aspect, a plurality of layers are formed over a substrate and a series of first trenches are etched into a first of the layers in a first direction. A series of second trenches are etched into the first layer in a second direction which is different from the first direction. Collectively, the first and second trenches define a plurality of different substrate elevations with adjacent elevations being joined by sidewalls which extend therebetween. Sidewall spacers are formed over the sidewalls, and material of the first layer is substantially selectively etched relative to material from which the spacers are formed. Material comprising the spacer material is substantially selectively etched relative to the first material. In a preferred implementation, the etching provides a plurality of cells which are separated from one another by no more than a lateral width dimension of a previously-formed spacer.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: August 17, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Darwin A. Clampitt, James E. Green
  • Patent number: 5889293
    Abstract: Electrically conductive studs are employed to interconnect bulk active devices and SOI devices in a semiconductor device. Also provided is a method for fabricating such devices.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: March 30, 1999
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Rutten, Steven H. Voldman
  • Patent number: 5760456
    Abstract: A planar inductor structure with improved Q compatible with typical integrated circuit fabrication. The structure includes a spiral inductor with a conductive plane between the resistive substrate of the integrated circuit and the spiral inductor which reduces the power loss of the inductor. A pattern of segments may be formed in the conductive material of conductive plane to prevent eddy currents from flowing through the conductive plane and reducing the inductance of the spiral inductor. The Q of the inductor can be enhanced by optimizing the pattern in which the segmented conductive plane is formed. The segmented conductive plane may be fabricated out of metal, polysilicon or a heavily-doped region of the substrate.
    Type: Grant
    Filed: December 21, 1995
    Date of Patent: June 2, 1998
    Inventors: Andrew Z. Grzegorek, William J. McFarland
  • Patent number: 5747863
    Abstract: The infrared solid-state image pickup device of the present invention comprises a light-receiving portion formed by arranging, on a transparent substrate, light-receiving elements of a plurality of types respectively including optical cavity structures with optical distances between photoelectric conversion portions and reflecting films which are different from each other by more than 100 nm. The light-receiving elements of at least one of the plurality of types having optical cavity structures whose optical distances are set such that a valley in sensitivity exists at a predetermined wavelength within a predetermined wavelength range, light within the wavelength range being photoelectrically convertible by the light-receiving elements of other types.
    Type: Grant
    Filed: July 8, 1996
    Date of Patent: May 5, 1998
    Assignee: Nikon Corporation
    Inventor: Masahiro Shoda
  • Patent number: 5670803
    Abstract: A three-dimensional five transistor SRAM trench structure and fabrication method therefor are set forth. The SRAM trench structure includes four field-effect transistors ("FETs") buried within a single trench. Specifically, two FETs are located at each of two sidewalls of the trench with one FET being disposed above the other FET at each sidewall. Coaxial wiring electrically cross-couples the FETs within the trench such that a pair of cross-coupled inverters comprising the storage flip-flop for the SRAM cell is formed. A fifth, I/O transistor is disposed at the top of the trench structure, and facilitates access to the flip-flop. Specific details of the SRAM trench structure, and fabrication methods therefor are also set forth.
    Type: Grant
    Filed: February 8, 1995
    Date of Patent: September 23, 1997
    Assignee: International Business Machines Corporation
    Inventors: Kenneth Edward Beilstein, Jr., Claude Louis Bertin, John Edward Cronin, Francis Roger White
  • Patent number: 5612552
    Abstract: A multilevel gate array MOS-type integrated circuit structure is described wherein each source, drain, and gate electrode region in the integrated circuit structure is accessible directly through a contact opening formed normal to the plane of the underlying substrate through an overlying insulation layer.
    Type: Grant
    Filed: March 21, 1995
    Date of Patent: March 18, 1997
    Assignee: LSI Logic Corporation
    Inventor: Alexander H. Owens
  • Patent number: 5606186
    Abstract: An insulating film having a through hole aligned with an electrode on a first semiconductor element is formed on a first semiconductor substrate and a metal is disposed in the through hole. A second semiconductor element on a second semiconductor substrate is placed on the insulating film in such a way that an electrode of the second semiconductor element contacts the metal. Thus, a plurality of transistors having different performance characteristics and functions can be easily disposed adjacent to each other for improved integration.
    Type: Grant
    Filed: August 9, 1995
    Date of Patent: February 25, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Minoru Noda
  • Patent number: 5312765
    Abstract: Optoelectronic devices (16) are formed on a first surface (12) of a gallium arsenide substrate (10) using selective ion implantation. Signal processing devices may be formed on a second, opposite surface (14) of the substrate (10) using selective ion implantation (38) and/or selective epitaxy (22,24),(40). Vertical interconnects (34,46) are formed between the first and second surfaces (12,14). Alternatively, a gallium arsenide buffer layer (54) may be grown on the first surface (12) of the substrate (10), and the signal processing devices formed on the buffer layer (54) using selective ion implantation (58,60,62) and/or selective epitaxy (76,78,80,82). Dielectric (50) and/or conductive metal (52) layers may be formed on selected areas of the first surface (12), and the buffer layer (54) grown from exposed areas (56) of the first surface (12) over the dielectric (50) and/or metal (52) layers using lateral epitaxial overgrowth organometallic chemical vapor deposition.
    Type: Grant
    Filed: May 11, 1993
    Date of Patent: May 17, 1994
    Assignee: Hughes Aircraft Company
    Inventor: Hilda Kanber
  • Patent number: 5290725
    Abstract: A method for producing a semiconductor memory device including a volatile memory element, a non-volatile memory element, and a driver in combination on a silicon conductive substrate is provided. The volatile memory element is a DRAM and is disposed in and on a reverse-conductive well. A charge storage electrode layer of the DRAM is partly disposed on a transfer gate electrode layer with an insulating film sandwiched therebetween. The non-volatile memory element is a mask read-only memory and/or a programmable read-only memory.
    Type: Grant
    Filed: June 28, 1991
    Date of Patent: March 1, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kenichi Tanaka, Keizo Sakiyama