With Devices Vertically Spaced In Different Layers Of Semiconductor Material (e.g., "3-dimensional" Integrated Circuit) Patents (Class 257/278)
  • Patent number: 7956391
    Abstract: Various integrated circuit devices, in particular a junction field-effect transistor (JFET), are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: June 7, 2011
    Assignee: Advanced Analogic Technologies, Inc.
    Inventors: Donald R. Disney, Richard K. Williams
  • Patent number: 7898009
    Abstract: Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F2. Using a ferroelectric material as the gate insulator produces a single-transistor FeRAM cell that overcomes the industry-wide Write Disturb problem. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: March 1, 2011
    Assignee: American Semiconductor, Inc.
    Inventors: Dale G. Wilson, Kelly James DeGregorio, Stephen A. Parke, Douglas R. Hackler, Sr.
  • Patent number: 7892904
    Abstract: A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-silicon (MONOS) or metal-aluminum oxide-silicon (MAS) memory cell structure with one-time programmable (OTP) function. The device includes a substrate, a first dielectric layer overlying the substrate, and one or more source or drain regions embedded in the first dielectric layer with a co-planar surface of n-type a-Si and the first dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes a second dielectric layer on the a-Si p-i-n diode junction and a metal control gate overlying the second dielectric layer. Optionally the device with OTP function includes a conductive path formed between n-type a-Si layer and the metal control gate. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: February 22, 2011
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Mieno Fumitake
  • Patent number: 7884390
    Abstract: A vertically conducting semiconductor device includes a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. An epitaxial layer extends over the topside surface of the semiconductor substrate but terminates prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. An interconnect layer extends into the recessed region but terminates prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: February 8, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: John T. Andrews, Hamza Yilmaz, Bruce Marchant, Ihsiu Ho
  • Patent number: 7834402
    Abstract: To strengthen tolerance to radiation. Source and back gate of P-channel transistor P1 are connected to power supply. Gate of the P-channel transistor P1 is connected to input terminal IN. Gate of N1 is connected to IN. Drain of N1 is connected to OUT. Cathode of diode D1 is connected to power supply, anode of D1 being connected to OUT. Cathode of diode D2 is connected to OUT, anode of D2 being grounded. When seen from a direction perpendicular to a substrate on which an inverter circuit is formed, a projection plane of a region of a p+ diffusion layer of D1 includes a projection plane of a region of an n+ diffusion layer of N, and a projection plane of a region of an n+ diffusion layer of the diode D2 includes a projection plane of a region of a p+ diffusion layer of P1.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: November 16, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hideyuki Yoneda
  • Patent number: 7825446
    Abstract: There is provided a semiconductor device including, a semiconductor substrate having a circuit forming region and a peripheral region, a base insulating film formed over the semiconductor substrate, a capacitor formed of a lower electrode, a capacitor dielectric film made of a ferroelectric material, and an upper electrode in this order over the base insulating film in the circuit forming region, an uppermost interlayer insulating film formed over the capacitor, a seal ring formed over the semiconductor substrate in the peripheral region, the seal ring having a height that reaches at least the upper surface of the interlayer insulating film, and surrounding the circuit forming region, a block film formed over the seal ring and over the interlayer insulating film in the circumference of the seal ring, and an electrode conductor pattern which is formed over the interlayer insulating film in the peripheral region, the electrode conductor pattern having an electrode pad, and having a cross-section exposed to a di
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: November 2, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yasufumi Takahashi, Kenichiro Kajio
  • Patent number: 7795651
    Abstract: A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: September 14, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hun Jeong, Ki-Nam Kim, Soon-Moon Jung, Jae-Hoon Jang
  • Patent number: 7777307
    Abstract: A method for manufacturing a high-frequency signal transmission circuit includes the steps of forming a groove to surround a first region on a semiconductor substrate, filling the groove with a stopper material, forming a high-frequency transmission line on the semiconductor substrate so that the transmission line extends over the first region, and etching the first region of the semiconductor substrate using the stopper material as an etching stopper to form a recess in the first region.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: August 17, 2010
    Assignee: Sony Corporation
    Inventor: KueiSung Chang
  • Patent number: 7763915
    Abstract: The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are formed, at a top level, in a preferably monocrystalline and compression strained second semi-conducting layer of germanium having a (110) orientation. The second semi-conducting layer is transferred onto a first block in which the n-MOS transistors were previously formed, and the p-MOS transistors are then formed.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: July 27, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Jean-Pierre Joly, Olivier Faynot, Laurent Clavelier
  • Publication number: 20100148226
    Abstract: In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.
    Type: Application
    Filed: December 11, 2008
    Publication date: June 17, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Chandra Mouli
  • Patent number: 7723764
    Abstract: A method of repairing a defective one of devices mounted on substrate is provided. Devices are arrayed on a substrate and electrically connected to wiring lines connected to a drive circuit, to be thus mounted on the substrate. The devices mounted on the substrate are then subjected to an emission test. If a defective device is detected in this test, a repair device is mounted at a position corresponding to a position of the defective device. At this time, after wiring lines connected to the defective device are cut off, the repair device is electrically connected to portions of the wiring lines, the portions of the wiring lines being located at positions nearer to the drive circuit side than the cut-off positions of the wiring lines.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: May 25, 2010
    Assignee: Sony Corporation
    Inventors: Toyoharu Oohata, Toshiaki Iwafuchi, Hisashi Ohba
  • Patent number: 7671389
    Abstract: An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: March 2, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hoon Jang, Soon-Moon Jung, Young-Seop Rah, Han-Byung Park
  • Patent number: 7586135
    Abstract: Semiconductor devices including a plurality of semiconductor layers. A plurality of transistors are on each of the semiconductor layers. The transistors include gate lines and have source regions and drain regions formed between the gate lines in the respective semiconductor layer including the transistors. The semiconductor devices further include a plurality of local source line structures. Each of the local source line structures is positioned on a corresponding one of the semiconductor layers and connects a plurality of the source regions formed on the corresponding one of the semiconductor layers. Methods of forming the semiconductor devices are also provided.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: September 8, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wook-Hyun Kwon, Ki-Nam Kim, Chan-Kwang Park, Soon-Moon Jung, Sang-Pil Sim
  • Patent number: 7525137
    Abstract: There is provided a monolithic three dimensional TFT mask ROM array. The array includes a plurality of device levels. Each of the plurality of device levels contains a first set of enabled TFTs and a second set of partially or totally disabled TFTs.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: April 28, 2009
    Assignee: Sandisk Corporation
    Inventors: Andrew J. Walker, Christopher Petti
  • Patent number: 7479673
    Abstract: Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on the bulk transistor. A lower TFT may be on the first interlayer insulating layer, and a second interlayer insulating layer may be on the lower TFT. An upper TFT may be on the second interlayer insulating layer, and a third interlayer insulating layer may be on the upper TFT. A first impurity region of the bulk transistor, a first impurity region of the lower TFT, and a first impurity region of the upper TFT may be electrically connected to one another through a node plug that penetrates the first, second and third interlayer insulating layers.
    Type: Grant
    Filed: January 11, 2005
    Date of Patent: January 20, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hoon Jang, Soon-Moon Jung, Kun-Ho Kwak, Byung-Jun Hwang
  • Patent number: 7449733
    Abstract: A semiconductor device includes a semiconductor substrate, a channel region formed above the semiconductor substrate, a first gate electrode formed above the channel region via a first gate insulating film, a second gate electrode formed below the channel region via a second gate insulating film to face the first gate electrode, a first insulating film covering side surfaces of the second gate electrode, a second insulating film covering a bottom surface of the second gate electrode, and a semiconductor layer which has an upper surface positioned above an upper surface of the first gate insulating film and side surfaces facing side surfaces of the first gate electrode, and in which a source region and drain region are formed. The side surfaces of the second gate electrode are aligned with or positioned inside the side surfaces of the semiconductor layer.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: November 11, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Inaba, Tetsu Morooka
  • Patent number: 7423304
    Abstract: A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: September 9, 2008
    Assignee: Sandisck 3D LLC
    Inventors: James M. Cleeves, Roy E. Scheuerlein
  • Publication number: 20080203445
    Abstract: An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.
    Type: Application
    Filed: May 15, 2008
    Publication date: August 28, 2008
    Applicant: International Business Machines Corporation
    Inventors: Kerry Bernstein, Paul W. Coteus, Philip George Emma, Allan Mark Hartstein, Stephen V. Kosonocky, Ruchir Puri, Mark B. Ritter
  • Patent number: 7402854
    Abstract: An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: July 22, 2008
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Paul W. Coteus, Philip George Emma, Allan Mark Hartstein, Stephen V. Kosonocky, Ruchir Puri, Mark B. Ritter
  • Patent number: 7394128
    Abstract: A semiconductor memory (26) having a plurality of memory cells (25), the semiconductor memory (26) having a substrate (1), at least one wordline (2) and first (3) and second lines (4). Each memory cell (25) of the plurality of memory cells (25) includes a fin (15) of semiconductor material, the fin (15) having a top surface (5), first (6) and second (7) opposing sidewalls and first (8) and second (9) opposing ends. The fin (15) extends along a first direction (X). Each memory cell (25) also includes a charge-trapping layer (11) disposed on the first (6) and second (7) sidewalls of said fin (15), a patterned first insulating layer (10) disposed on the top surface (5) of the fin (15), wherein the first insulating layer (10) abuts the top surface (5) of the fin (15) and the charge-trapping layer (11). Each memory cell (25) also includes a first doping region (12) coupled to the first end (8) of said fin (15) and a second doping region (13) coupled to the second end (9) of the fin (15).
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: July 1, 2008
    Assignee: Infineon Technologies AG
    Inventor: Lars Bach
  • Patent number: 7388277
    Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: June 17, 2008
    Assignee: International Business Machines Corporation
    Inventors: H. Bernhard Pogge, Roy Yu, Chandrika Prasad, Chandrasekhar Narayan
  • Patent number: 7369436
    Abstract: Memory devices, arrays, and strings are included that facilitate the use of vertical floating gate memory cells in NAND architecture memory strings, arrays, and devices. NAND Flash memory strings, arrays, and devices, include vertical Flash memory cells to form NAND architecture memory cell strings and memory arrays. These vertical memory cell NAND architecture strings allow for an improved high density memory devices or arrays that can take advantage of the feature sizes semiconductor fabrication processes are generally capable of and still allow for appropriate device sizing for operational considerations.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: May 6, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Publication number: 20080023731
    Abstract: An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.
    Type: Application
    Filed: July 31, 2006
    Publication date: January 31, 2008
    Applicant: International Business Machines Corporation
    Inventors: Kerry Bernstein, Paul W. Coteus, Philip George Emma, Allan Mark Hartstein, Stephen V. Kosonocky, Ruchir Puri, Mark B. Ritter
  • Patent number: 7312487
    Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: December 25, 2007
    Assignee: International Business Machines Corporation
    Inventors: Syed M. Alam, Ibrahim M. Elfadel, Kathryn W. Guarini, Meikei Ieong, Prabhakar N. Kudva, David S. Kung, Mark A. Lavin, Arifur Rahman
  • Patent number: 7298638
    Abstract: A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating body between a drain region and a source region, and a second vertical MOS transistor merged with the sense transistor. Addressing the second vertical MOS transistor provides a means for changing a potential of the floating body of the sense transistor. The vertical gain cell can be used in a memory array with a read data/bit line and a read data word line coupled to the sense transistor, and with a write data/bit line and a write data word line coupled to the second transistor of the vertical gain cell.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: November 20, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 7288821
    Abstract: A method and device for increasing pFET performance without degradation of nFET performance. The method includes forming a first structure on a substrate using a first plane and direction and forming a second structure on the substrate using a second plane and direction. In use, the device includes a nFET stack on a substrate using a first plane and direction, e.g., (100)<110> and a pFET stack on the substrate using a second plane and direction, e.g., (111)/<112>. An isolation region within the substrate is provided between the nFET stack and the pFET stack.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: October 30, 2007
    Assignee: International Business Machines Corporation
    Inventor: Oh-Jung Kwon
  • Patent number: 7250646
    Abstract: There is provided a monolithic three dimensional TFT mask ROM array. The array includes a plurality of device levels. Each of the plurality of device levels contains a first set of enabled TFTs and a second set of partially or totally disabled TFTs.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: July 31, 2007
    Assignee: Sandisk 3D, LLC.
    Inventors: Andrew J. Walker, Christopher Petti
  • Publication number: 20070170471
    Abstract: The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are formed, at a top level, in a preferably monocrystalline and compression strained second semi-conducting layer of germanium having a (110) orientation. The second semi-conducting layer is transferred onto a first block in which the n-MOS transistors were previously formed, and the p-MOS transistors are then formed.
    Type: Application
    Filed: January 18, 2007
    Publication date: July 26, 2007
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Jean-Pierre Joly, Olivier Faynot, Laurent Clavelier
  • Patent number: 7244977
    Abstract: A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film (10) constituting the channel forming region from an n type poly-crystalline silicon film (7) constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film (10); and reducing an effective impurity concentration in the poly-crystalline silicon film (10).
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: July 17, 2007
    Assignee: Elpida Memory, Inc.
    Inventors: Tsuyoshi Tabata, Kazuo Nakazato, Hiroshi Kujirai, Masahiro Moniwa, Hideyuki Matsuoka, Teruo Kisu, legal representative, Haruko Kisu, legal representative, Satoru Haga, Teruaki Kisu, deceased
  • Patent number: 7226871
    Abstract: A method for forming a silicon oxynitride layer, suitable to be used in the production of semiconductor devices, e.g. poly-silicon thin film transistors, is provided. A plasma surface treatment is performed over a substrate after a silicon nitride/silicon oxide layer has been formed on the substrate by a glow discharge system to transform the silicon nitride/silicon oxide layer into a silicon oxynitride layer. The semiconductor device may be completely manufactured in simplex equipment. Therefore, the production time and production cost are favorably reduced.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: June 5, 2007
    Assignee: Industrial Technology Research Institute
    Inventors: Lin-En Chou, Hung-Che Ting
  • Patent number: 7217658
    Abstract: High density plasma chemical vapor deposition and etch back processes fill high aspect ratio gaps without liner erosion or further underlying structure attack. The characteristics of the deposition process are modulated such that the deposition component of the process initially dominates the sputter component of the process. For example, reactive gasses are introduced in a gradient fashion into the HDP reactor and introduction of bias power onto the substrate is delayed and gradually increased or reactor pressure is decreased. In the case of a multi-step etch enhanced gap fill process, the invention may involve gradually modulating deposition and etch components during transitions between process steps. By carefully controlling the transitions between process steps, including the introduction of reactive species into the HDP reactor and the application of source and bias power onto the substrate, structure erosion is prevented.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: May 15, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Atiye Bayman, George D. Papasouliotis, Yong Ling, Weijie Zhang, Vishal Gauri, Mayasari Lim
  • Patent number: 7183197
    Abstract: A method and apparatus for depositing a material layer onto a substrate is described. The method includes delivering a mixture of precursors for the material layer into a process chamber and depositing the material layer on the substrate at low temperature. The material layer can be used as an encapsulating layer for various display applications which require low temperature deposition process due to thermal instability of underlying materials used. In one aspect, the encapsulating layer includes one or more material layers (multilayer) having one or more barrier layer materials and one or more low-dielectric constant materials. The encapsulating layer thus deposited provides reduced surface roughness, improved water-barrier performance, reduce thermal stress, good step coverage, and can be applied to many substrate types and many substrate sizes. Accordingly, the encapsulating layer thus deposited provides good device lifetime for various display devices, such as OLED devices.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: February 27, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Tae Kyung Won, Sanjay Yadav
  • Patent number: 7141856
    Abstract: Disclosed is a semiconductor fin construction useful in FinFET devices that incorporates an upper region and a lower region with wherein the upper region is formed with substantially vertical sidewalls and the lower region is formed with inclined sidewalls to produce a wider base portion. The disclosed semiconductor fin construction will also typically include a horizontal step region at the interface between the upper region and the lower region. Also disclosed are a series of methods of manufacturing semiconductor devices incorporating semiconductor fins having this dual construction and incorporating various combinations of insulating materials such as silicon dioxide and/or silicon nitride for forming shallow trench isolation (STI) structures between adjacent semiconductor fins.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: November 28, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Deok Hyung Lee, Byeong Chan Lee, In Soo Jung, Yong Hoon Son, Siyoung Choi, Taek Jung Kim
  • Patent number: 7119385
    Abstract: A semiconductor apparatus includes a substrate, a buffer layer made of a monocrystal semiconductor material and formed on the substrate, a strained-Si layer formed on the buffer layer and having a lattice constant different from that of the buffer layer, a monocrystal insulating film formed on the strained-Si layer and made of a material having a rare earth structure with a lattice constant different from that of Si, and an electrode formed on the insulating film.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: October 10, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Usuda, Shinichi Takagi
  • Patent number: 7091604
    Abstract: A three-dimensional integrated circuit that provides reduced interconnect signal delay over known 2-dimensional systems. The three-dimensional integrated circuit also allows improved circuit cooling. The three-dimensional integrated circuit includes two or more electrically connected integrated circuits, separated by a cooling channel.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: August 15, 2006
    Assignee: Cabot Microelectronics Corporation
    Inventors: Ian W. Wylie, Heinz H. Busta, David J. Schroeder, J. Scott Steckenrider, Yuchun Wang
  • Patent number: 7030448
    Abstract: The structure of the nonvolatile memory includes a substrate having source/drain formed at unselected sides and source/drain with extension source/drain formed at other selected sides. A gate dielectric layer is formed on the substrate and a gate is formed on the gate dielectric layer. An isolation layer is formed along the surface of the gate. Spacers are formed attached on the sidewalls of the gate.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: April 18, 2006
    Assignee: Applied Intellectual Properties Co., Ltd.
    Inventor: Erik S. Jeng
  • Patent number: 7030918
    Abstract: The present invention discloses a solid-state image pickup device in which a photoelectric conversion part having a photoelectric conversion region, and a logic circuit part are formed on a semiconductor substrate, and outputs a potential change caused by the charges generated in the photoelectric conversion region, and is provided with a light shielding layer that covers the logic circuit part, and a light shielding film that defines the region of beam incidence on the photoelectric conversion region, where the light shielding film is provided closer to the semiconductor substrate than the light shielding layer.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: April 18, 2006
    Assignee: NEC Electronics Corporation
    Inventor: Yasutaka Nakashiba
  • Patent number: 6956256
    Abstract: A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating body between a drain region and a source region, and a second vertical MOS transistor merged with the sense transistor. Addressing the second vertical MOS transistor provides a means for changing a potential of the floating body of the sense transistor. The vertical gain cell can be used in a memory array with a read data/bit line and a read data word line coupled to the sense transistor, and with a write data/bit line and a write data word line coupled to the second transistor of the vertical gain cell.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: October 18, 2005
    Assignee: Micron Technology Inc.
    Inventor: Leonard Forbes
  • Patent number: 6909129
    Abstract: A magnetic random access memory includes a plurality of multi-layered memory structures that are formed within a single memory unit and connected in one of a series and a parallel configuration. Each of the plurality of multi-layered memory structures has a resistance that varies based on a magnetization direction of a ferromagnetic layer. A transistor is operatively coupled to each of the plurality of multi-layered memory structures to perform one of a memory read and a memory write operation based on a conduction state of the transistor.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: June 21, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chang Shuk Kim, Hyeok Je Jeong
  • Patent number: 6844578
    Abstract: In a semiconductor integrated circuit device in which the number of the PMOS transistors to be used is relatively larger than that of the NMOS transistors and the PMOS transistor is used as an output driver, there is provided a semiconductor integrated circuit device having excellent stability, reliability, and performance while being inexpensive, and a manufacturing method thereof. In such a semiconductor integrated circuit device, complementary MOS circuits are composed of a P-type MOSFET (36) and an N-type MOSFET (37) which are a horizontal, an output driver is composed of a P-type vertical MOSFET (38) having a trench structure, and a conductivity type of the gate electrode of the respective MOSFETs is set as a P-type.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: January 18, 2005
    Assignee: Seiko Instruments Inc.
    Inventors: Hirofumi Harada, Jun Osanai
  • Patent number: 6841813
    Abstract: There is provided a monolithic three dimensional TFT mask ROM array. The array includes a plurality of device levels. Each of the plurality of device levels contains a first set of enabled TFTs and a second set of partially or totally disabled TFTs.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: January 11, 2005
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Andrew J. Walker, Christopher Petti
  • Patent number: 6806535
    Abstract: A method of fabricating a non-volatile memory is provided. A longitudinal strip of stacked layer is formed over a substrate. The longitudinal strip is a stacked layer including a gate dielectric layer, a conductive layer and a cap layer. A buried bit line is formed in the substrate on each side of the longitudinal strip. The longitudinal strip is patterned to form a plurality of stacked blocks. Thereafter, a dielectric layer is formed over the substrate. The dielectric layer exposes the cap layer of the stacked blocks. Some cap layers of the stacked blocks are removed to expose the conductive layer underneath. A word line is formed over the dielectric layer to connect stacked blocks in the same row serially together.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: October 19, 2004
    Assignee: Macronix International Co., Ltd.
    Inventor: Ching-Yu Chang
  • Patent number: 6787825
    Abstract: A data storage/processing apparatus includes ROM and/or WORM and/or REWRITEABLE memory modules and/or processing modules provided as a single main layer or multiple main layers on top of a substrate. Transistors and/or diodes operate the apparatus. In one set of embodiments, at least some of the transistors and/or diodes are provided on or in the substrate. In another set of embodiments, at least some of the layers on the top of the substrate include low-temperature compatible organic materials and/or low temperature compatible processes inorganic films, and the transistors and/or diodes need not be disposed on or in the substrate. In a related fabricating method, the memory and/or processing modules are provided on the substrate by depositing the layers in successive steps under thermal conditions that avoid subjecting an already-deposited, processed underlying layers to static or dynamic temperatures exceeding given stability limits, particularly with regard to organic materials.
    Type: Grant
    Filed: January 2, 2001
    Date of Patent: September 7, 2004
    Assignee: Thin Film Electronics ASA
    Inventors: Hans Gude Gudesen, Per-Erik Nordal, Geirr I. Leistad, Johan Carlsson, Göran Gustafsson, Michael O Thompson
  • Publication number: 20030209739
    Abstract: It is an object of the present invention to provides a field effect transistor with extremely low leakage current. It is another object of the invention to provide a semiconductor memory device having an excellent information holding characteristic. It is a further object of the invention to provide a method for manufacturing in a simple manner a novel field effect transistor or semiconductor memory device with extremely low leakage current. According to a typical basic configuration of the present invention, a thin insulating film is inserted in a vertically disposed Schottky junction to form source and drain electrodes and a tunnel of the insulating film in the junction is controlled by a gate electrode. The gate electrode is disposed on each of both sides of a vertical channel, permitting a field effect to be exerted effectively on the junction, whereby a junction leakage in an OFF state can be made extremely low.
    Type: Application
    Filed: June 12, 2003
    Publication date: November 13, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Dai Hisamoto, Koza Katayama
  • Patent number: 6630700
    Abstract: An integrated NMOS circuit including an active stack having a plurality of isolated p-well active devices M1-M3, a bias stack having a plurality of diode-connected isolated p-well bias devices M4-M6, the gate of each of the plurality of diode-connected isolated p-well bias devices coupled to the gate of a corresponding one of the plurality of isolated p-well active devices, the bulk of each of the plurality of diode-connected isolated p-well bias devices coupled directly to the bulk of the corresponding one of the plurality of isolated p-well active devices, and the source of each of the plurality of diode-connected isolated p-well bias devices coupled directly to the bulk of the corresponding diode-connected isolated p-well bias device.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: October 7, 2003
    Assignee: Motorola, Inc.
    Inventor: Gary Kaatz
  • Patent number: 6624046
    Abstract: A multi-layered structure is fabricated in which a microprocessor is configured in different layers and interconnected vertically through insulating layers which separate each circuit layer of the structure. Each circuit layer can be fabricated in a separate wafer or thin film material and then transferred onto the layered structure and interconnected.
    Type: Grant
    Filed: November 1, 1999
    Date of Patent: September 23, 2003
    Assignee: Kopin Corporation
    Inventors: Paul M. Zavracky, Matthew Zavracky, Duy-Phach Vu, Brenda Dingle
  • Patent number: 6586284
    Abstract: The present invention relates to a silicon-on-insulator (SOI) substrate, a method for fabricating the SOI substrate and a SOI MOSFET using the SOI substrate to easily migrate the design applied to a conventional bulk silicon substrate to the SOI design and to remove a floating body effect. The SOI substrate includes a mono-silicon substrate, a buried oxide layer formed over the surface of the mono-silicon substrate, and a thin mono-silicon layer formed over the surface of the buried oxide layer. Conductive layers are formed at through holes of the buried oxide layer positioned between the predetermined regions of the thin layer and the substrate for body contacts. Therefore, additional layout spaces are not needed for body contacts and the constant body contact resistance can allow the conventional circuit design applied to die bulk silicon substrate to be migrated to the circuit design applied to the SOI substrate without any modifications.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: July 1, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Min-su Kim
  • Patent number: 6498372
    Abstract: A method and structure for conductively coupling electrical structures to a semiconductor device located under a silicon on insulator (SOI) layer. The SOI layer is formed on a bulk semiconductor substrate. A trench structure through the SOI layer is formed, wherein an end of the trench structure interfaces with the bulk semiconductor substrate. A semiconductor device is formed in the bulk semiconductor substrate, wherein the semiconductor device includes P+ and N+ diffusions. Conductive plugs are formed through the trench structure such that the conductive plugs are self-aligned with, and in conductive contact with, the diffusions. The semiconductor device in the bulk semiconductor substrate may include an electrostatic discharge device (ESD). The bulk semiconductor substrate, which has a high thermal conductivity, serves as an effective medium for dissipating heat generated by the ESD.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: December 24, 2002
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey S. Brown, Robert J. Gauthier, Jr., Jed H. Rankin, William R. Tonti
  • Patent number: 6483148
    Abstract: A method of forming a self-aligned elevated transistor using selective epitaxial growth is described. An oxide layer is provided overlying a semiconductor substrate. The oxide layer is etched through to the semiconductor substrate to form a trench having a lower portion contacting the substrate and an upper portion having a width larger than the width of the lower portion. A silicon layer is grown within the trench using selective epitaxial growth wherein the silicon layer fills the lower portion and partially fills the upper portion. Nitride spacers are formed on the sidewalls of the trench. A polysilicon layer is deposited overlying the oxide layer and within the trench and etched back to form a gate electrode within the trench between the nitride spacers. The nitride spacers are etched away where they are not covered by the gate electrode leaving thin nitride spacers on sidewalls of the gate electrode.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: November 19, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Lap Chan, Cher Liang Cha
  • Patent number: 6465834
    Abstract: In the case of a large capacity DRAM (Dynamic Random Access Memory) of a conventional type, since a signal voltage read out from a memory cell is low, the action thereof is apt to be unstable. If a gain is added to a memory cell to obtain a large output voltage, the area for a memory cell becomes large. Accordingly, a memory cell with RAM action being stable and which requires a small area is needed. A memory cell according to the present invention is provided with MOS transistors 2, 3, 4, 5 to read out storage information, transistors 8 and 11b to write storage information, and a capacitor 11a to control the voltage at the storage node. These component parts are assembled to form a 3-dimensional structure.
    Type: Grant
    Filed: March 1, 2000
    Date of Patent: October 15, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Nakazato, Kiyoo Ito